CHAPTER 1 INTRODUCTION
1.3 T HESIS O RGANIZATION
The thesis is organized as follows. Chapter 2 describes the development of analog front end circuit for biomedical signal acquisition. Descriptions of MSFEIC design are in Chapter 3. Then the circuit performance and testing platform are presented in Chapter 4.
Finally, a summary of this thesis research and future work is briefly concluded by Chapter 5.
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Chapter 2
Architecture Survey
2.1 A CMOS IC for portable EEG acquisition systems
Rui Martins et al[2]. proposed a CMOS IC for portable EEG acquisition systems in 1998.Besides low power, the key design points are high common mode rejection ratio (CMRR) and very low noise. Minimum component count is also important to reduce system weight and volume. The system includes 16 instrumentation amplifiers, one 16-to-1 analog multiplexer, a microprocessor compatible digital interface, and an internal current/voltage reference source as shown in the block diagram of Fig. 2-1.
The basic functional block diagram of current feedback amplifiers is presented in Fig.
2-2.Analyzing the input branch of this figure, we conclude that high input impedance is guaranteed by two unity gain buffers. Utilizing the current feedback, by the ratio of input impedance and output impedance to determine voltage gain, and reach high CMRR.
Fig. 2-1 IC block diagram [2]
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Fig. 2-2 Block diagram of an IA with current feedback [2]
Design the concept as the (2-1).
ref g
s
out
v v v
R
v = R ⋅ (
1−
2) +
(2-1)
But it is important to note that, contrary to the classical configuration with three operational amplifiers, there is no global feedback (from the output to the input) and that there is only one high impedance node, which simplifies the frequency compensation.
Another advantage is the CMRR do not depend on any matching of resistor values. The resistor count is also reduced, saving chip area.
They implemented a CMOS variation of [19], as with this configuration only a reduced number of stacked transistors is necessary (improving dc behavior at low voltage power supply) and only two transistors at input are needed. Also, as PMOS transistors exhibit low flicker noise for the same area, we chose them to the input as shown in Fig. 2-3.
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Fig. 2-3 Simplified IA circuit [2]
In order to realize high pass filter function, it was implemented using another
feedback loop around the output circuit, as shown in Fig. 2-4. The complete circuit of the IA is shown in Fig. 2-5.
Fig. 2-4 Feedback look realizing the high pass filter function [2]
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Fig. 2-5 Complete circuit of the IA [2]
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2.2 A CMOS analog front-end (AFE) IC for portable EEG/ECG monitoring applications
K. A. Ng and P. K. Chan proposed a CMOS analog front-end (AFE) IC for portable EEG/ECG monitoring applications in 2005[20]. The proposed AFE system chip is shown in Fig. 2-6. A promising approach is the differential difference amplifier (DDA) based non-inverting IA [21][22], which has favorable properties such as simplicity and acceptable low power dissipation. Fig. 2-7 shows the basic DDA non-inverting amplifier.
Fig. 2-6 System block diagram of the proposed AFE IC [20]
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Fig. 2-7 Non-inverting DDA for use an IA [20]
The input and output relation of non-inverting DDA is defined as (2-2). The major advantage of the DDA non-inverting amplifier over the typical IA is it requires an active amplifier and two resistors to set the instrumentation gain. In this DDA-based design, the CMRR is related to the mismatch of the input ports. Mismatch between resistors R1 and R2 only affects the gain factor, but it does not degrade the CMRR of the amplifier.
⎟⎟ ⎠
Fig. 2-8 is a circuit schematic of the PMOS differential-input chopper-stabilized differential difference amplifier (CHSDDA). It joined a chopper-stabilized skill in the circuit to reduce flicker noise and DC offset voltage.
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Fig. 2-8 Circuit schematic of the PMOS CHSDDA [20]
A new rail-to-rail input IA is proposed in Fig. 2-9, which shows the filtering circuits added to the basic chopper-stabilized DDA non-inverting amplifier for suppressing this input DC offset voltage. In this realization, two CHSDDAs are arranged in parallel configuration. Input pairs are NMOS and PMOS separately, guarantee to normal running of the circuit in any input common mode voltage. In addition, the circuit added an external RC band pass filter to eliminate noise outside the frequency bandwidth of biomedical signals.
Fig. 2-9 Proposed rail-to-rail IA [20]
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Fig. 2-10 shows the conceptual circuit block diagram of the chopper-stabilized DDA circuit. The two pairs of input differential voltage signals are modulated concurrently and translated to the current signals via the trans-conductance cells having identical trans-conductance gain of Gm.
Fig. 2-10 CHSDDA and its associated clock for the chopping switches [20]
Because the chopper-stabilized circuit utilizes clock to control the switches, it could produce the high frequency noise. In order to reduce the influence, it must join a low pass filter used to except the switch noise.
The programmable gain amplifier (PGA) provides further amplification with respect to the output of the rail-to-rail IA. To prevent the input impedance of the amplifier from loading the band pass filter output of the rail-to-rail IA, a non-inverting configuration is used. Note that the first chopper-stabilized stage inside the PGA is derived from the CHSDDA by just removing one input differential port. By digitally connecting the resistors via CMOS switches, the amplifier provides programmable voltage gain.
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2.3 Low-power Low-noise 8-channel EEG front-end ASIC for Ambulatory Acquisition Systems
Refet Firat Yazicioglu et al. proposed low-power low-noise 8-channel EEG front-end ASIC for ambulatory acquisition systems in 2006 [16]. Fig. 2-11 shows the architecture of the implemented 8-channel EEG readout front-end ASIC. Each channel of the ASIC consists of an instrumentation amplifier (IA), a spike filter (SF), a fixed gain stage, a variable gain amplifier (VGA) stage, and a channel buffer.
Fig. 2-11 Architecture of the implemented 8-channel EEG front-end ASIC [16]
The IA defines the noise level and CMRR of the channel, and filters the electrode offset. The second gain stage further amplifies the output of the IA and also serves as a differential to single-ended converter. The VGA is used to adjust the gain of the channels for different applications. A multiplexer, time multiplexes the output of each channel.
Moreover, a bias generator and a digital control circuit generate the bias currents and digital signals for the ASIC, respectively.
Fig. 2-12 shows the implemented current feedback instrumentation amplifier (CFIA) architecture. The presented CFIA consists of only 4 main parallel branches to minimize the power dissipation, and the ratio of two resistors defines the gain (R2/R1). On the other hand, flicker noise and process related mismatches still put a limit on the minimum achievable power dissipation and CMMR. A commonly used technique to eliminate
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flicker noise and to achieve high CMRR is called chopping [23]. However, conventional chopping amplifiers are inherently DC coupled devices. Fig. 2-12 shows the architecture of the implemented AC coupled chopped IA.
Fig. 2-12 CFIA architecture and the AC coupled chopped IA topology [16]
Fig. 2-13 shows the block diagram of the digital control circuit. It generates the necessary clock signals for the AC coupled chopped IA, the spike filter and the output multiplexer from a single clock input. Additionally, this block generates a sync-signal that can be used to synchronize the ASIC with an ADC. A non-overlapping clock generator supplies the chopping signal for the chopping switches of the AC coupled chopped IA.
Fig. 2-13 Block diagram of the digital control circuit [16]
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Refet Firat Yazicioglu et al. proposed a 60 uW 60 nV/ Hz readout front-end for portable bio-potential acquisition systems in 2007 [6]. The architecture of the front-end acquisition system is shown as Fig. 2-14. The readout channel of the system consists of the AC coupled chopped instrumentation amplifier (ACCIA), a chopping spike filter (CSF) stage, a digitally programmable gain stage and an output buffer.
Fig. 2-14 Architecture of the bio-potential readout front-end for the acquisition of EEG, ECG, and EMG signals [6]
The concept of the ACCIA is shown in Fig. 2-15. DC input voltage which is the offset voltage is modulated by the input chopper and copied to the terminals of R1. The voltage creates a current through R1 which is copied to R2 and defines the output voltage after demodulation by the output chopper. A trans-conductance stage GM with trans-conductance and low pass cut-off frequency fp filters the DC component of the output and converts it into current. The transfer function of the architecture is as (2-3), assuming low pass cut-off frequency of the ACCIA fLP,IA is much larger than fchop and gmR2>>1.
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Fig. 2-15 Concept of the ACCIA [6]
On the other hand, the noise of the IA is only modulated by the output chopper.
Therefore, the output noise power spectral density of ACCIA, SACCIA, can be expressed in terms of the output noise power spectral density of the IA, SIA, as (2-4).
)
If fLP,IA>>fchop and the flicker noise corner frequency of the current feedback IA is smaller than fchop/2, SIA,white [23]. As a result, while flicker noise of the current feedback IA is eliminated by chopping, the electrode offset is filtered by the feedback loop implemented by GM. Fig. 2-16 shows the implementation of the concept presented Fig. 2-15. This architecture can eliminate flicker noise, and external circuit reduces the offset voltage is presented by electrode and IA. The GM is implemented by the OTA2-Cext2 filter and the trans-conductance stage, gm2. This results in an equivalent trans-conductance of Av gm2, where Av is the voltage gain of OTA2. By replacing gm of (2-8) with Avgm2 and fp with gmOTA2/(AvCext2), high-pass cut-off frequency of the ACCIA, fHP,ACCIA, is shown as (2-5).19
Fig. 2-16 ACCIA implemented circuit [6]
OTA2 is implemented as a current mirror OTA as Fig. 2-17(a), where is reduced using a series parallel division of current [24]. The gm2 stage is implemented as a basic differential stage as Fig. 2-17(b), which acts as a voltage to current converter. The combination of the two feedback loops cancels both different electrode offset (DEO) and the IA offset.
Fig. 2-17 Schematic of OTA [6]: (a) OTA1-Cext1and OTA2-Cext2 implemented circuit (b) gm1 and gm2 implemented circuit
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Fig. 2-18 shows the complete schematic of the implemented current feedback IA.
All the current sources are implemented by paralleling the unit cascode current source, MSN1, MSN2 for NMOS current sources and MSP1, MSP2 for PMOS current sources.
Current sources I1,1 and I1,2 are implemented by combining a fixed current source and a regulated cascade current mirror. R2 is implemented with a NMOS transistor so that the gain of the IA can be continuously adjusted. The source follower stages, which consist of transistors and act as level shifters in order to maximize the input-output voltage swing of the IA.
Fig. 2-18 Schematic of current feedback IA is used in ACCIC implementation [6]
Fig. 2-19 shows the implemented chopping spike filter (CSF) stage. Before the appearance of the chopping spike, output is sampled to the capacitor and during the presence of a chopping spike, switch S is opened and output is held on the capacitor.
Fig. 2-19 Schematic of CSF and operation principle [6]
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A continuous-time variable gain amplifier (VGA) stage with digitally controllable gain is shown as Fig. 2-20. Pseudo-resistors are used in order to set the DC level at the inverting node of the OTA. The VGA transfer function of the VGA is shown as (2-6).
Fig. 2-20 Schematic of the VGA [6]
⎥ ⎦
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Chapter 3
A CMOS Mixed-Signal Front-End IC for Portable Biopotential Acquisition
System
In this chapter, the critical issues of front-end circuit and complete mixed-signal front-end integrated circuit (MSFEIC) are presented. Section 3.1 shows the overview of MSFEIC architecture. Section 3.2 describes the critical issues of front-end circuit.
Section 3.3 presents every stage of MSFEIC. The simulation results and summary are presented in Section 3.4 and 3.5, respectively.
3.1 System Architecture
This study aims to develop a bandwidth/gain tunable, low noise, low power and multi-channel mixed-signal front-end integrated circuit (MSFEIC) for patient’s biomedical signals monitoring. It amplifies the measured signals and filters other noise and makes these signals become to the meaningful information. Because the biomedical signals distribute over the very weak amplitude and very low frequency, they must be processed by MSFEIC before input the digital signal processor (DSP) to analyze.
MSFEIC is divided into four parts, that including instrumentation amplifier (IA), voltage amplifier, low-pass filter (LPF), and analog-to-digital converter (ADC).
However, the measured node of the biomedical signals is not only one node, so the MSFEIC is a multi-channel design to cooperate to measure conditions practically. The structure of the MSFEIC is shown as Fig. 3-1. It is composed of four chopper-stabilized instrumentation amplifier (CHS-IA), a four-to-one analog multiplexer, a switched-capacitor variable gain amplifier (SC-VGA), a switched-capacitor low-pass
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filter (SC-LPF), a Multi-stAge-noise-SHaping 2-1-1 tri-level sigma-delta analog-to-digital converter (MASH 2-1-1 tri-level ΣΔ ADC). In addition, MSFEIC includes a digital controlling interface with a clock generator.
Fig. 3-1 The signal flow gragh of MSFEIC
In this structure of MSFEIC, the first stage CHS-IA initially amplifies the weak biomedical signals which are received by electrodes. It defines the noise performance of the front-end. A standard IA architecture is the three-opamp IA. However, the CMRR of the three-opamp IA depends on the matching of the resistors and the need for low output impedance amplifiers results in excessive power dissipation. Thus, three-opamp IA is convenient for low-power and low-noise front-ends.
A digitally programmable gain stage with selectable gain is used to adjust the gain of the readout for different biomedical signals. Conventional gain stages use either capacitor or resistive feedback topologies, where former has consumes excessive power. In this work, a switched-capacitor topology for variable gain amplifier is applied to MSFEIC, in which input signal amplification and output load drive are separated into two different phases. This SC-VGA technique relaxes the requirement for the bandwidth and the slew rate of the operational amplifiers employed. Thus, the power consumption can be reduced.
In the last decade or so many active filters with resistors and capacitors have been replaced with a special kind of filter called a switched-capacitor filter. The switched-capacitor filter allows for very sophisticated, accurate, and tuneable analog
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circuits to be manufactured without using resistors. This is useful for several reasons.
Chief among these is that resistors are very noisy, and the circuits can be made to depend on ratios of capacitor values (which can be set accurately), and not absolute values.
Moreover, it can also perform the operation of an anti-aliasing filter.
In a complete biomedical signal sensor circuit, that must includes a analog-to-digital (ADC) converter, the incorporation of an analog-to-digital converter (ADC) allows data communication with digital devices, targeted for ultimate system-on-chip approach, with the incorporation of a digital signal processor for full function.
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3.2 Design Issues
3.2.1 Device Electronic Noise
Noise limits the minimum signal level that a circuit can process with acceptable quality. In particular, biomedical signals are very weak and susceptible to noise interference. Therefore, the input stage of biomedical signals acquisition circuit need to eliminate and popcorn noise. First of all, the need to analyze the form of noise.
Analog signals processed by integrated circuits are corrupted by two different type of noise: device electronic noise and environmental noise. We focus on device electronic noise here.
(1) Thermal Noise
Fig. 3-2 Resistor noise model
Resistance is the most common source of noise, the random motion of electrons in conductor introduces fluctuations in the voltage measured across the conductor even if the average current is zero. Thus, the spectrum of thermal noise is proportional to the absolute temperature. According to Nyquist theorem, the Effective noise power and one-sided spectral density:
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(3-1) (3-2)
where is the boltzmann constant. Equation (3-2) shows that noise spectral density is independent of frequency; thus, it is called “white noise”, as shown in Fig. 3-3.
Fig. 3-3 Noise one-sided spectral density
MOS transistors also exhibit thermal noise. The most significant source is the noise generated in in the channel. It can be proved that for long-channel MOS devices operating in saturation, the channel noise can be modeled by a current source connected between the drain and source terminals as shown in Fig. 3-4.
Fig. 3-4 Thermal noise of a MOSFET
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(2) Flicker Noise ( Noise)
Fig. 3-5 Dangling bonds at the oxide-silicon interface [25]
The interface between the gate oxide and the silicon substrate in a MOSFET entails an interesting phenomenon. Since the silicon crystal reaches an end at this interface, many “dangling” bonds appear, giving rise to extra energy states. As charge carriers move at the interface , some are randomly trapped and later released by such energy states, introducing “flicker” noise in the drain current. In addition to trapping, several other mechanisms are believed to generate flicker noise.
Unlike thermal noise, the average power of flicker noise cannot be predicted easily.
Depending on the “cleanness” of the oxide-silicon interface, flicker noise may assume considerably different values and as such varies from one CMOS technology to another.
The flicker noise is modeled as a voltage source in series with the gate and given by
(3-3)
where K is a process-dependent constant. As shown in Fig. 3-6, the noise spectral density is inversely proportional to the frequency.
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Fig. 3-6 Flicker noise spectrum
From the above discussion, in order to quantify the significance of noise with respect to thermal noise for a given device, we plot both spectral densities on the same axes (Fig. 3-7), and we can reduce noise “enough” by
1. Using “large” devices and good layout.
2. Trimming (bipolar).
3. Dynamic noise-cancellation (DNC) techniques.
Fig. 3-7 Concept of noise
For this design, DNC is a good way to eliminate noise, one for the application of continuous-time, we use the chopper stabilization technique, because it has excellent long term stability, and no additional costs for testing.
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3.2.2 Charge Injection
Charge injection occurs by channel charge when MOS switches turn off. From Fig.
3-8 we can see the channel charge flow out from the channel region of the transistor to the drain and source junctions. The channel charge of a transistor had zero drain-source voltage is given by (3-4).
(3-4)
And we derive voltage error due to charge injection is given by (3-5).
(3-5)
Switches connected to analog ground and virtual ground will cause signal -independent error because its turn-on voltage is constant. Besides these, switches connected to the signal will cause signal-dependent error which is changed with signal.
Signal-dependent error is important because it truly affects resolution of the circuit.
Therefore, How to reduce this kind of errors is the critical issue when we design switches of switched-capacitor circuit.
Fig. 3-8 Non-ideal effects of MOSFET switch.
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3.2.3 Switch Body Effect
To alleviate the body effect on a CMOS switch, we may permanently connect the body of the MOSFET to its source. However, this arrangement is not applicable to some fabrication processes. Alternatively, we use an auxiliary structure as shown in Fig. 3-9.
As the schematic shows, M3 and M4 form the main switch, while M1 and M2 forms the auxiliary switch. When clk goes low, both M1 and M3 are shut off, and the body of M3 is tied to the highest voltage in the circuit (i.e., Vdd) through the PMOS transistor M5, in order to prevent latch-up. When the clock signal clk goes high, both the main and auxiliary switches are conducting, and the body of the PMOS transistor M3 is connected to its source rather than to Vdd. As a result, its body-to-source voltage (Vbs) is constantly set to zero, and the body effect is thus removed. Also, its on-resistance is signifi cantly lowered [30].
Fig. 3-9 CMOS switch configuration.
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3.2.4 Analog Nonlinearities in Cascaded Modulator
Fig. 3-10 A cascaded fourth-order (2-1-1) modulator general form with analog
Fig. 3-10 A cascaded fourth-order (2-1-1) modulator general form with analog