CHAPTER 2 ARCHITECTURE SURVEY
2.3 L OW ‐ POWER L OW ‐ NOISE 8‐ CHANNEL EEG FRONT ‐ END ASIC FOR A MBULATORY A CQUISITION S YSTEMS
Refet Firat Yazicioglu et al. proposed low-power low-noise 8-channel EEG front-end ASIC for ambulatory acquisition systems in 2006 [16]. Fig. 2-11 shows the architecture of the implemented 8-channel EEG readout front-end ASIC. Each channel of the ASIC consists of an instrumentation amplifier (IA), a spike filter (SF), a fixed gain stage, a variable gain amplifier (VGA) stage, and a channel buffer.
Fig. 2-11 Architecture of the implemented 8-channel EEG front-end ASIC [16]
The IA defines the noise level and CMRR of the channel, and filters the electrode offset. The second gain stage further amplifies the output of the IA and also serves as a differential to single-ended converter. The VGA is used to adjust the gain of the channels for different applications. A multiplexer, time multiplexes the output of each channel.
Moreover, a bias generator and a digital control circuit generate the bias currents and digital signals for the ASIC, respectively.
Fig. 2-12 shows the implemented current feedback instrumentation amplifier (CFIA) architecture. The presented CFIA consists of only 4 main parallel branches to minimize the power dissipation, and the ratio of two resistors defines the gain (R2/R1). On the other hand, flicker noise and process related mismatches still put a limit on the minimum achievable power dissipation and CMMR. A commonly used technique to eliminate
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flicker noise and to achieve high CMRR is called chopping [23]. However, conventional chopping amplifiers are inherently DC coupled devices. Fig. 2-12 shows the architecture of the implemented AC coupled chopped IA.
Fig. 2-12 CFIA architecture and the AC coupled chopped IA topology [16]
Fig. 2-13 shows the block diagram of the digital control circuit. It generates the necessary clock signals for the AC coupled chopped IA, the spike filter and the output multiplexer from a single clock input. Additionally, this block generates a sync-signal that can be used to synchronize the ASIC with an ADC. A non-overlapping clock generator supplies the chopping signal for the chopping switches of the AC coupled chopped IA.
Fig. 2-13 Block diagram of the digital control circuit [16]
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Refet Firat Yazicioglu et al. proposed a 60 uW 60 nV/ Hz readout front-end for portable bio-potential acquisition systems in 2007 [6]. The architecture of the front-end acquisition system is shown as Fig. 2-14. The readout channel of the system consists of the AC coupled chopped instrumentation amplifier (ACCIA), a chopping spike filter (CSF) stage, a digitally programmable gain stage and an output buffer.
Fig. 2-14 Architecture of the bio-potential readout front-end for the acquisition of EEG, ECG, and EMG signals [6]
The concept of the ACCIA is shown in Fig. 2-15. DC input voltage which is the offset voltage is modulated by the input chopper and copied to the terminals of R1. The voltage creates a current through R1 which is copied to R2 and defines the output voltage after demodulation by the output chopper. A trans-conductance stage GM with trans-conductance and low pass cut-off frequency fp filters the DC component of the output and converts it into current. The transfer function of the architecture is as (2-3), assuming low pass cut-off frequency of the ACCIA fLP,IA is much larger than fchop and gmR2>>1.
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Fig. 2-15 Concept of the ACCIA [6]
On the other hand, the noise of the IA is only modulated by the output chopper.
Therefore, the output noise power spectral density of ACCIA, SACCIA, can be expressed in terms of the output noise power spectral density of the IA, SIA, as (2-4).
)
If fLP,IA>>fchop and the flicker noise corner frequency of the current feedback IA is smaller than fchop/2, SIA,white [23]. As a result, while flicker noise of the current feedback IA is eliminated by chopping, the electrode offset is filtered by the feedback loop implemented by GM. Fig. 2-16 shows the implementation of the concept presented Fig. 2-15. This architecture can eliminate flicker noise, and external circuit reduces the offset voltage is presented by electrode and IA. The GM is implemented by the OTA2-Cext2 filter and the trans-conductance stage, gm2. This results in an equivalent trans-conductance of Av gm2, where Av is the voltage gain of OTA2. By replacing gm of (2-8) with Avgm2 and fp with gmOTA2/(AvCext2), high-pass cut-off frequency of the ACCIA, fHP,ACCIA, is shown as (2-5).19
Fig. 2-16 ACCIA implemented circuit [6]
OTA2 is implemented as a current mirror OTA as Fig. 2-17(a), where is reduced using a series parallel division of current [24]. The gm2 stage is implemented as a basic differential stage as Fig. 2-17(b), which acts as a voltage to current converter. The combination of the two feedback loops cancels both different electrode offset (DEO) and the IA offset.
Fig. 2-17 Schematic of OTA [6]: (a) OTA1-Cext1and OTA2-Cext2 implemented circuit (b) gm1 and gm2 implemented circuit
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Fig. 2-18 shows the complete schematic of the implemented current feedback IA.
All the current sources are implemented by paralleling the unit cascode current source, MSN1, MSN2 for NMOS current sources and MSP1, MSP2 for PMOS current sources.
Current sources I1,1 and I1,2 are implemented by combining a fixed current source and a regulated cascade current mirror. R2 is implemented with a NMOS transistor so that the gain of the IA can be continuously adjusted. The source follower stages, which consist of transistors and act as level shifters in order to maximize the input-output voltage swing of the IA.
Fig. 2-18 Schematic of current feedback IA is used in ACCIC implementation [6]
Fig. 2-19 shows the implemented chopping spike filter (CSF) stage. Before the appearance of the chopping spike, output is sampled to the capacitor and during the presence of a chopping spike, switch S is opened and output is held on the capacitor.
Fig. 2-19 Schematic of CSF and operation principle [6]
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A continuous-time variable gain amplifier (VGA) stage with digitally controllable gain is shown as Fig. 2-20. Pseudo-resistors are used in order to set the DC level at the inverting node of the OTA. The VGA transfer function of the VGA is shown as (2-6).
Fig. 2-20 Schematic of the VGA [6]
⎥ ⎦
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Chapter 3
A CMOS Mixed-Signal Front-End IC for Portable Biopotential Acquisition
System
In this chapter, the critical issues of front-end circuit and complete mixed-signal front-end integrated circuit (MSFEIC) are presented. Section 3.1 shows the overview of MSFEIC architecture. Section 3.2 describes the critical issues of front-end circuit.
Section 3.3 presents every stage of MSFEIC. The simulation results and summary are presented in Section 3.4 and 3.5, respectively.
3.1 System Architecture
This study aims to develop a bandwidth/gain tunable, low noise, low power and multi-channel mixed-signal front-end integrated circuit (MSFEIC) for patient’s biomedical signals monitoring. It amplifies the measured signals and filters other noise and makes these signals become to the meaningful information. Because the biomedical signals distribute over the very weak amplitude and very low frequency, they must be processed by MSFEIC before input the digital signal processor (DSP) to analyze.
MSFEIC is divided into four parts, that including instrumentation amplifier (IA), voltage amplifier, low-pass filter (LPF), and analog-to-digital converter (ADC).
However, the measured node of the biomedical signals is not only one node, so the MSFEIC is a multi-channel design to cooperate to measure conditions practically. The structure of the MSFEIC is shown as Fig. 3-1. It is composed of four chopper-stabilized instrumentation amplifier (CHS-IA), a four-to-one analog multiplexer, a switched-capacitor variable gain amplifier (SC-VGA), a switched-capacitor low-pass
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filter (SC-LPF), a Multi-stAge-noise-SHaping 2-1-1 tri-level sigma-delta analog-to-digital converter (MASH 2-1-1 tri-level ΣΔ ADC). In addition, MSFEIC includes a digital controlling interface with a clock generator.
Fig. 3-1 The signal flow gragh of MSFEIC
In this structure of MSFEIC, the first stage CHS-IA initially amplifies the weak biomedical signals which are received by electrodes. It defines the noise performance of the front-end. A standard IA architecture is the three-opamp IA. However, the CMRR of the three-opamp IA depends on the matching of the resistors and the need for low output impedance amplifiers results in excessive power dissipation. Thus, three-opamp IA is convenient for low-power and low-noise front-ends.
A digitally programmable gain stage with selectable gain is used to adjust the gain of the readout for different biomedical signals. Conventional gain stages use either capacitor or resistive feedback topologies, where former has consumes excessive power. In this work, a switched-capacitor topology for variable gain amplifier is applied to MSFEIC, in which input signal amplification and output load drive are separated into two different phases. This SC-VGA technique relaxes the requirement for the bandwidth and the slew rate of the operational amplifiers employed. Thus, the power consumption can be reduced.
In the last decade or so many active filters with resistors and capacitors have been replaced with a special kind of filter called a switched-capacitor filter. The switched-capacitor filter allows for very sophisticated, accurate, and tuneable analog
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circuits to be manufactured without using resistors. This is useful for several reasons.
Chief among these is that resistors are very noisy, and the circuits can be made to depend on ratios of capacitor values (which can be set accurately), and not absolute values.
Moreover, it can also perform the operation of an anti-aliasing filter.
In a complete biomedical signal sensor circuit, that must includes a analog-to-digital (ADC) converter, the incorporation of an analog-to-digital converter (ADC) allows data communication with digital devices, targeted for ultimate system-on-chip approach, with the incorporation of a digital signal processor for full function.
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3.2 Design Issues
3.2.1 Device Electronic Noise
Noise limits the minimum signal level that a circuit can process with acceptable quality. In particular, biomedical signals are very weak and susceptible to noise interference. Therefore, the input stage of biomedical signals acquisition circuit need to eliminate and popcorn noise. First of all, the need to analyze the form of noise.
Analog signals processed by integrated circuits are corrupted by two different type of noise: device electronic noise and environmental noise. We focus on device electronic noise here.
(1) Thermal Noise
Fig. 3-2 Resistor noise model
Resistance is the most common source of noise, the random motion of electrons in conductor introduces fluctuations in the voltage measured across the conductor even if the average current is zero. Thus, the spectrum of thermal noise is proportional to the absolute temperature. According to Nyquist theorem, the Effective noise power and one-sided spectral density:
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(3-1) (3-2)
where is the boltzmann constant. Equation (3-2) shows that noise spectral density is independent of frequency; thus, it is called “white noise”, as shown in Fig. 3-3.
Fig. 3-3 Noise one-sided spectral density
MOS transistors also exhibit thermal noise. The most significant source is the noise generated in in the channel. It can be proved that for long-channel MOS devices operating in saturation, the channel noise can be modeled by a current source connected between the drain and source terminals as shown in Fig. 3-4.
Fig. 3-4 Thermal noise of a MOSFET
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(2) Flicker Noise ( Noise)
Fig. 3-5 Dangling bonds at the oxide-silicon interface [25]
The interface between the gate oxide and the silicon substrate in a MOSFET entails an interesting phenomenon. Since the silicon crystal reaches an end at this interface, many “dangling” bonds appear, giving rise to extra energy states. As charge carriers move at the interface , some are randomly trapped and later released by such energy states, introducing “flicker” noise in the drain current. In addition to trapping, several other mechanisms are believed to generate flicker noise.
Unlike thermal noise, the average power of flicker noise cannot be predicted easily.
Depending on the “cleanness” of the oxide-silicon interface, flicker noise may assume considerably different values and as such varies from one CMOS technology to another.
The flicker noise is modeled as a voltage source in series with the gate and given by
(3-3)
where K is a process-dependent constant. As shown in Fig. 3-6, the noise spectral density is inversely proportional to the frequency.
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Fig. 3-6 Flicker noise spectrum
From the above discussion, in order to quantify the significance of noise with respect to thermal noise for a given device, we plot both spectral densities on the same axes (Fig. 3-7), and we can reduce noise “enough” by
1. Using “large” devices and good layout.
2. Trimming (bipolar).
3. Dynamic noise-cancellation (DNC) techniques.
Fig. 3-7 Concept of noise
For this design, DNC is a good way to eliminate noise, one for the application of continuous-time, we use the chopper stabilization technique, because it has excellent long term stability, and no additional costs for testing.
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3.2.2 Charge Injection
Charge injection occurs by channel charge when MOS switches turn off. From Fig.
3-8 we can see the channel charge flow out from the channel region of the transistor to the drain and source junctions. The channel charge of a transistor had zero drain-source voltage is given by (3-4).
(3-4)
And we derive voltage error due to charge injection is given by (3-5).
(3-5)
Switches connected to analog ground and virtual ground will cause signal -independent error because its turn-on voltage is constant. Besides these, switches connected to the signal will cause signal-dependent error which is changed with signal.
Signal-dependent error is important because it truly affects resolution of the circuit.
Therefore, How to reduce this kind of errors is the critical issue when we design switches of switched-capacitor circuit.
Fig. 3-8 Non-ideal effects of MOSFET switch.
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3.2.3 Switch Body Effect
To alleviate the body effect on a CMOS switch, we may permanently connect the body of the MOSFET to its source. However, this arrangement is not applicable to some fabrication processes. Alternatively, we use an auxiliary structure as shown in Fig. 3-9.
As the schematic shows, M3 and M4 form the main switch, while M1 and M2 forms the auxiliary switch. When clk goes low, both M1 and M3 are shut off, and the body of M3 is tied to the highest voltage in the circuit (i.e., Vdd) through the PMOS transistor M5, in order to prevent latch-up. When the clock signal clk goes high, both the main and auxiliary switches are conducting, and the body of the PMOS transistor M3 is connected to its source rather than to Vdd. As a result, its body-to-source voltage (Vbs) is constantly set to zero, and the body effect is thus removed. Also, its on-resistance is signifi cantly lowered [30].
Fig. 3-9 CMOS switch configuration.
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3.2.4 Analog Nonlinearities in Cascaded Modulator
Fig. 3-10 A cascaded fourth-order (2-1-1) modulator general form with analog nonidealities.
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Fig. 3-10 illusfrates A cascaded fourth-order (2-1-1) modulator with analog nonidealities. The DAC nonlinearities, ed1, ed2, and ed3, are represented as additive white noises, similar to the quantization error, at the corresponding feedback path of the modulator. The coefficients, γ1, γ2, and γ3, are referred to as the leakage factors of the integrators, respectively.
Ideally, the coefficients, γ1, γ2, and γ3, are all equal to unity, and the DAC errors, ed1, ed2, and ed3, are equal to zero. In reality, mismatches in the analog components make these coefficients vary slightiy from their ideal values, causing circuit non- linearities. Therefore, efforts need to be made to alleviate these circuit nonlinearities[26].
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3.3 Circuit Design
The structure of MSFEIC is divided into four parts mainly (Fig. 3-11). The first stage is a chopper-stabilized instrumentation amplifier (CHS-IA), the second stage is a switched-capacitor variable gain amplifier (SC-VGA), the third stage is a switched- capacitor low-pass filter (SC-LPF), and the fourth stage is a cascaded fourth-order (2-1-1) sigma-delta analog-to digital converter (MASH 2-1-1 tri-level ΣΔ ADC). In addition, the circuit has four analog multiplexer to select signal paths and a digital control circuit to select different mode.
Fig. 3-11 The structure of MSFEIC
3.3.1 Chopper-Stabilized Instrumentation Amplifier (CHS-IA)
Biomedical signals are small-of the order of tens of μV-and reside at low bandwidths
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that make them susceptible to excess noise. The chopper architecture circumvents the major issues of low power designs by using closed-loop feedback with specific timing constraints. To illustrate this concept, the proposed signal flow graph for an amplifier responding to a step is illustrated in Fig. 3-12. Feedback is a well-known technique to suppress distortion and increase precision in circuits. The implementation of feedback in this application, however, required a design paradigm. Input and feedback paths around the amplifier are conveyed as ac signals that were up-modulated to the chopper modulation frequency. The ac feedback ensures that all signals passing through the front-end of the amplifier are well above the corner for the transistors. Using ac modulation also allows for input and feedback signal chain scaling to be achieved with low-noise, on-chip capacitors as opposed to resistors that potentially draw excess power and add noise to the signal chain[27].
Fig. 3-12 The signal flow gragh of CHS-IA[27]
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The chopper stabilization is an established technique for suppressing device electronic noises; the noises can be regarded as input refered noise, aggressor. At the input, a switch modulator translates input signal to the chopper frequency prior to entering the amplifier; and the chopper frequency must excess noise corner. After amplification, the signal is translated back to baseband, while shifting the noise up to the modulation frequency. Finally, the integrator filter out noise and retain the signal. The gain characteristics of the chopper-stabilized instrumentation amplifier are set by the input and feedback-switched capacitor networks. The amplifier summing node VA receives a differential signal input scaled by the capacitor (Fig. 3-13), and the gain we set in CHS-IA is 26 dB.
Fig. 3-13 The structure of CHS-IA
The structure of CHS-IA is shown as Fig. 3-13, the chopper modulator is composed of CMOS switch. To alleviate the body effect on a CMOS switch, we use the low body effect CMOS switch illustrated in section 3.2.3, the chopper amplifier in CHS-IA is a two stage amplifier with chopping switch[28], which is shown as Fig. 3-14.
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Fig. 3-14 Chopper amplifier (Two stage amplifier with chopper switch)[28]
The two stage amplifier illustrated in Fig. 3-14 is based on a fully differential folded-cascode p-type two-stage Miller-compensated configuration. with active load which also allows a large output swing. Since the opamp uses a two-stage structure and a compensation capacitor, the same switching arrangement cannot be used at the output. In fact, the compensation capacitance acts like a memory element that prohibits the opamp output to be chopped instantaneously. Instead, the output of the first stage is chopped as shown in Fig. 3-14 using two sets cascode transistors M51, M52 and M61, M62. Due to the differential structure, the common-mode output voltage of both stages needs to be regulated using common-mode feedback (CMFB). In order to avoid this extra CM amplifier, the CMFB circuit for the first stage has been replaced by the cross-coupled connection of transistors M31, M32, M41, and M42. For the second stage, a simple active CMFB circuit, shown in Fig. 3-15, is used. Although the signal characteristics are purely ac at node VA(input of chopper amplifier), the amplifier must have the proper dc biasing to ensure the appropriate amplification and demodulation of the signals. Thus, the pseudoresistor is used.
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Fig. 3-15 Active CMFB
Pre-layout simulation (1) Chopper Amplifier
Fig. 3-16 Pre-layout simulation of chopper amplifier (Corners: TT, SS, FF, FS, SF Temperature: 0 ~100 Power supply: 1.8V±10%)
Gain > 73.4 dB PM > 62.3
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(2) CHS-IA
Input testing signal
Input signal type:sine wave
Input signal frequency: 1.024 kHz (the max frequency that system to process) Input signal amplitude: 213 μV
Fig. 3-17 The output of CHS-IA in time-domain (Corners: TT, SS, FF, FS, SF Temperature: 0 ~100 Power supply: 1.8V±10%)
Fig. 3-18 The output of CHS-IA in frequency-domain (worst case)
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SPEC CHS-IA
Supply Voltage 1.8 V
Power Consumption 72.61 uW
Gain 26 dB
Nonlinearity 0.00135%
Sample Rate 65.536 Hz
Bandwidth 2 kHz
3.3.2 Switched-Capacitor Variable Gain Amplifier (SC-VGA)
The architecture of the switched-capacitor variable gain amplifier is shown as Fig.
3-19. SC-VGA is the second gain stage besides the CHS-IA. With the measured
3-19. SC-VGA is the second gain stage besides the CHS-IA. With the measured