MASH 2‐1‐1 tri‐level ΣΔ Modulator

The growing trend in biomedical signal processing is to shift more signal processing from the analog to the digital domain. This implies that the analog-to-digital converter (ADC) is moved toward the front-end system with less analog preprocessing, which makes the performance requirement more stringent.

The target performance of an ADC has at least 90-dB signal-to-noise ratio (SNR) and 100-dB spurious-free dynamic-range (SFDR) with a bandwidth exceeding 1 kHz.

This design presents a 16-b 2 kHz output-rate ADC, which achieves these performance and reduces power dissipation. This ADC development involves a key design issue. That is a sigma-delta modulator (SDM) topology feasible at a low oversampling ratio (OSR) of 32. This is important for integration with the decimation filter. The resulting sampling clock of 64 kHz makes digital switching noise easier to manage, and a cost-effective single-chip solution possible. Also, a lower sampling clock will relax speed requirements in the analog circuits, and hence reduce power dissipation. In this development, an architectural approach that combines merits of cascaded SDM structures and tri-level quantization makes all quantization noise sources negligible at 32 OSR. As a result, the entire noise budget can be given to analog noise sources to reduce analog power dissipation.

Cascaded SDM structures realize high-order noise shaping by cascading sigma- delta stages of second order or lower to avoid instability, and are suited for ADCs with low OSR. A common choice is fourth-order noise shaping implemented as a 2-1-1 cascaded SDM, as shown in Fig. 3-33

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Fig. 3-33 MASH 2-1-1 tri-level modulator with noise cancellation logic

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In a cascaded structure, the quantization noise of the preceding stage is extracted and fed to the following stage. As a result, the digital output of the following stage includes information of quantization noise for both the preceding stage and itself. By

replicating the noise transfer function of the preceding stage in the noise cancellation logic (NCL), the quantization noise can be cancelled using the digital representation.

Ideally, quantization noise of only the final stage suppressed by the total noise- shaping order appears at the SDM output, which is usually referred to as theoretical quantization noise (TQN)[31].

(3-18)

where H is the transfer function of integrator, is the quantization error of third stage.

The implementation of MASH 2-1-1 tri-level ΣΔ modulator is shown as Fig. 3-34

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ΣΔ Modulator

Fig. 3-34 The SC diagram of MASH 2-1-1 tri-level ΣΔ modulator

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The fully differential SC increased signal dynamic range (DR), higher immunity to clock and charge feed-through, and rejection to the common-mode noise. The circuit is operated with two non-overlapping clock phases, in the phase the sampling capacitors are charged, while in the phase this charge is transferred to the integrating capacitors. In an SC system, the smallest capacitor usually generates the largest thermal noise. The size of the smallest capacitor needs to be determined according to the equation, since the thermal noise injected at the input cannot be shaped. Their sizes need to be carefully selected to prevent significant SNR loss due to the thermal noise limitation.

The relationship between the modulator's SNR and its input capacitor is given by

where is the peak-to-peak value of the reference voltage , is the input capacitance, k is the Boltzmann's constant (1.381 ), T is the

temperatiire in Kelvin[32].

Conventionally, 1-b quantization has been used in the cascaded stages because of its inherent linearity. In this ADC, a signal-to-quantization-noise ratio (SQNR) substantially lower than the 90-dB SNR target is required. On the other hand, the use of the multibit quantizer requires dynamic element matching (DEM) algorithm to solve the nonlinear problem of multibit digital-to-analog converters (DACs). The DEM circuit usually consume considerable power and cost additional silicon area. Thus, we use the tri-level quantizer to meet the requirements. The structures of tri-level quantizer and SR-latch are shown as Fig. 3-35. Each stage use a tri-level quantizer and two SR-latch to generate the required output and feedback control signal.

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Fig. 3-35 Tri-level quantizer and SR-latch (i=1~3)

where Vr1= , Vr0= , the output and feedback signal of each stage are constituted by the output of two SR-latch as shown in Fig. 3-36

Fig. 3-36 The output and feedback control signal (i=1~3) of each stage

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To meet the required DC gain. Thus, usually a two-stage amplifier is needed. Fig.

3-37 shows the used opamp[28]. It is based on a fully differential folded-cascode p-type two-stage Miller-compensated configuration. The second stage is a common-source amplifier with active load which also allows a large output swing (-1.77 V~+1.77 V).

Fig. 3-37 Two stage operational amplifier

The performance of the modulator is greatiy influenced by the accuracy of its integrators, especially the one at the front input. The integrator's accuracy, defined by its fransient behavior, is govemed by the slew rate and unity-gain bandwidth of the amplifier. These two specifications are critical to the design of the modulator. The integrator's output is arranged to settle to its final value at half (50%) of the on-period of the clock, . The difference between the integrator's output at the half of and its ideal value is defined as the integration error, ε, which limits the maximum accuracy that the modulator can achieve[38-39].

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Fig. 3-38 The transient behavior for the modulator[26].

The amplifier’s slew rate can be expressed as

where ΔV is the maximum output of integrator, is the integrator’s slewing factor in percent of , and an equation associated with the amplifier's unity-gain bandwidth and its sampling frequency can be obtained as

where is the amplifier's unity-gain bandwidth in hertz, is the settling factor of the integrator in percent of , and ε is the integration error.

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The comparator is appropriate for high-speed and low-power applications, and it operates as follows. During the reset mode (i.e., is low), the outputs are connected to VDD through M9 and M10. When goes high, the comparator enters the regenerative mode and transistors M3–M8 form a positive feedback loop. As a result, the input difference voltage is amplified to a full-scale rail-to-rail output. Once the comparator makes a decision, the crosscoupled transistors M3,4 and M7,8 immediately shut down all the connections between VDD and VSS, thereby saving power. This process may be better understood by looking at Fig. 3-39: When in+ is high and in- is low, out- becomes low and out+ becomes high. As a result, M3 and M8 are on, whereas M4 and M7 are off and hence the comparator is turned off[33].

VDD

VSS

Fig. 3-39 Comparator[30]

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Pre-layout simulation

Fig. 3-40 Plot of simulated SNDR versus input level

Input testing signal:

Input signal type: sine wave

Input signal frequency: 1.024 kHz (the max frequency that system to process) Input signal amplitude: 0.82 V

Fig. 3-41 Output PSD of MASH 2-1-1 tri-level ΣΔ modulator at 64 kHz sampling rate

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SPEC ΣΔ-ADC

Supply Power 1.8 V

Power Consumption 271.7 uW

Gain 0 dB

Sample Rate 65.536 kHz

Bandwidth 1.024 kHz

SNDR 95.1 dB

Resolution 16-bit

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