CHAPTER 3 A CMOS MIXED-SIGNAL FRONT-END IC FOR PORTABLE
3.3 C IRCUIT D ESIGN
3.3.6 Wide‐Swing Constant‐Gm Cascode Biasing Circuit
The architecture of the wide-swing constant-Gm cascade biasing circuit is shown as Fig. 3-44. It can be divided into three parts: The first part is a bias loop which is composed of high-swing cascode current mirror [41] to provide a stable current source.
On the presupposition of low power consumption, the current mirror used about 1uA to drive the core circuit. The second part is a cascode bias which utilizes the current mirror to copy the current of bias loop and utilizes the cascode structure to bias voltage. The third part is a start-up circuit. Because this structure adopts the wide-swing and constant-Gm, the biasing circuit must add a start-up circuit to maintain the circuit in a correct state at any time. The concepts of the start-up circuit are low consumption and no effects on the biasing circuit. The start-up circuit will revise the voltage in order to maintain the biasing circuit in a normal operational state following the feedback during the biasing circuit only when the biasing circuit is operated abnormally.
Fig. 3-44 The architecture of the biasing circuit.
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Chapter 4
Chip Implementation, Verification and Test Platform
4.1 Design Flow
While design the suitable MSFEIC for acquiring biomedical signals, we observed the characteristics of the biomedical signals first, for example, different biomedical signals have different amplitude and frequency. Then we consulted other structures of the circuit proposed by other laboratories and the first generation AFEIC design to think that the drawbacks of design and practical applications. Revise and improve the drawbacks, and design more complete structure. And then we utilized HSPICE to design the circuit with transistor level and simulate the pre-layout simulation. After MSFEIC passed the pre-layout simulation, we utilized Laker tools to layout the circuits, verified the layout (Calibre DRC、LVS、PEX), and simulated the post-layout simulation. We checked the specification with conformability to improve the practicability of the MSFEIC. After the chip is manufactured, we will test the characteristic and analyze the different between the simulation and the result of testing. The design flow is shown as Fig. 4-1
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Fig. 4-1 Design flow
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4.2 Layout Consideration and Implementation
Analog circuits have high processing sensitivity, so we must consider the place when layout the circuit. The fundamental consideration of analog circuit layout is matching, so it should add dummy cells to protect the elements in order to reduce errors in the VLSI process. In the core circuit parts, we used a guard ring to isolate the passive elements and to avoid the surrounding noise affecting the performance of the core circuit. Therefore, we used a double-layer guard ring in the layout to isolate the core analog circuit, digital controlling circuit, and passive elements (resistors and capacitors array).
The unit capacitor is 50fF and is cut the angle of 45 degrees neatly in this design. It is composed of two metal boards (M5, M6). We utilized the unit capacitor to arrange into a necessary capacitor array, and added dummy cells, and surrounded a guard ring with six contacts. The unit high P+ poly resistor with RPO is 5kΩ. We utilized the unit resistor to arrange into a necessary resistor array, and added dummy cells, and surrounded a guard ring with six contacts.
Fig. 4-2 is the complete MSFEIC layout containing electrostatic discharge (ESD) pads. The area of the core circuit is 1.9198×1.9198 mm2. Due to the chip is composed of analog signals and digital signals circuit, layout needs to pay attention to the following notices.
(1) In order to avoid noise by the high frequency signals coupling to the analog circuit, we utilized resistors and capacitors to isolate the analog circuits and digital circuits.
(2) Separate the analog power supply and digital power supply and be distant from each other. The power supplies are used different pads to connect with outside to increase PSRR of the analog circuit.
(3) In the sensitive circuit, add one or more guard ring layers to protect the circuit from noise effects.
(4) If accuracy of resistors or capacitors is expected much, capacitors must use common centroid layout and resistors must use intersection layout.
(5) The differential input pairs, for example the differential input pair of OP, are possible symmetry in the layout.
(6) Choose the pads with ESD protection to reduce the effects of latch up.
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(7) Add dummy cells around the passive elements to avoid the imperfect etching.
Fig. 4-2 Complete MSFEIC layout.
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4.3 Post-Layout Simulation
System input testing signal:
Input signal type: sine wave
Input signal frequency: 1.024 kHz (the max frequency that system to process) Input signal amplitude: 213 uV
Fig. 4-3 output of CHS-IA
Fig. 4-4 output of SC-VGA for gain=72 dB
Fig. 4-5 output of SC-VGA for gain=66 dB
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Fig. 4-6 output of SC-VGA for gain=60 dB
Fig. 4-7 output of SC-LPF
Fig. 4-8 output of MASH 2-1-1 tri-level ΣΔ-ADC
Fig. 4-9 PSD of system output
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4.4 Specification Comparison
The specification of MSFEIC design in this thesis is shown as Table 1, Table 2, and Table 3 summarizes the comparison results among the proposed MSFEIC and the conventional designs. It can be seen that the proposed MSFEIC offers reasonable low power, high signal-to-noise ratio(SNR) performance. In terms of area size, the proposed four-channel MSFEIC is fully implemented with relative small size. Importantly, by integrating digital interface, the MSFEIC has the selectable system gain and bandwidth.
Table 1 The specification of MSFEIC.
Process Technology
TSMC 0.18um 1P6M
Pre-Simulation Post-Simulation
Supply voltage 1.8V 1.8V
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spec CHSIA SCVGA SCLPF ΣΔ-ADC
Supply voltage 1.8 V 1.8V 1.8V 1.8V
Power
consumption
72.61 uW 104uW 124.48uW modulator 271.7 uW decimation 20uW
Gain 26 dB 34~46dB 0dB 0dB
nonlinearity <0.00135% <0.0056% <0.001405% -
Gain step - 6 dB - -
Sample Rate 65.536 kHz 65.536 kHz
- 65.536 kHz
BandWidth 2 kHz 2 kHz Sampling rate / 32
1.024 kHz
SNDR(dB) - - - 95.1
Resolution - - - 16bit
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Table 2 The comparison MSFEIC (analog) with relevant papers.
Parameter Ref [1]
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Table 3 The comparison ΣΔ-ADC with relevant papers.
parameter IEEE,
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4.5 Test Platform Design
The architecture of testing the chip is shown as Fig. 4-10. Its purpose confirms that whether the chip can operate correctly or not. Test the performances of amplification, filter, and eliminating noise in the MSFEIC. The equipments of testing the chip include function generators, an oscilloscope, power supplies, etc. The testing step is as following.
(1) Adjust the power supply to proper voltage supply, and connect to the analog voltage supply (0/1.8V), digital voltage supply (0/1.8V), and ESD voltage supply (0/1.8V). In order to avoid 60Hz noise with power supply, we must add a capacitor and a resistor to filter the noise.
(2) Input the simulated biomedical signal sine wave, which is produced by the function generator, to the CHS-IA.
(3) Input voltage to digital selected input of the multiplexer to pass a channel which we want to analyze.
(4) Set the sampling frequency of SC-LPF by the function generator producing a suitable clock.
(5) Input voltage to digital selected input of the decoder to choose appropriate voltage gain by passing the resistor switch.
(6) Connect the output of SC-VGA to an oscilloscope to observe the output wave of the MSFEIC.
(7) Outputs of the multiplexer and decoder have pins. If the multiplexer or decoder is failure, input the signals to the output of the multiplexer or decoder to test other analog circuits.
(8) Calculate the various specifications utilizing logical analyzer and computer
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Fig. 4-10 Test Platform
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Chapter 5 Conclusions
5.1 Conclusion
The study realized a tunable bandwidth/gain circuit design of multi-channel biomedical signals acquisition. Focus on low power consumption and low noise. The MSFEIC is integrated on a chip, that is SoC, and it has advantages of low cost and size. It is conducive to integrate the embedded biomedical system. The feature of MSFEIC is that utilized the characteristic of self-circuit to reduce additional circuit design and area.
Multi-channel design shared a SCFLP and a PGA to reduce the area of the circuit, SCFLP utilized different clock frequency to select different bandwidth of the system, and SC-VGA utilized different CMOS switches in parallel capacitor to select different gain ratio.
5.2 Future Work
The thesis has had superiority in the biomedical signals recording system according to the result of the MSFEIC post-layout simulation. However, the MSFEIC is still worth improving further in the future. For example, reduce the phase delay in the SC-LPF, consume lower power, use battery to supply the power of MSFEIC, integrate with digital signal processing circuit, etc.
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Appendix
A. DRC Verification
上表為 DRC report 的錯誤訊息表，其中 OD.S.1 & OD.C.1 & OD.C.5 & RPO.C.3
& RPO.C.6 為 IO PAD 中的假錯，CTM.R.2 為電容假錯，可忽略。而 PO.R.3 & M1.R.1
& M2.R.1 & M4.R.1 & M5.R.1 & _M6T.R.1 是因為使用 CIC 的 cell based design 所以佈局中的 cell 還未放入佈局中，所以會造成 poly 和各層 metal 的錯誤，其 也為假錯。
B. LVS Verification
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C. Tapeout Review Form (for Full-Custom IC)
Tapeout review form 的用意在提醒設計者在設計、模擬、佈局、佈局驗證及
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4-1. 是否有作 whole chip 的 DRC 及 LVS?_____YES_______
4-2. 除了 PAD 上 DRC 的錯誤之外,內部電路及與 PAD 連接的線路是否有
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5-1-7 電阻採用哪一材質製作?____ P+ high poly resistor with RPO 單位電阻值多大? 1k Ohm
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7-3 模擬軟體 (可不只一種)? _____________________
7-4 系統整合 chip 裡之各個 block 是否曾下過線且量測符合預期規格
89
90
Instance 的結構______
8-3 由 IC Core 部份拉線到 Pad 只拉到最邊緣部分，未過於覆蓋 Pad______
9. 使用 ARM926EJ or ARM7TDMI CPU IP
9-1. 若有使用 ARM926EJ /ARM7TDMI CPU IP，請提供以下訊息以便向 ARM 原廠申請 Design ID。
使用的 CPU 種類 (ARM926EJ or ARM7TDMI) :
使用的 metal layers 的層數:
佈局中 ARM926EJ /ARM7TDMI Macro 的 cell name:
這個晶片是否為修訂版本(revision,也就是之前曾下線過相同晶片)？
若是修訂版本，前一次下線的晶片編號:
修訂版本的原因是？(例如修正 bug) 10 其他考量
10-1 是否考量測試時的輸出量測點? YES
10-2 是否考量電路之可修改性(如用 laser cut 設備) YES
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D. Tapeout Review Form (for Cell-Based IC)
Tapeout review form 的用意在提醒設計者在設計、模擬、佈局、佈局驗證及
1-1 專題名稱：A CMOS Mixed-Signal Front-End IC for Portable Biopotential Acquisition System
1-2 Top Cell 名稱： MSFEIC 1-3 使用 library 名稱：
CIC_CBDK90 v CIC_CBDK18
CBDK 版本: CBDK018_TSMC_Artisan_v2.0
是否使用 Core Cell: v 若有使用 Core Cell 型號: □hvt □rvt □
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93
3-4. Scan Chain Information Flip-Flop 共有多少個？ 772
註：若使用 Synopsys TetraMAX 來產生 ATPG pattern，請使用 set faults -fault_coverage 指令指定 TetraMAX 產生 fault coverage information 若使用 SynTest TurboScan 之 asicgen 來產生 ATPG pattern，請以 atpg pessimistic fault coverage 的值為準
9. 佈局前模擬
4-1. gate level simulation 是否有 timing violation？
有 setup time violation、 有 hold time violation
9. 實體佈局
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95 M1.R.1 M2.R.1 M4.R.1 M5.R.1 M6T.R.1 等的錯誤為數位電路部分，
所有的 cell 還未填入，所以會有此些 density 的問題。
9-2. 若有使用 ARM926EJ /ARM7TDMI CPU IP，請提供以下訊息以便向 ARM 原廠申請 Design ID。
使用的 CPU 種類 (ARM926EJ or ARM7TDMI) :
96
使用的 metal layers 的層數:
佈局中 ARM926EJ /ARM7TDMI Macro 的 cell name:
這個晶片是否為修訂版本(revision,也就是之前曾下線過相同晶片)？
若是修訂版本，前一次下線的晶片編號:
修訂版本的原因是？(例如修正 bug)