Chapter 1 Introduction
1.2 Thesis organization
We will discuss three frequency synthesizers in this thesis. The first is the one with 10GHz oscillating frequency applied to MB-OFDM UWB 5th band group while the second one is suited for 802.11a communication system and thus owns an oscillator operating at about 5GHz. The last one continues the unfinished designed work presented before which combined four systems and enabled it to receive different signals at the same time within the single chip. Down below lists details of each chapter:
Chapter 2 introduces an integer-N frequency synthesizer operates around the MB-OFDM UWB 5th band group. Occupying a 1GHz frequency tuning range and a -97dBc/Hz phase noise at 1MHz offset from the desired signal, the design verifies the possibility of a traditional architecture operates at high frequency band.
Chapter 3 is the design of an integer-N frequency synthesizer operates at 5.2GHz which suited for the application of 802.11a communication system. In this design the voltage controlled oscillator performs impressive phase noise at about -126dBc/Hz at 1MHz
offset from the carrier and 20µs settling time.
Chapter 4 fulfills the unfinished design presented before. It is a quad-bands sigma-delta fractional-N frequency synthesizer that combines 802.11a/b/g and GSM/DCS1800 systems by using only a single oscillator under the fabrication of TSMC CMOS 0.18µm. The desired frequency of each application can be successfully produced through the closed loop. In the chapter we will briefly discuss the architecture of the circuit that already published before and then display the main effort of measurements and follow-up simulations in this thesis.
All these three circuits are fabricated in TSMC CMOS 0.18µm technology and have been put into practice, thus simulation results and measurement data will listed at the bottom of each chapter.
Finally in chapter 5 we will conclude the design work presented in the thesis and discuss the possible methods to improve the circuit performance and also some new ideas available for the future design.
Chapter 2
Integer-N Frequency Synthesizer
Applied to MB-OFDM UWB 5
thband group
Ultra wide band technology brings the convenience and mobility of wireless communications to high-speed interconnects in devices throughout the digital home and office. The Federal Communications Commission (FCC) in the US has mandated that UWB radio transmissions can legally operate in the range from 3.1GHz~10.6GHz [1], at a limit transmit power of -41dBm/MHz. Designed for short-range, wireless personal area networks (WPANs), UWB is the leading technology for freeing people from wires, enabling wireless connection of multiple devices for transmission of video, audio and other high bandwidth data. Fundamentally differs from other radio frequency communications, it is unique in that it achieves wireless communication without using a sine-wave RF carrier. Instead it uses modulated high frequency low energy pulses of less than one nanosecond in duration. Since the actual transmission is physically a wavelet, some authorities consider it to be true modulated-wavelet radio [2].
A traditional UWB transmitter as shown in Fig. 2-1 works by sending billions of pulses across a very wide spectrum of frequencies several GHz in bandwidth [3]. The pulses generated by the transmitter are completely defined by their center frequency and the bandwidth. This specific signal scheme is also defined as a “carrier-based” UWB due to the separate generation of the carrier and the envelope.
The corresponding receiver then translates the pulses into data by listening for a familiar pulse sequence sent by the transmitter. Specially, UWB is defined as any radio technology having a spectrum that occupies a bandwidth 20 percent greater than the central
frequency, or a bandwidth of at least 500MHz.
Fig. 2-1 Impulse-based ultra wideband transmitter architecture
However the modern UWB systems as shown in Fig. 2-2 use other modulation techniques, such as Orthogonal Frequency Division Multiplexing (OFDM), to occupy these extremely wide bandwidths [4]. In addition, the use of multiple bands in combination with OFDM modulation can provide significant advantages to traditional UWB systems, including high spectral efficiency, inherent resilience to RF interference, robustness to multi-path, and the ability to efficiently capture multi-path energy. The multi-band OFDM approach also allows for good coexistence with narrow band systems such as 802.11a, who owns a frequency band less than 500MHz, adaptation to different regulatory environments, future scalability and backward compatibility [5].
Fig. 2-2 Transmitter Architecture of the multi-band OFDM system
The transmitter of the OFDM-UWB system architecture that operates in 3.1 to 4.6 GHz section since the other bands are preserved for later use is shown in Fig. 2-3 while the band scheme for the MB-OFDM in Fig. 2-4 shows that five logic channels are mapped out while multiple groups of bands enable multiple modes of operation for MB-OFDM devices.
Channel 1, which contains the very first three bands, is mandatory for all UWB devices and radios, used in longer range applications while channel 3 and 4 are for shorter range applications [6].
Fig. 2-3 A basic OFDM UWB System Architecture
Fig. 2-4 A multi-band OFDM band plan
2.1 Architecture [7]
In a MB-OFDM UWB system, the very wide frequency band is divided into five band groups while the 5th group divided into two frequency bands. Since frequency synthesizers designed at 10GHz such a high frequency are not popular yet, and a synthesizer that can operates from 3.1GHz~10.6GHz needs not only more control signals than usual but also raising the circuit implementation complexity. Besides, a designing work of a frequency synthesizer that covers the first four band groups is undergoing, we will try to prove that the highest band is possibly realizable by using the conventional PLL architecture.
In this chapter, a synthesizer shown in Fig. 2-5 with a varying frequency ranging from 9.5GHz~10.6GHz is designed, and a fully programmable multi-modulus frequency divider (FPMMFD) [8] scales down the oscillating frequency to meet the target we set.
Fig. 2-5 10 GHz frequency synthesizer with multi-modulus divider
2.2 10GHz VCO
Instead of using complementary cross-coupled pairs as usual, we adopt a single NMOS
couple pair fort the voltage controlled oscillator in this work and outputs two differential signals. As shown in Fig. 2-6, differential outputs can effectively alleviate the common-mode noise coupled from the substrate.
Fig. 2-6 NMOS cross-coupled VCO
Although we used to widen the output power by increasing conductance through the complementary PMOS coupled pairs, it can still be replaced by a simple architecture at high frequency, a NMOS coupled circuit, which is free from the upper operating region limits that bothers a lot under the cascoding condition. As long as well adjusting the size of NMOS can we obtain a greater output waveform.
In this design, we get rid of the traditional single-in single-out inductor often used in NMOS-only voltage controlled oscillator, and choose a center-tapped structure as shown separately in Fig. 2-7(a) [9] and Fig. 2-7(b) [10] in behalf of high Q value and improvement in economizing the circuit area. Fig. 2-8 also shows the equivalent circuit model of a traditional spiral inductor.
(a) (b)
Fig. 2-7 (a) A Traditional NMOS-only VCO
(b) A differential-in center-tapped inductor
Fig. 2-8 Equivalent circuit model of a spiral inductor
Some additional elements, varactors, are added to the circuit to modulate the oscillating frequency by their identity of voltage-controllable capacitance. There are two kinds of varactors, accumulation-mode and inversion-mode. For the latter one, when a control bit of capacitor bank is at low level, the MOS varactor has small capacitance.
Otherwise, if a control bit is set at high level, the MOS varactor will turn into large capacitance. The relationship between control voltage and capacitance is shown in Fig.
2-9(a), (b), and Fig. 2-10 is an equivalent circuit model and a practical layout of MOS varactor [11].
(a) (b)
Fig. 2-9 (a) Tuning characteristics for the accumulation-mode MOS capacitor (b) Tuning characteristics for the inversion-mode MOS capacitor
(a) (b) Fig. 2-10 (a) Equivalent circuit model of a varactor
(b) Practical layout of a varactor
Because a frequency synthesizer needs many control signals, it can not be measured on wafer. Consequently considering the load effect and parasitic effect while designing is very important. As shown in Fig. 2-11, since the output signals from the core circuit of VCO are connected to pads through the buffer first and then measured by a spectrum analyzer, the pad parasitic capacitance, bond-wire induced inductance, blocking capacitance and input resistance of the instrument are considered while simulating.
Fig. 2-11 Output stage simulation consideration of a VCO
2.3 High Speed Frequency Divider
A digital frequency divider [12] is in principle a counter. The main advantage of digital dividers over their analog counterparts is that they can be readily designed for variable division ratios and are easily cascaded to generate very large division ratios. The general characteristics of these dividers are that they are wideband and the power consumption increases with the operating frequency. However digital logic DFF (shown in Fig. 2-12(a)) will not work accurately at high frequency. We will sketch an analog-based divider in this project [13].
Dividers which fit for high frequency application are generally injection-lock frequency divider (ILFD) and current-mode logic (CML) these two types. Since that the voltage-controlled oscillator has wide frequency tuning range and ILFD not only locked within a narrow ambit but also occupies considerable area due to usage of inductors, the CML architecture will be our first priority while meditating.
So in this design, an analog DFF frequency divider based on the topology of source coupled logic (SCL) rather than injection lock is adopted owing to the circuit size consideration as shown in Fig. 2-12(b), besides, remove the tail current source can effectively improve the input frequency range about 10% and reduce the layout complexity.
Fig. 2-13 is the simulation result of a 10GHz signal pass through two cascaded dividers, as it can tell from the graph, the minimum acceptable input signal is about 500mV peak to peak.
(a) (b)
Fig. 2-12 (a) Block diagram of a divider-by-2 circuit (b) Structure of an analog DFF
Fig. 2-13 A 10GHz signal downscaled by two cascaded divide by 2 circuit
2.4 Fully programmable multi-modulus frequency divider
The most common choice of frequency dividers in frequency synthesizer are phase-switching circuit and programmable pulse-swallow counter, however these two architectures have lower flexibility. So in this design we adopt the fully programmable multi-modulus frequency divider (FPMMFD) [8] which is not only easy to be implemented, but can also effectively reduces the possibility of dividing error since that the delay time of every stage only related to next stage compared with other divider architecture.
Fully programmable multi-modulus divider is put to use in order to achieve both high-speed frequency division and moderate power consumption. It consists of 7 asynchronously cascaded dual modulus divide-by-2/3 dividers as shown in Fig. 2-14, with the first two stages assumed to operate at high frequency. Therefore, both two circuits are realized in a differential source coupled logic (SCL) and the others are accomplished as digital devices.
Fig. 2-14 Fully programmable multi-modulus frequency divider
We can vary the total division N by changing the input level of each block’s control bit (B0, B1, B2…). In this work, the VCO is designed to oscillate at 10GHz and the output signals are downscaled by two cascaded dividers, that is to say, the signal sent into the multi-modulus divider is at about 2.5GHz. Under this frequency order, the divider can be programmed to all integer values in between 128 and 255, depending on the input control bits B0…6, which are brought out from the register which will be introduced in next section, and the programmable dividing ratio is:
∑ ∑
This divider structure provides high flexibility and the simple logic of the AND/OR gates assures that the modulus signals of the last stages are produced first and given to the next stage. Thus the delay time in the critical path, the feedback of the first stage, is minimized.
As it shows in the figure above, the 2nd 2/3-divider outputs a pair of differential signals but only the positive edge is connected to the next stage. So we insert an additional differential amplifier with single output (Fig. 2-15) to connect these two stages and enlarge the signal at the same time in case of unexpected weak waveform lacks the ability to drive the following dividers.
Fig. 2-15 Differential amplifier with single ended output
As we mentioned before, in order to perform the high frequency operating at the first two dividing stages, the architecture of differential source coupled logic must be used and logic gates will embedded in it. A simple structure of a two-modulus divider is shown in Fig.
2-16 [14], and since that the parasitic capacitance has great influence upon maximum operating speed, the first stage requests for a symmetrical and accurate layout.
Fig. 2-16 Basic two-modulus divider in differential source-coupled form
2.5 Register
Owing to the great number of input signals a frequency synthesizer has, if we design a pad for every single input control signal and output signal, the chip size will be enlarged.
Furthermore, we implement a fully programmable multi-modulus frequency divider in the circuit, which needs seven control bits to adjust the division, and will again make the chip even bigger. In order to improve the drawback, a register is designed to fix the problem.
As shown in Fig. 2-17, a register is composed of seven cascaded D–type flip flops due to seven control signals a single FPMMFD needs. The control signals are input from the
node named Data, and by the clock ticking, the frequency divider can be accurately loaded.
The register not only prevents long metal lines in layout which will lead to serious parasitic effects, it also scales the chip size down by reducing the pad numbers from seven to two.
Fig. 2-17 A seven stages cascaded register
2.6 Phase/Frequency Detector
The phase detector is an architecture that generates the error signal required in the feedback loop of the synthesizer. The PFD compares the reference frequency Fref with that of the divided down VCO signals (Fvco/N) and activates the charge pumps based on the difference in phase between these two signals. It can be classified into two types: analog and digital structures, the former one includes double balanced multiplier and Gilbert cell while the latter one can be realized in exclusive-OR logic gates, two-state detector and three-state detector these three kinds. The analog type PFD is widely adopted at about hundreds MHz order, however the signal inputs to the PFD in this frequency synthesizer is down scaled by a sequence of dividers to tens MHz, for this reason, we will put digital architectures to use.
Exclusive-OR gate is the simplest circuit to realize a phase/frequency detector as shown in Fig. 2-18(a), but it has a serious drawback that can only resolve phase differences
between±π2 . Fig. 2-18(b) shows the tendency of Vd while phase error varies.
(a) (b)
Fig. 2-18 (a) XOR PFD and the timing diagram (b) Output voltage vs. phase difference
Therefore, another two different types of PFD are developed to fix the problems. As shown in Fig. 2-19(a) and Fig. 2-19(b), a two-state PFD is composed of two D-type flip flops and a single exclusive-OR, while a three-state PFD involves two D-type flip flops with asynchronous active–low reset, RN. But still, the former one only can resolve phase differences in the ± range which can not satisfy our basic requirement, and thus make π three-state PFD that has a ±2π range the first priority in this project.
(a) (b) Fig. 2-19 (a) Two-state PFD (b) Three-state PFD
Why we are so eagerly demanding for a PFD to have a ±2π resolution range? The operational characteristics of a phase/frequency detector can be separated particularly into three segments: frequency detection, phase detection, and locking mode. When two signals sent in, as long as the phase difference is greater than ±2π, the charge pump connected afterwards will output a constant current and thus make the loop filter integrate a continuously changing control voltage applied to VCO. This is so called the frequency detection and the PFD will keep on recurring until the phase difference is less than 2π.
Once the condition discussed above happened, the PFD will then turn to the mode of phase detection. In this mode, the charge pump switches between up and down depends on the two input frequencies. If the reference signal is faster than the divided one, the PFD will generates high and low level signals and force the charge pump generate a charge current to the loop filter so as to raise the oscillating frequency to catch up with the reference source, vice versa. As long as the phase difference reaches zero, the whole circuit is in the state called phase and frequency locked.
Dead zone consideration is also a significant topic when designing a PFD. The dead zone takes place while the two compared signals have only slight difference in phase, and such tiny discrepancy make the charge pump connected afterwards fail to catch up with the variation and correctly react before the D-type flip flops being reset. So a buffer stage is added between the NAND gate and the reset end as realized in Fig. 2-19(b) to hold off the reset signal until the charge pump is properly functioned. The dead zone improvement result of this circuit is shown in Fig.2-20. Besides, while operating in the phase lock state, the PFD will still output narrow spikes, occur at the frequency equal to the reference signal, due to the finite logic responding speed and will be filtered out for fear of moderating the VCO and lead to unwanted spurious noise.
Fig. 2-20 dead zone elimination simulated by MATLAB
2.7 Loop filter design
There are two types of loop filters, active and passive. Active loop filters include OP-amplifiers and are usually differential, allowing the frequency synthesizer to generate tuning voltage levels higher than the PLL IC can generate on chip. Passive loop filters are mainly R, C those passive components and often connected directly between the charge pump and the VCO to generate a control voltage that can adjust the oscillating frequency.
Loop bandwidth plays an important role in designing, not only because a high loop bandwidth will lead to the circuit fast locked, a lower one enables it to suppress spurious noise leaked from PFD and charge pump efficiently. We adopt a 3rd order loop filter as shown in Fig. 2-21 in this design, and set the phase margin to about 60 degrees for the stable consideration.
Fig. 2-21 A 3rd order loop filter
The loop filter transfer function is:
)
Locations of poles, zeros, and loop bandwidth determine the synthesizer settling time, spurious noise, and phase margin. Generally we will make the frequency difference between ωp1 and Kh equals to the difference between ωz and Kh for the consideration of maximum phase margin. There is a useful criterion shown in Fig. 2-22 to determine the value of Kh, ωp1, ωp2, and ωz, so as to derive the preliminary value of the passive component use in the loop filter. The formulas are described in detail and down below shows a simple example.
1)
= and needs to be enlarge to bypass spurious noise
Fig. 2-22 Allocation diagram of poles, zero, reference frequency and loop bandwidth
Here we assume the current outputted from the charge pump is 50µA, and Kvco is 200 MHz/V, that is to say the value of R2 is:
We use MATLAB to simulate whether those calculated values make the closed loop
We use MATLAB to simulate whether those calculated values make the closed loop