Chapter 3 802.11a Pulse-Swallow Integer-N Frequency Synthesizer
3.11 Measurement Results
3.11.1 Measurement Preparation
Since a frequency synthesizer owns a lot of output pads including supply voltage, bias voltage, input channel control signals, reference signal, and output signals, it is quite unlikely to measure the whole circuit on wafer. We design a PCB (printed circuit board) layout which graphed in Fig. 3-23 and use SMA connectors to make it possible connect the circuit to the measuring equipments. The measuring equipments for VCO and frequency synthesizer contains Agilent E5052A signal source analyzer (Fig. 3-24a at CIC), Agilent E4407B spectrum analyzer (Fig. 3-24b at CIC), HP 8563E spectrum analyzer (Fig. 3-24c at lab), HP54610B oscilloscope (Fig. 3-24d at lab), HP E3611A power supply (Fig. 3-24e at lab), and HP33120A function generator (Fig. 3-24f at lab).
While designing a PCB layout, we can tell from Fig. 3-23 that the line widths of the output signal from VCO need to be matched to 50Ω which is the interior resistance of the instruments. We also reserve extra space for bypass and DC blocking capacitors, and the chip is stuck to the board with all I/O pads bounded onto it via bond-wires. Fig. 3-25 is the practical FR4 PCB measurement circuit and the die photo is shown in Fig. 3-26.
Fig. 3-23 PCB layout of the frequency synthesizer
(a)
(b)
(c)
(d)
(e)
(f)
Fig. 3-24 (a) Agilent E5052A signal source analyzer
(b) Agilent E4407B spectrum analyzer (c) HP 8563E spectrum analyzer (d) HP54610B oscilloscope (e) HP E3611A power supply
(f) HP33120A function generator
Fig. 3-25 A practical FR4 PCB measurement circuit
Fig. 3-26 A 5.2GHz integer-N frequency synthesizer
3.11.2 Measurement Results
First we will discuss about the tuning curve and output power of the voltage controlled oscillator. We can see from Fig. 3-27 that all the banks (from 00 to 11) include the frequency range needed, namely, as long as picking up the right control bits corresponds to each bank can we make the frequency synthesizer lock successfully. In Fig. 3-28 is the comparison of tuning range between simulation and measurement at bank 10.
Fig. 3-27 Measured tuning range under different banks
Fig. 3-28 Comparison between post-simulation and measurement at bank 10
According to the graph, a successful prediction of parasitic capacitor was performed since that the central part of tuning curves are almost the same linear for both post-simulation and measurement even though there is a little difference when control voltage is nearly 0V and 1.8V.
Next we will find out the critical parameter of a voltage-controlled oscillator, phase noise. First we set the buffer’s bias voltage to 0.9V just as what has been done during the simulation to examine the phase noise at 1MHz offset from the carrier and obtain the result shown in Fig. 3-29. However the output power is smaller compared to the simulation result, we raise the bias voltage up to meet the DC analytic anticipation and come to the end which is almost the same as expected.
Fig. 3-30(a) shows the post-simulation result, Fig. 3-30(b) shows the measurement, and Fig. 3-31 is the output power spectrum showing the magnitude of -13.5dBm. Besides we can improve the phase noise by adjusting the bias voltage, consequently a value -126dBc/Hz is obtained and shown in Fig. 3-32.
Fig. 3-29 Phase noise is about -100dBc/Hz @ 1MHz with Vb=0.9V
(a)
(b)
Fig. 3-30 (a) Post-simulation phase noise is -114dBc/Hz @ 1MHz (b) Measured phase noise is -114dBc/Hz @ 1MHz
Fig. 3-31 VCO output power is -13.50dBm at 5.2GHz
Fig. 3-32 Phase noise is -126dBc/Hz @ 1MHz after adjusted
Down below in Fig. 3-33 is the measurement result of the settling time while applying a periodical clock signal to the division control bit. Since it is impossible to read the settling time from an oscilloscope directly due to the locking time ranges at micro-seconds, we have to observe the transient by switching the total division through a function generator.
As which can be distinguished that the settling time is just a little bit longer than 20µs which derived from the simulation. The control voltage is stably locked at about 40µs. Tab.
3-4 shows the comparison between the simulation and the measurement results while Tab.
3-5 is the comparison with the references.
Fig. 3-33 Settling time of the close loop
Tab. 3-4 Comparison between simulation and measurement
Spec. Simulation Measurement
Tuning Range 4.95GHz~5.82GHz 4.98GHz~5.73GHz Phase noise -114dBc/Hz @ 1MHz -126dBc/Hz @ 1MHz
Settling time 20us ~20us
VCO output power -9.9dBm -13.5dBm
Power dissipation 18.844mW 26.35mW
Tab. 3-5 Comparison between reference papers and this work
Reference [16] 2005 [19] 2005 [17] 2003 [8] 2003 This work
Frequency band (GHz) N/A 4.11~4.35 5.15~5.70 5.15~5.82 4.98~5.73
Tuning range N/A 5.64% 27.2% N/A 14.42%
Phase noise
-125dBc/Hz ( @3MHz)
-139dBc/Hz ( @20MHz)
-116dBc/Hz ( @1MHz)
-106dBc/Hz ( @1MHz)
-126dBc/Hz ( @1MHz) Divider architecture Fractional-N Integer-N Integer-N Fractional-N Integer-N
Reference frequency N/A 16MHz 10MHz 19MHz 10MHz
Settling time 25us N/A 100us 520us 20us
Power consumption 54mW 9.68mW 13.5mW N/A 26.35mW
Supply voltage 1.8V 1.0V 2.5V 1.8V 1.8V
Manufacturing process 0.18um 0.18um 0.25um 0.18um 0.18um
Chapter 4
Conclusions and Future Works
4.1 Conclusions
We have presented a frequency synthesizer that applied to MB-OFDM UWB 5th band group. Throughout the design, each component is accomplished in the traditional architecture in order to testify the possibility for an ordinary circuit to operate at high frequency. A differential-in center-tapped inductor is adopted while designing a 10GHz VCO not only for the chip area consideration but also anxiety for high Q value and impressive performance in phase noise. Only NMOS cross-coupled pairs are used instead of NP cascaded structure as mostly seen prevents the upper voltage limitation occurs a lot in the latter one and make it easier to design.
Fully programmable multi-modulus frequency divider is consists of 7-stage cascaded divide by 2/3 circuits with varying division from 128 to 159 and is used to scaled down the operating frequency for the phase/frequency detector to compared with the reference signal.
A register is designed to load all the divider control signals since that preparing each control path a pad will lead to extremely large chip size. The VCO is simulated to have a 1000mV peak-to-peak voltage swing at 10GHz and -5.79dBm output power. The tolerant frequency range varies from 9.29GHz to 10.9GHz due to adjustment of two-pairs of varactors, besides it owns a -97dBc/Hz phase noise at 1MHz and a settling time at about 25us.
After that we introduce an integer-N frequency synthesizer applied to IEEE 802.11a. In the design a cascode NMOS and PMOS cross-coupled pairs forms the core circuit of the voltage controlled oscillator, only a single dual modulus frequency is adopted in order to
lower power consumption. A pulse-swallow counter is designed to control the switching mechanism of the dual modulus frequency divider by comparing the internal proceeding signal with the external setting control bits. The loading number is set to be 28 instead of 32 due to extra clocks needed during the comparison takes place.
The tuning range measurement results are very alike to the simulations although shift down slightly. This may results from the neglect of parasitic inductors which come from the overlong metal line connected to the output pad while simulating. It can be solved henceforward by using other simulation software such as SONNET. The measuring phase noise comes to the best at about -126dBc/Hz after adjusting the power supply and the bias voltage with resulting output power -13.5dBm at 5GHz. And the settling time is closely 20us with one of the division control bit connected to the function generator.
4.2 Future works
In spite of a frequency synthesizer applied to 802.11a has already been successfully fabricated, there are still some space left for improvement. Scaling the chip size down and efficiently suppress the power dissipation are good aspects since which can be clearly told from the layout shown before that some space is wasted by some overlong control signal paths and dummy. Furthermore, we can try to lower down the supply voltage to 1V and modified the circuit architecture to reduce power consumption. So a more compact chip with lower power dissipation can be expected.
Besides that, the pulse-swallow counter we adopted in this design actually existing some problems while putting into practice. Time delay consideration and clock control which easily vary as seen while during simulation determine whether the counter derives
the right compared signal or not. Consequently finding new substitute architectures or taking every possible problem into consideration will enhance the possibility for a circuit to functions well.
Ultra wide-band systems have recently received a great deal of interest due to their potential for high-speed wireless communication. Not only offers a promising solution to the RF spectrum drought by allowing new services to coexist with current radio systems with minimal or no interference, but also brings the advantage of avoiding the expensive spectrum licensing fees that providers of all other radio services must pay. In IEEE 802.15.3a, multi-band orthogonal frequency division multiplexing (MB-OFDM) with fast frequency hopping is proposed as a means of high bit-rate wireless communication in the UWB spectrum.
As the result, a proper transceiver design that applied to UWB system will be one of the main streams in the future. Although some articles mentioned that they are almost getting this job done, make it more complete and even better are still moving forward and needs great devotion. How to map out a well-performance frequency synthesizer that can carry out stable oscillating frequency varying from the lowest band group 3.1GHz to the highest one 10.6GHz and come to the specifications required by the system is our next objective.
Reference
[1] Evan R. Green and Sumit Roy, “System Architectures for High-rate Ultra-wideband Communication Systems: A Review of Recent Developments”, Intel Labs 2111 NE 25th Ave. Hillsboro, OR97124
[2] Behzad Razavi, Turgut Aytur, Christopher Lam, Fei-Ran Yang, Kuang-Yu (Jason) Li, Ran-Hong (Ran) Yan, Han-Chang Kang, Cheng-Chung Hsu,and Chao-Cheng Lee, “A UWB CMOS Transceiver”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005
[3] Julien Ryckaert, Claude Desset, Vincent de Heyn, Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Bert Van Poucke “Ultra-Wideband Transmitter for Wireless Body Area Network”, IMEC, Kapeldreef, 75 B-3001 Leuven Belgium
[4] Anuj Batra, Jaiganesh Balakrishnan, and Anand Dabak, “Multiband OFDM: Why it Wins for UWB”, Texas Instruments, 2006
[5] S. M. Sajad Sadough, Mahieddine M. Ichir, Emmanuel Jaffrot and Pierre Duhamel,
“Multiband OFDM UWB Channel Estimation Via A Wavelet Based EM-MAP Algorithm”, SPAWC, 2006, Juillet France
[6] Dr. Anuj Batra, “Multi-Band OFDM: Achieving High Speed Wireless Communications” Texas Instruments, August 22, 2004.
[7] Geum-Young Tak; Seok-Bong Hyun; Tae Young Kang; Byoung Gun Choi; Seong Su Park, “A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications”, Solid-State Circuits, IEEE Journal of Volume 40, Issue 8, Aug. 2005 Page(s):1671 - 1679 Digital Object Identifier 10.1109/JSSC.2005.852421.
[8] Detlev Theill, Christian Durdodt, Andre Hanke, Stefan Heinen, Stefan van Waasen, Dietolf Seippel, Duyen Pham-Stabner, Klaus Schumacher, “A Fully Integrated CMOS
Frequency Synthesizer for Bluetooth”, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.103-106, Phoenix, Arizona, USA., May 20-22, 2001
[9] N.Pavlovic, J.Gosselin, K.Mistry, D.Lelnaerts, “A 10GHz Frequency Synthesizer for 802.11a in 0.18um CMOS”, 21-23 Sept. 2004 Page(s):367 – 370, Digital Object Identifier 10.1109/ESSCIR.2004.1356694
[10] C.B. Sia, K.W. Chan, C.Q. Geng, W. Yang, K.S. Yeo, M.A. Do, J.G.. Ma, S. Chu, K.W. Chew, “An Accurate and scalable Differential Inductor Design Kit”, 22-25 March 2004 Page(s):63 – 68
[11] Pietro Andreani, Sven Mattisson, “On the Use of MOS Varactors in RF VCO’s”, IEEE Journal of Solid-State Circuits, Volume 35, Issue 6, June 2000 Page(s):905 - 910 Digital Object Identifier 10.1109/4.845194.
[12] Thomas H.Lee, Hamid R.Rategh, “Multi-GHz Frequency Synthesis & Division:
Frequency Synthesizer Design for 5GHz Wireless LAN Systems”, Kluwer Academic Publishers, 2001
[13] C. Lam, B. Razavi, “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-µm CMOS technology”, IEEE Journal of Solid-State Circuits, Volume 35, Issue 5, May 2000 Page(s):788 - 794 Digital Object Identifier 10.1109/4.841508
[14] N. Foroudi, T.A Kwasniewski, “CMOS High-Speed Dual-Modulus Frequency Divider For RF Frequency Synthesis”, IEEE Journal of Solid-State Circuits, Volume 30, Issue 2, Feb. 1995 Page(s):93 - 100 Digital Object Identifier 10.1109/4.341735.
[15] Jung-Eim Lee; Eun-Chul Park; Choong-Yul Cha; Hyun-Su Chae; Chun-Deok Suh;
Jeongwook Koh; Hanseimg Lee; Hoon-Tae Kim,” A frequency synthesizer for UWB transceiver in 0.13/spl mu/m CMOS technology”, Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on 18-20 Jan.
2006 Page(s):4 pp. Digital Object Identifier 10.1109/SMIC.2005.1587974
[16] Weilun Shen, Kangmin Hu, Xiaofeng Yi, Ye Zhou, Zhiiang Hong, “A 5GHz CMOS
monolithic fractional-N frequency synthesizer”, ASIC 2005, ASICON 2005. 6th International Conference on Volume 2, 24-27 Oct. 2005 Page(s):624 – 627.
[17] Herzel, F, Fischer, G.; Gustat, H. ”An integrated CMOS RF synthesizer for 802.11a wireless LAN”, IEEE Journal of Solid-State Circuits, Volume 38, Issue 10, Oct. 2003 Page(s):1767 - 1770 Digital Object Identifier 10.1109/JSSC.2003.817601.
[18] Marsolais, A.; El-Gamal, M.N.; Sawan, M. “A CMOS frequency synthesizer covering the lower and upper bands of 5GHz WLANs”, Circuits and Systems, 2003. MWSCAS 2003, Proceedings of the 46th IEEE International Midwest Symposium on Volume 3, 27-30 Dec. 2003 Page(s):1146 - 1149 Vol. 3
[19] Leung, L.L.K.; Luong, H.C. ”A 1-V, 9.7mW CMOS frequency synthesizer for WLAN 802.11a transceivers”, VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on 16-18 June 2005 Page(s):252 - 255 Digital Object Identifier 10.1109/
VLSIC.2005.1469379.
[20] Yan Dan Lei, “A low power CMOS 2.4-GHz monolithic integer-N synthesizer for wireless sensor”, Radio-Frequency Integration Technology: Integrated Circuits for Wideband Communication and Wireless Sensor Networks, 2005. Proceedings. 2005 IEEE International Workshop on 30 Nov.-2 Dec. 2005 Page(s):219 - 222 Digital Object Identifier 10.1109/RFIT.2005.1598915
[21] Mano, M., “Digital Design: Second Edition”, Prentice-Hall Inc., USA, 1991.
[22] Sulaiman, M.S.; Khan, N ”A novel low-power high-speed programmable dual modulus divider for PLL-based frequency synthesizer”, Semiconductor Electronics, 2002.
Proceedings. ICSE 2002. IEEE International Conference on 19-21 Dec. 2002 Page(s):77 - 81 Digital Object Identifier 10.1109/SMELEC.2002.1217779
[23] Ali, S. Margala, M. “A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time”, Circuits and Systems, 2004. ISCAS 2004. Proceedings of the 2004 International Symposium on Volume
4, 23-26 May 2004 Page(s):IV - 237-40 Vol.4.
[24] Rahul Magoon, Alyosho Molnar, Jeff Zachan, Geoff Hatcher, Woogeun Rhee, “A Single-Chip Quad-Band (850/900/1800/1900 MHz) Direct Conversion GSM/GPRS RF Transceiver with Integrated VCOs and Fractional-N Synthesizer”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002
[25] Rogers, J.W.M., Cavin, M, Dai, F. and Rahn, D., “A ∆Σ Fractional-N Frequency Synthesizer with Multi-Bands PMOS VCOs for 2.4GHz and 5GHz WLAN Applications”, European Solid-States Circuits, pp.651-654, Sep. 16-18, 2003.
[26] Pengfei Zhang; Der, L.; Dawei Guo; Sever, I.; Bourdi, T.; Lam, C.; Zolfaghari, A.;
Chen, J.; Gambetta, D.; Baohong Cheng; Gowder, S.; Hart, S.; Huynh, L.; Nguyen, T.;
Razavi, B.; “A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-/spl mu/m CMOS”, IEEE Journal of Solid-State Circuits, Volume 40, Issue 9, Sept. 2005 Page(s):1932 – 1939.
[27] R. Magoon and A. Molnar, “RF local oscillator path for GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation,” 2002 RFIC Symp. Dig. Papers, RFIC, Seattle, WA, 2002.
[28] Bram De Muer and Michiel Steyaert, “CMOS Fractional-N Synthesizers-Design for High Spectral Purity and Monolithic Integration,” Kluwer Academic Publisher, 2003.
[29] Rogers, J.W.M.; Dai, F.F.; Cavin, M.S.; Rahn, D.G, ”A multiband /spl Delta//spl Sigma/
fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC”, IEEE Journal of Solid-State Circuits Volume 40, Issue 3, Mar 2005 Page(s):678 - 689 Digital Object Identifier 10.1109/JSSC.2005.843604
[30] Wei-Zen Chen; Jia-Xian Chang; Ying-Jen Hong; Meng-Tzer Wong; Chien-Liang Kuo,
“A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-/spl mu/m digital CMOS process”, IEEE Journal of Solid-State Circuits Volume 39, Issue 1, Jan. 2004 Page(s):234 - 237 Digital Object Identifier 10.1109/JSSC.2003.820878.
Chapter 5 Appendix
Highly Integrated Quad-Bands Σ∆
Fractional-N Frequency Synthesizer
As modern GSM cell phones become more and more popular, the critical factors in their manufacture become cost, size, and time to the market [24]. Another important integration is the wireless local area network (WLAN) used most in data communications.
Although system integration is a trend nowadays, and the high integration of radio ICs also reduces board area and complexity while cutting component cost and system design time, there are still a lot of discrepancies between these two different communication systems such as channel bandwidth, data rates, and central frequency, etc. thus make it difficult for the applications come to the market. In this chapter we will discuss and design a quad-bands frequency synthesizer that can fit to the system specification of 802.11a/b/g, DCS 1800, and GSM 900 by frequency division switching and fractional-N Σ∆ modulation methods. Down below in Tab. 5-1 shows the specifications for WLAN, DCS 1800, and GSM 900 standards.
Tab. 5-1 System Specifications
IEEE 80211a IEEE 802.11 b/g DCS 1800 GSM 900 RF Frequency 5.15~5.35 GHz 2.4~2.483 GHz 1710~1880 MHz 890~960 MHz
Channel Bandwidth
20MHz 20MHz 200KHz 200KHz
Phase Noise -110 @1MHz -110 @1MHz -116 @600KHz -121 @600KHz
Locking Time < 200µs < 200µs N/A N/A
5.1 Traditional Architecture
Integration between different systems has already draw lots of intension recently. There are two ways to realize a multi-bands circuit: frequency doubling/dividing and dual VCOs.
We will discuss separately in the next sections.
5.1.1 Dual VCOs frequency synthesizer
There are many ways to reach the goal of multi-bands frequency synthesizer, and one of them is by adopting dual voltage controlled oscillators as shown in Fig. 5-1 [25]. In this design, since two oscillators operate at different oscillating frequency are placed in the circuit to make it multi-bands, the whole chip size will consequently enlarged due to inductors’ great dimension. Therefore, under the consideration of economic cost, this topology will be the last choice among our design forethought in spite of their great power due to directly output from oscillators. In Tab. 5-2 are the performance of the circuit.
Fig. 5-1 Architecture of a multi-bands frequency synthesizer
Tab. 5-2 Summary of synthesizer performance
Specification Performance High VCO tuning range 4.93GHz~5.35GHz
Med VCO tuning range 4.47GHz~4.91GHz Low VCO tuning range 3.52GHz~3.87GHz VCO phase noise -120dBc/Hz @ 1MHz In band phase noise -93dBc/Hz Loop corner frequency 150KHz
Reference frequency 40MHz Channel resolution 1MHz
Reference spurs -56dBc
Power supply 2.75V
Current consumption 84mA
5.1.2
Multi-bands frequency synthesizer by doubling/dividing
As shown in Fig. 5-2 are the circuit blocks of a frequency synthesizer that reach the goal of multi-bands switching by adopting a divide-by-3 divider and a multiply-by-2 multiplier. The voltage controlled oscillator is designed to oscillate during the frequency range 1245MHz to 1650MHz. After passing through a buffer, the oscillating signal will divide by three, thus produce a frequency f1 between 451MHz to 550MHz. Finally a multiplier makes it possible to realize a triple-bands frequency synthesizer by double the output signal from the divider. The circuit performances are summarized in Tab. 5-3.
Fig. 5-2 Triple-bands frequency synthesizer
Tab. 5-3 Synthesizer summary
Specification Performance Tuning range 1250MHz~1650MHz
Resolution 3Hz
Settling time 175µs Phase noise @ 100KHz -106dBc/Hz Phase noise @ 400KHz -124dBc/Hz Phase noise @ 3MHz -141dBc/Hz
Bias current 28mA
5.2 System Adjustment
We will discuss adjustments needed while integrating those discrepancies between each system, by this way, it will be more distinct to make the design complete.
5.2.1 Frequency bands consideration
The most difficult in combing different systems is to adjust frequency bands, phase noise, and channel bandwidths between each other. As we can tell from Tab. 5-1, those dissimilar frequency bands vary from 890 MHz to 5.35GHz, in order to output those frequencies by a structure that is as simple as possible, dividers will be adopted to modulate the oscillating frequency. We will take the highest frequency as the reference target and outputted directly from the oscillator, then the signal will pass through a 50%-duty-cycle divide-by-2 circuit to obtain the 802.11b/g signal. Similarly, the DCS 1800 signal will come from a 50%-duty-cycle divide-by-3 circuit while the GSM 900 signal is from a divide-by-6 divider. The specification of each system after integration is shown in Tab. 5-4.
Tab. 5-4 System specifications after integrated to 5GHz
IEEE 80211a IEEE 802.11 b/g DCS 1800 GSM 900 RF Frequency 5.15~5.35 GHz 4.8~4.96 GHz 5.13~5.64 GHz 5.34~5.76 GHz
Channel Bandwidth
20MHz 40MHz 600KHz 1200KHz
Phase Noise -110 @1MHz -110 @2MHz -116 @1.8MHz -121 @3.6MHz
Locking Time < 200µs < 200µs N/A N/A
5.2.2 Frequency switching consideration
Although we know how to obtain different signals by only a single oscillating frequency, switch back to each desired system is the prior concern. As we can tell from the data shown in last section, the operating frequency varies from the lowest 4.8GHz to the
highest 5.76GHz, and if we make the voltage controlled oscillator to accomplish that without aids, it will end up a 20% frequency tuning range and thus make the system easily
highest 5.76GHz, and if we make the voltage controlled oscillator to accomplish that without aids, it will end up a 20% frequency tuning range and thus make the system easily