Chapter 2 Integer-N Frequency Synthesizer Applied to MB-OFDM UWB
2.9 Conclusion
Due to its high channel capacity, an ultra-wide band system is an attractive solution for the implementation of very high data rate (>100Mb/s) short range wireless networks.
Nevertheless frequency synthesizers that applied to such high operating frequency are not yet so popular recently not only due to their realistic applications not being extensively but also the serious high frequency parasitic effects that make it more complicate for the designers to meditate the circuit.
However there are still some issues published lately discussing applications to UWB system. According to those references, phase noise suppression and power management will become the first priority while designing. A high oscillating frequency VCO may not only face the problem of circuit stability, parasitic effects will also lead to the frequency deviation, at the meanwhile draw extra power and increase the cost. A frequency divider that operates at high frequency also determines whether a circuit works or not because of the easily varying division. Besides, passive components such as inductors must be redesign since a simple metal path is inductor alike and will lead to unexpected results.
Carefully dealing with those problems may possibly complicate the designing process, but in order to make the circuit owns great performance and high stability, these considerations are important and necessary.
Chapter 3
802.11a Pulse-Swallow Integer-N Frequency Synthesizer
The two most popular structures of RF frequency synthesizers are the fractional-N frequency synthesizer and the integer-N frequency synthesizer. As it tells from the name, the fractional-N structure synthesizes fractional frequency of the reference frequency while the latter one produces integral times of the input signal. In the very beginning of this chapter, we will briefly explain the differences of architectures and applications between these two architectures.
As we just mentioned above that the minimum step size of an integer-N synthesizer equals the reference frequency, however fractional-N breaks this coupling, the step can be designed very small indeed, and designers are free to increase comparison frequency and wide loop bandwidth, locking time is thus reduced, reference spurs and microphonics are eliminated. In Fig. 3-1 it indicates that by periodically changing the division ration from N to N+1 and back, in such that the average is N+A/M where 0≦A＜M (N, A, M are all
Fig. 3-1 Basic view of Fractional-N Synthesizer
Although fractional-N synthesizer owns great performance in frequency resolution and settling time, its division number depends on accumulator carrier which may lead to spur noise closing to the wanted signal due to the periodically produced characteristic. Figure 2 is a basic topology of integer-N synthesizer, because of the integer multiple of the input signal and constant division number in every reference period, spur noise of integer-N structures is less than Fractional-N synthesizer. Consequently, compared with the integer-N frequency synthesizer, a more complicated modulator is needed to alleviate the influence of noise for fractional-N synthesizer.[16]
Fig. 3-2 Basic view of Integer-N Synthesizer
If frequency resolution is not the main factor among designing progress (ex: 20MHz for 802.11a/b/g WLANs system), integer-N structure will be the better choice due to its
spectrum purity. The comparisons of these two architectures are summarized in Tab. 3-1
Tab. 3-1 Comparison between integer-N and fractional-N Synthesizers
Integer-N Fractional-N
Complexity Low High
Spurious noise Well Poor
Settling time Slow Fast
Frequency resolution Slender Adequate Power consumption Low Medium
3.1 Architecture
In this chapter we will explain thoroughly a 802.11a pulse-swallow integer-N frequency synthesizer design flow [17]. In Fig. 3-3 shows basic blocks of the circuit. The whole circuit is designed on chip except the loop filter. It is not only because of larger resistances and capacitances required by the loop filter compared with on-chip components, but also for the intention of adjusting the performance which may be influenced by the fabrication variations. The reference frequency is set to 10MHz and a pulse-swallow counter is designed for the purpose of controlling the dual-modulus divider (÷8/9).
Fig. 3-3 Basic architecture of an integer-N frequency synthesizer
3.2 VCO Design
In order to fit the specifications of 802.11a WLANs system, we adopted a differentially and complementary cross-coupled pairs to generate 5GHz differential symmetric signal outputs [19]. The circuit is shown in Fig. 3-4, as we can see; using both PMOS and NMOS cross-coupled pairs at the same time provides higher negative resistance and symmetries the output waveform. With differential outputs, the common-mode noise coupled from substrate can be alleviated certainly and will lead to impressive low phase noise, meanwhile, since PMOS owns great ability against flicker noise, it can suppress noise up-converted from 1/f noise and other low frequency noise sources efficiently. The design concepts of varacters and buffer used in this circuit are the same as mentioned in Chapter 2.
Fig. 3-4 5.2GHz Voltage controlled oscillator architecture
3.3 High Speed Frequency Divider
In this work, we apply D-type flip flop operation principles to achieve an analog DFF divide- by-2 circuit shown in Fig. 3-5 since all digital units will not function properly at high operating frequency. We can find out in the figure that a divide-by-2 circuit needs to be well planned while performing layout because of its high sensitivity to those parasitic capacitances and resistances resulted from cross signal lines. So take these parasitic effects into consideration during circuit simulation make it the key to precisely division. Fig. 3-6 is the transient simulation result of a 5.2GHz sine wave inputted divider that operates from 4~6GHz with 70 mV minimum acceptable input signal.[12][13]
Fig. 3-5 Analog structure of a divide-by-2 circuit
Fig. 3-6 Simulation result of a divider with 5.2GHz, 80mV sine wave input
3.4 Dual-Modulus Frequency Divider (DMFD)
Since we modulate the oscillating frequency by setting control signals to change the total divisor, a circuit which can carry out more than one division is needed. In this design work we realize a dual-modulus frequency divider that can switch division between 2 and 3 by combining NOR gates to D-type flip-flops. The circuit prototype is shown in Fig. 3-7(a) with clock time diagram analyzed, and the single analog D-type flip-flop is also presented in Fig. 3-7(b). Besides, a DMFD can also accomplished by substituting the NOR gates for NAND gates which graphed in Fig. 3-8.
(a)
(b)
Fig. 3-7 (a) The Prototype of DMFD and its clock timing diagram (b) Architecture combining both DFF and NOR gate
Fig. 3-8 Architecture combining both DFF and NAND gate
As the same situation mentioned in last section, a DMFD must be well constructed and be carefully dealt with its parasitic effects which are due to the complicated cross-coupled signal lines. So the layout is laid in a compact way and the estimated parasitic capacitances about 25fF are connected to the output nodes. Because of the additional D-type flip-flops, a DMFD costs more power than a divide-by-2 divider does.
3.5 Prescaler Design
The prescaler in this design work is actually a combination of two divide-by-2 dividers and a DMFD, thus makes the total division varies between 8 and 9. It is connected right after the outputs of a divider that the main function is to lower down the oscillating frequency. The circuit blocks are shown in Fig. 3-9, the modulus control signal (mc) is provided by the pulse-swallow counter which will be explained in next section. In this figure exist some digital components, since a clear and definite signal must be generated to control the division,delay time and output signal magnitude between each circuit have to be well-planned. The frequency synthesizer generally fails because of signal mistakes in prescaler.
Fig. 3-9 Components of a prescaler
3.6 Pulse-Swallow Counter
Pulse-swallow counter is the key circuit in the close loop design since it controls dual modulus division (÷8/9) we just discussed. It consists of a channel detecting circuit and a loading / resetting counter. The basic way it operates is that the counter counts up from zero to the setting input codes (e.g. 00111), then be reset to counts down from 28 to the input codes thus makes a period of 32. Each block will discuss thoroughly below.[20]
3.6.1 Loading and Resetting Counter
Fig. 3-10 shows a loading and resetting counter consists of 5 JKFFs with which J and K are shorted together. The control signal UD determines the counting mechanism of the circuit, when the signal is low, the counter will count up, and comparatively it will count down if the control signal UD is set to high. In the very first beginning, we set the loading number to 28 instead of 32, this is because that switching between count-up and count-down consumes two clocks and the input codes appear twice cost one extra clock.
The counter counts up from 0 and UD=RL=high at first, when A1~A5 equal to the external channel input codes, RL will be set to low only for one single clock and switched back to high, at the meanwhile, the counter resets and UD changes to low forcing the counting mechanism reversed downwards from 28. As A1~A5 equal to the channel input codes again, RL changes to low still for one clock, and UD turns to high making the counter to re-count upwards from 0. The clock timing diagram is shown in Fig. 3-11.
Fig. 3-10 Loading and resetting counter
Fig. 3-11Timing diagram of loading and resetting counter
3.6.2 Pulse-Swallow Counter [21][22]
The fully-integrated pulse-swallow counter is shown in Fig. 3-12, we can see that the 5 output signals of the loading / resetting counter are connected to XORs to compare with the external channel input signals. As long as A1~A5 equal Ch1~Ch5, the RL signal will turn into low and consequently make the JKFF, which J, K shorted together, output a low level
signal sent back to UD. Remember that the RL signal will swap between high and low only on the instance A1~A5 equal Ch1~Ch5.
Fig. 3-12 Architecture of fully-integrated pulse-swallow counter
We mentioned in last section that the load number of the counter should be set to 28 instead of 32, it can be explained by the timing diagram shown in Fig. 3-13. Assume the external channel input codes are 00110 (i.e. 6), no matter the counter counts up from 0 or counts down from 28, the digit 6 is calculated twice, and the same circumstance occurs during loading the codes and reset the counter.
Fig. 3-13 Analysis of a pulse-swallow counter
3.7 Phase / Frequency Detector
The heart of a synthesizer is the phase / frequency detector. This is where the reference frequency signal is compared with the signal fed back from the voltage controlled oscillator output, and the resulting error signal is transformed into current by charge pump in order to drive the loop filter and the VCO control bit. Generally in a RF frequency synthesizer design, the VCO output signal will be scaled down gradually by several analog and digital dividers so that the frequency inputting to a phase / frequency detector will be only a few tens MHz, and for this reason, a digital PFD is the most adopted in designing RF frequency synthesizers.[25]
Down below in Fig. 3-14(a) shows a basic implementation of PFD and a simple charge pump which in next section will be described, basically consisting of two D-type flip flops and digital delay cells. As we can see in the Fig. 3-14(b), if the reference signal (Vref) is faster than the signal scaling down from VCO (Vdiv ), the upper flip flop will send the output high and this is maintained until the first rising edge occurs on Vdiv, till then the NAND gate will generate a signal low back to reset both flip flops. In a practical system this means that the output which input to the VCO is driven higher forcing the oscillating frequency to catch up with the reference signal, vice versa.
Fig. 3-14 (a) Phase / frequency detector (b) Time diagram comparison between Vref and Vdiv
3.8 Charge Pump
Fig. 3-15 shows the architecture of a charge pump which functions as a transforming mechanism turning phase mismatch detected by PFD into a charging current. In this project the charge pump works with a fixed reference current, and in order to obtain high voltage output range, the transistor size of the current mirror transistors (M1~M11) must be designed carefully.
Besides, since mismatched current produced at the time the two input signals out of
phase will cause interference with adjacent channel and spurious tones in RF receiver, we will implement two extra transistors (M12, M14) in the circuit to solve the problem. Those two NMOS guarantee that M13 and M15 sources are already pre-charged when switching takes place. Also an accurate layout of the circuit can improve the matching among the positive and negative currents to reduce undesired spectral emission in RF transmitter.
Fig. 3-15 Schematic of charge pump
3.9 Loop Filter
We choose a 3rd order RC loop filter in this work as shown in Fig. 3-16 since it is an extremely critical key point in designing a frequency synthesizer. Output of a loop filter is a dc voltage and directly connected to VCO, so a well considered circuit not only can degrade high frequency noise but also prevent the disturbance produced while PFD and charge pump switching states from influencing VCO, and at the meanwhile can the synthesizer come to stable. Loop bandwidth of the filter owns great affections to the synthesizer settling time, so
we make the filter the only one circuit exclude from the chip so as to modulate the response of the circuit. Based on simulation results, we can obtain a set of element values and are shown in Tab. 3-2.
Fig. 3-16 A 3rd order loop filter
Tab. 3-2 Optimized loop filter elements
Component Value
C1 19.92 pF
R2 19.57 kΩ
C2 300 pF
R3 4 kΩ
C3 39.79 pF
3.10 Synthesizer Simulation Results
All of the building blocks mentioned before will be combined into a single frequency synthesizer to simulate together and display in this section. Fig. 3-17 is the whole circuit schematic, and Fig. 3-18 shows the frequency synthesizer pre-analyzed by MATLAB since
the whole circuit simulation takes a lot of time.[23]
Fig. 3-17 Schematic of an integer-N frequency synthesizer
We can find out in the figure that the phase margin is more than 55 degree. After that, we adopt Eldo RF to examine whether the close loop performance meet our expectation or not and the results in Fig. 3-19 shows that the settling time is less than 30µs (the circuit enters the stable region at about 20µs ), also in Fig. 3-20 shows the output power spectrum with the peak magnitude -9.9dBm, and Fig. 3-21 is the channel-switching result between 00000 and 00010 ( at the meanwhile, oscillating frequency changes from 5.14GHz to 5.20GHz ). In Tab. 3-3 are the results of the full circuit closed-loop simulation, The layout of an integer-N frequency synthesizer that occupies a dimension 1.219mm2 is shown in Fig.
3-22 which.
Fig. 3-18 MATLAB simulation results
Fig. 3-19 Settling time of the close loop is less than 30µs
Fig. 3-20 Output power spectrum (about -9.9dBm)
Fig. 3-21 Channels switch from 00000 to 00010 ( 5.14GHz to 5.20GHz )
Tab. 3-3 Simulation results of a integer-N frequency synthesizer
Simulation Results
Application 802.11a Manufacturing process TSMC 0.18um CMOS
Supply voltage 1.8V
Synthesizer type Integer-N pulse-swallow
Oscillating frequency 5.2GHz
Reference frequency 10MHz
Tuning range 4.95GHz~5.82GHz
Phase noise -114dBc/Hz @ 1MHz
Settling time 20us
Output power -9.9dBm
Die area 1.15mm X 1.06mm
Power dissipation 18.844mW
Fig. 3-22 Layout of the integer-N frequency synthesizer
3.11 Measurement Results
3.11.1 Measurement Preparation
Since a frequency synthesizer owns a lot of output pads including supply voltage, bias voltage, input channel control signals, reference signal, and output signals, it is quite unlikely to measure the whole circuit on wafer. We design a PCB (printed circuit board) layout which graphed in Fig. 3-23 and use SMA connectors to make it possible connect the circuit to the measuring equipments. The measuring equipments for VCO and frequency synthesizer contains Agilent E5052A signal source analyzer (Fig. 3-24a at CIC), Agilent E4407B spectrum analyzer (Fig. 3-24b at CIC), HP 8563E spectrum analyzer (Fig. 3-24c at lab), HP54610B oscilloscope (Fig. 3-24d at lab), HP E3611A power supply (Fig. 3-24e at lab), and HP33120A function generator (Fig. 3-24f at lab).
While designing a PCB layout, we can tell from Fig. 3-23 that the line widths of the output signal from VCO need to be matched to 50Ω which is the interior resistance of the instruments. We also reserve extra space for bypass and DC blocking capacitors, and the chip is stuck to the board with all I/O pads bounded onto it via bond-wires. Fig. 3-25 is the practical FR4 PCB measurement circuit and the die photo is shown in Fig. 3-26.
Fig. 3-23 PCB layout of the frequency synthesizer
(a)
(b)
(c)
(d)
(e)
(f)
Fig. 3-24 (a) Agilent E5052A signal source analyzer
(b) Agilent E4407B spectrum analyzer (c) HP 8563E spectrum analyzer (d) HP54610B oscilloscope (e) HP E3611A power supply
(f) HP33120A function generator
Fig. 3-25 A practical FR4 PCB measurement circuit
Fig. 3-26 A 5.2GHz integer-N frequency synthesizer
3.11.2 Measurement Results
First we will discuss about the tuning curve and output power of the voltage controlled oscillator. We can see from Fig. 3-27 that all the banks (from 00 to 11) include the frequency range needed, namely, as long as picking up the right control bits corresponds to each bank can we make the frequency synthesizer lock successfully. In Fig. 3-28 is the comparison of tuning range between simulation and measurement at bank 10.
Fig. 3-27 Measured tuning range under different banks
Fig. 3-28 Comparison between post-simulation and measurement at bank 10
According to the graph, a successful prediction of parasitic capacitor was performed since that the central part of tuning curves are almost the same linear for both post-simulation and measurement even though there is a little difference when control voltage is nearly 0V and 1.8V.
Next we will find out the critical parameter of a voltage-controlled oscillator, phase noise. First we set the buffer’s bias voltage to 0.9V just as what has been done during the simulation to examine the phase noise at 1MHz offset from the carrier and obtain the result shown in Fig. 3-29. However the output power is smaller compared to the simulation result, we raise the bias voltage up to meet the DC analytic anticipation and come to the end which is almost the same as expected.
Fig. 3-30(a) shows the post-simulation result, Fig. 3-30(b) shows the measurement, and Fig. 3-31 is the output power spectrum showing the magnitude of -13.5dBm. Besides we can improve the phase noise by adjusting the bias voltage, consequently a value -126dBc/Hz is obtained and shown in Fig. 3-32.
Fig. 3-29 Phase noise is about -100dBc/Hz @ 1MHz with Vb=0.9V
(a)
(b)
Fig. 3-30 (a) Post-simulation phase noise is -114dBc/Hz @ 1MHz (b) Measured phase noise is -114dBc/Hz @ 1MHz
Fig. 3-31 VCO output power is -13.50dBm at 5.2GHz
Fig. 3-32 Phase noise is -126dBc/Hz @ 1MHz after adjusted
Down below in Fig. 3-33 is the measurement result of the settling time while applying a periodical clock signal to the division control bit. Since it is impossible to read the settling time from an oscilloscope directly due to the locking time ranges at micro-seconds, we have to observe the transient by switching the total division through a function generator.
As which can be distinguished that the settling time is just a little bit longer than 20µs which derived from the simulation. The control voltage is stably locked at about 40µs. Tab.
3-4 shows the comparison between the simulation and the measurement results while Tab.
3-5 is the comparison with the references.
Fig. 3-33 Settling time of the close loop
Tab. 3-4 Comparison between simulation and measurement
Spec. Simulation Measurement
Tuning Range 4.95GHz~5.82GHz 4.98GHz~5.73GHz Phase noise -114dBc/Hz @ 1MHz -126dBc/Hz @ 1MHz
Settling time 20us ~20us
VCO output power -9.9dBm -13.5dBm
Power dissipation 18.844mW 26.35mW
Tab. 3-5 Comparison between reference papers and this work
Reference [16] 2005 [19] 2005 [17] 2003 [8] 2003 This work
Frequency band (GHz) N/A 4.11~4.35 5.15~5.70 5.15~5.82 4.98~5.73
Tuning range N/A 5.64% 27.2% N/A 14.42%
Phase noise
-125dBc/Hz
-125dBc/Hz