Chapter 3 802.11a Pulse-Swallow Integer-N Frequency Synthesizer
3.6 Pulse-Swallow Counter
3.6.2 Pulse-Swallow Counter [21][22]
The fully-integrated pulse-swallow counter is shown in Fig. 3-12, we can see that the 5 output signals of the loading / resetting counter are connected to XORs to compare with the external channel input signals. As long as A1~A5 equal Ch1~Ch5, the RL signal will turn into low and consequently make the JKFF, which J, K shorted together, output a low level
signal sent back to UD. Remember that the RL signal will swap between high and low only on the instance A1~A5 equal Ch1~Ch5.
Fig. 3-12 Architecture of fully-integrated pulse-swallow counter
We mentioned in last section that the load number of the counter should be set to 28 instead of 32, it can be explained by the timing diagram shown in Fig. 3-13. Assume the external channel input codes are 00110 (i.e. 6), no matter the counter counts up from 0 or counts down from 28, the digit 6 is calculated twice, and the same circumstance occurs during loading the codes and reset the counter.
Fig. 3-13 Analysis of a pulse-swallow counter
3.7 Phase / Frequency Detector
The heart of a synthesizer is the phase / frequency detector. This is where the reference frequency signal is compared with the signal fed back from the voltage controlled oscillator output, and the resulting error signal is transformed into current by charge pump in order to drive the loop filter and the VCO control bit. Generally in a RF frequency synthesizer design, the VCO output signal will be scaled down gradually by several analog and digital dividers so that the frequency inputting to a phase / frequency detector will be only a few tens MHz, and for this reason, a digital PFD is the most adopted in designing RF frequency synthesizers.[25]
Down below in Fig. 3-14(a) shows a basic implementation of PFD and a simple charge pump which in next section will be described, basically consisting of two D-type flip flops and digital delay cells. As we can see in the Fig. 3-14(b), if the reference signal (Vref) is faster than the signal scaling down from VCO (Vdiv ), the upper flip flop will send the output high and this is maintained until the first rising edge occurs on Vdiv, till then the NAND gate will generate a signal low back to reset both flip flops. In a practical system this means that the output which input to the VCO is driven higher forcing the oscillating frequency to catch up with the reference signal, vice versa.
Fig. 3-14 (a) Phase / frequency detector (b) Time diagram comparison between Vref and Vdiv
3.8 Charge Pump
Fig. 3-15 shows the architecture of a charge pump which functions as a transforming mechanism turning phase mismatch detected by PFD into a charging current. In this project the charge pump works with a fixed reference current, and in order to obtain high voltage output range, the transistor size of the current mirror transistors (M1~M11) must be designed carefully.
Besides, since mismatched current produced at the time the two input signals out of
phase will cause interference with adjacent channel and spurious tones in RF receiver, we will implement two extra transistors (M12, M14) in the circuit to solve the problem. Those two NMOS guarantee that M13 and M15 sources are already pre-charged when switching takes place. Also an accurate layout of the circuit can improve the matching among the positive and negative currents to reduce undesired spectral emission in RF transmitter.
Fig. 3-15 Schematic of charge pump
3.9 Loop Filter
We choose a 3rd order RC loop filter in this work as shown in Fig. 3-16 since it is an extremely critical key point in designing a frequency synthesizer. Output of a loop filter is a dc voltage and directly connected to VCO, so a well considered circuit not only can degrade high frequency noise but also prevent the disturbance produced while PFD and charge pump switching states from influencing VCO, and at the meanwhile can the synthesizer come to stable. Loop bandwidth of the filter owns great affections to the synthesizer settling time, so
we make the filter the only one circuit exclude from the chip so as to modulate the response of the circuit. Based on simulation results, we can obtain a set of element values and are shown in Tab. 3-2.
Fig. 3-16 A 3rd order loop filter
Tab. 3-2 Optimized loop filter elements
Component Value
C1 19.92 pF
R2 19.57 kΩ
C2 300 pF
R3 4 kΩ
C3 39.79 pF
3.10 Synthesizer Simulation Results
All of the building blocks mentioned before will be combined into a single frequency synthesizer to simulate together and display in this section. Fig. 3-17 is the whole circuit schematic, and Fig. 3-18 shows the frequency synthesizer pre-analyzed by MATLAB since
the whole circuit simulation takes a lot of time.[23]
Fig. 3-17 Schematic of an integer-N frequency synthesizer
We can find out in the figure that the phase margin is more than 55 degree. After that, we adopt Eldo RF to examine whether the close loop performance meet our expectation or not and the results in Fig. 3-19 shows that the settling time is less than 30µs (the circuit enters the stable region at about 20µs ), also in Fig. 3-20 shows the output power spectrum with the peak magnitude -9.9dBm, and Fig. 3-21 is the channel-switching result between 00000 and 00010 ( at the meanwhile, oscillating frequency changes from 5.14GHz to 5.20GHz ). In Tab. 3-3 are the results of the full circuit closed-loop simulation, The layout of an integer-N frequency synthesizer that occupies a dimension 1.219mm2 is shown in Fig.
3-22 which.
Fig. 3-18 MATLAB simulation results
Fig. 3-19 Settling time of the close loop is less than 30µs
Fig. 3-20 Output power spectrum (about -9.9dBm)
Fig. 3-21 Channels switch from 00000 to 00010 ( 5.14GHz to 5.20GHz )
Tab. 3-3 Simulation results of a integer-N frequency synthesizer
Simulation Results
Application 802.11a Manufacturing process TSMC 0.18um CMOS
Supply voltage 1.8V
Synthesizer type Integer-N pulse-swallow
Oscillating frequency 5.2GHz
Reference frequency 10MHz
Tuning range 4.95GHz~5.82GHz
Phase noise -114dBc/Hz @ 1MHz
Settling time 20us
Output power -9.9dBm
Die area 1.15mm X 1.06mm
Power dissipation 18.844mW
Fig. 3-22 Layout of the integer-N frequency synthesizer
3.11 Measurement Results
3.11.1 Measurement Preparation
Since a frequency synthesizer owns a lot of output pads including supply voltage, bias voltage, input channel control signals, reference signal, and output signals, it is quite unlikely to measure the whole circuit on wafer. We design a PCB (printed circuit board) layout which graphed in Fig. 3-23 and use SMA connectors to make it possible connect the circuit to the measuring equipments. The measuring equipments for VCO and frequency synthesizer contains Agilent E5052A signal source analyzer (Fig. 3-24a at CIC), Agilent E4407B spectrum analyzer (Fig. 3-24b at CIC), HP 8563E spectrum analyzer (Fig. 3-24c at lab), HP54610B oscilloscope (Fig. 3-24d at lab), HP E3611A power supply (Fig. 3-24e at lab), and HP33120A function generator (Fig. 3-24f at lab).
While designing a PCB layout, we can tell from Fig. 3-23 that the line widths of the output signal from VCO need to be matched to 50Ω which is the interior resistance of the instruments. We also reserve extra space for bypass and DC blocking capacitors, and the chip is stuck to the board with all I/O pads bounded onto it via bond-wires. Fig. 3-25 is the practical FR4 PCB measurement circuit and the die photo is shown in Fig. 3-26.
Fig. 3-23 PCB layout of the frequency synthesizer
(a)
(b)
(c)
(d)
(e)
(f)
Fig. 3-24 (a) Agilent E5052A signal source analyzer
(b) Agilent E4407B spectrum analyzer (c) HP 8563E spectrum analyzer (d) HP54610B oscilloscope (e) HP E3611A power supply
(f) HP33120A function generator
Fig. 3-25 A practical FR4 PCB measurement circuit
Fig. 3-26 A 5.2GHz integer-N frequency synthesizer
3.11.2 Measurement Results
First we will discuss about the tuning curve and output power of the voltage controlled oscillator. We can see from Fig. 3-27 that all the banks (from 00 to 11) include the frequency range needed, namely, as long as picking up the right control bits corresponds to each bank can we make the frequency synthesizer lock successfully. In Fig. 3-28 is the comparison of tuning range between simulation and measurement at bank 10.
Fig. 3-27 Measured tuning range under different banks
Fig. 3-28 Comparison between post-simulation and measurement at bank 10
According to the graph, a successful prediction of parasitic capacitor was performed since that the central part of tuning curves are almost the same linear for both post-simulation and measurement even though there is a little difference when control voltage is nearly 0V and 1.8V.
Next we will find out the critical parameter of a voltage-controlled oscillator, phase noise. First we set the buffer’s bias voltage to 0.9V just as what has been done during the simulation to examine the phase noise at 1MHz offset from the carrier and obtain the result shown in Fig. 3-29. However the output power is smaller compared to the simulation result, we raise the bias voltage up to meet the DC analytic anticipation and come to the end which is almost the same as expected.
Fig. 3-30(a) shows the post-simulation result, Fig. 3-30(b) shows the measurement, and Fig. 3-31 is the output power spectrum showing the magnitude of -13.5dBm. Besides we can improve the phase noise by adjusting the bias voltage, consequently a value -126dBc/Hz is obtained and shown in Fig. 3-32.
Fig. 3-29 Phase noise is about -100dBc/Hz @ 1MHz with Vb=0.9V
(a)
(b)
Fig. 3-30 (a) Post-simulation phase noise is -114dBc/Hz @ 1MHz (b) Measured phase noise is -114dBc/Hz @ 1MHz
Fig. 3-31 VCO output power is -13.50dBm at 5.2GHz
Fig. 3-32 Phase noise is -126dBc/Hz @ 1MHz after adjusted
Down below in Fig. 3-33 is the measurement result of the settling time while applying a periodical clock signal to the division control bit. Since it is impossible to read the settling time from an oscilloscope directly due to the locking time ranges at micro-seconds, we have to observe the transient by switching the total division through a function generator.
As which can be distinguished that the settling time is just a little bit longer than 20µs which derived from the simulation. The control voltage is stably locked at about 40µs. Tab.
3-4 shows the comparison between the simulation and the measurement results while Tab.
3-5 is the comparison with the references.
Fig. 3-33 Settling time of the close loop
Tab. 3-4 Comparison between simulation and measurement
Spec. Simulation Measurement
Tuning Range 4.95GHz~5.82GHz 4.98GHz~5.73GHz Phase noise -114dBc/Hz @ 1MHz -126dBc/Hz @ 1MHz
Settling time 20us ~20us
VCO output power -9.9dBm -13.5dBm
Power dissipation 18.844mW 26.35mW
Tab. 3-5 Comparison between reference papers and this work
Reference [16] 2005 [19] 2005 [17] 2003 [8] 2003 This work
Frequency band (GHz) N/A 4.11~4.35 5.15~5.70 5.15~5.82 4.98~5.73
Tuning range N/A 5.64% 27.2% N/A 14.42%
Phase noise
-125dBc/Hz ( @3MHz)
-139dBc/Hz ( @20MHz)
-116dBc/Hz ( @1MHz)
-106dBc/Hz ( @1MHz)
-126dBc/Hz ( @1MHz) Divider architecture Fractional-N Integer-N Integer-N Fractional-N Integer-N
Reference frequency N/A 16MHz 10MHz 19MHz 10MHz
Settling time 25us N/A 100us 520us 20us
Power consumption 54mW 9.68mW 13.5mW N/A 26.35mW
Supply voltage 1.8V 1.0V 2.5V 1.8V 1.8V
Manufacturing process 0.18um 0.18um 0.25um 0.18um 0.18um
Chapter 4
Conclusions and Future Works
4.1 Conclusions
We have presented a frequency synthesizer that applied to MB-OFDM UWB 5th band group. Throughout the design, each component is accomplished in the traditional architecture in order to testify the possibility for an ordinary circuit to operate at high frequency. A differential-in center-tapped inductor is adopted while designing a 10GHz VCO not only for the chip area consideration but also anxiety for high Q value and impressive performance in phase noise. Only NMOS cross-coupled pairs are used instead of NP cascaded structure as mostly seen prevents the upper voltage limitation occurs a lot in the latter one and make it easier to design.
Fully programmable multi-modulus frequency divider is consists of 7-stage cascaded divide by 2/3 circuits with varying division from 128 to 159 and is used to scaled down the operating frequency for the phase/frequency detector to compared with the reference signal.
A register is designed to load all the divider control signals since that preparing each control path a pad will lead to extremely large chip size. The VCO is simulated to have a 1000mV peak-to-peak voltage swing at 10GHz and -5.79dBm output power. The tolerant frequency range varies from 9.29GHz to 10.9GHz due to adjustment of two-pairs of varactors, besides it owns a -97dBc/Hz phase noise at 1MHz and a settling time at about 25us.
After that we introduce an integer-N frequency synthesizer applied to IEEE 802.11a. In the design a cascode NMOS and PMOS cross-coupled pairs forms the core circuit of the voltage controlled oscillator, only a single dual modulus frequency is adopted in order to
lower power consumption. A pulse-swallow counter is designed to control the switching mechanism of the dual modulus frequency divider by comparing the internal proceeding signal with the external setting control bits. The loading number is set to be 28 instead of 32 due to extra clocks needed during the comparison takes place.
The tuning range measurement results are very alike to the simulations although shift down slightly. This may results from the neglect of parasitic inductors which come from the overlong metal line connected to the output pad while simulating. It can be solved henceforward by using other simulation software such as SONNET. The measuring phase noise comes to the best at about -126dBc/Hz after adjusting the power supply and the bias voltage with resulting output power -13.5dBm at 5GHz. And the settling time is closely 20us with one of the division control bit connected to the function generator.
4.2 Future works
In spite of a frequency synthesizer applied to 802.11a has already been successfully fabricated, there are still some space left for improvement. Scaling the chip size down and efficiently suppress the power dissipation are good aspects since which can be clearly told from the layout shown before that some space is wasted by some overlong control signal paths and dummy. Furthermore, we can try to lower down the supply voltage to 1V and modified the circuit architecture to reduce power consumption. So a more compact chip with lower power dissipation can be expected.
Besides that, the pulse-swallow counter we adopted in this design actually existing some problems while putting into practice. Time delay consideration and clock control which easily vary as seen while during simulation determine whether the counter derives
the right compared signal or not. Consequently finding new substitute architectures or taking every possible problem into consideration will enhance the possibility for a circuit to functions well.
Ultra wide-band systems have recently received a great deal of interest due to their potential for high-speed wireless communication. Not only offers a promising solution to the RF spectrum drought by allowing new services to coexist with current radio systems with minimal or no interference, but also brings the advantage of avoiding the expensive spectrum licensing fees that providers of all other radio services must pay. In IEEE 802.15.3a, multi-band orthogonal frequency division multiplexing (MB-OFDM) with fast frequency hopping is proposed as a means of high bit-rate wireless communication in the UWB spectrum.
As the result, a proper transceiver design that applied to UWB system will be one of the main streams in the future. Although some articles mentioned that they are almost getting this job done, make it more complete and even better are still moving forward and needs great devotion. How to map out a well-performance frequency synthesizer that can carry out stable oscillating frequency varying from the lowest band group 3.1GHz to the highest one 10.6GHz and come to the specifications required by the system is our next objective.
Reference
[1] Evan R. Green and Sumit Roy, “System Architectures for High-rate Ultra-wideband Communication Systems: A Review of Recent Developments”, Intel Labs 2111 NE 25th Ave. Hillsboro, OR97124
[2] Behzad Razavi, Turgut Aytur, Christopher Lam, Fei-Ran Yang, Kuang-Yu (Jason) Li, Ran-Hong (Ran) Yan, Han-Chang Kang, Cheng-Chung Hsu,and Chao-Cheng Lee, “A UWB CMOS Transceiver”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005
[3] Julien Ryckaert, Claude Desset, Vincent de Heyn, Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Bert Van Poucke “Ultra-Wideband Transmitter for Wireless Body Area Network”, IMEC, Kapeldreef, 75 B-3001 Leuven Belgium
[4] Anuj Batra, Jaiganesh Balakrishnan, and Anand Dabak, “Multiband OFDM: Why it Wins for UWB”, Texas Instruments, 2006
[5] S. M. Sajad Sadough, Mahieddine M. Ichir, Emmanuel Jaffrot and Pierre Duhamel,
“Multiband OFDM UWB Channel Estimation Via A Wavelet Based EM-MAP Algorithm”, SPAWC, 2006, Juillet France
[6] Dr. Anuj Batra, “Multi-Band OFDM: Achieving High Speed Wireless Communications” Texas Instruments, August 22, 2004.
[7] Geum-Young Tak; Seok-Bong Hyun; Tae Young Kang; Byoung Gun Choi; Seong Su Park, “A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications”, Solid-State Circuits, IEEE Journal of Volume 40, Issue 8, Aug. 2005 Page(s):1671 - 1679 Digital Object Identifier 10.1109/JSSC.2005.852421.
[8] Detlev Theill, Christian Durdodt, Andre Hanke, Stefan Heinen, Stefan van Waasen, Dietolf Seippel, Duyen Pham-Stabner, Klaus Schumacher, “A Fully Integrated CMOS
Frequency Synthesizer for Bluetooth”, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.103-106, Phoenix, Arizona, USA., May 20-22, 2001
[9] N.Pavlovic, J.Gosselin, K.Mistry, D.Lelnaerts, “A 10GHz Frequency Synthesizer for 802.11a in 0.18um CMOS”, 21-23 Sept. 2004 Page(s):367 – 370, Digital Object Identifier 10.1109/ESSCIR.2004.1356694
[10] C.B. Sia, K.W. Chan, C.Q. Geng, W. Yang, K.S. Yeo, M.A. Do, J.G.. Ma, S. Chu, K.W. Chew, “An Accurate and scalable Differential Inductor Design Kit”, 22-25 March 2004 Page(s):63 – 68
[11] Pietro Andreani, Sven Mattisson, “On the Use of MOS Varactors in RF VCO’s”, IEEE Journal of Solid-State Circuits, Volume 35, Issue 6, June 2000 Page(s):905 - 910 Digital Object Identifier 10.1109/4.845194.
[12] Thomas H.Lee, Hamid R.Rategh, “Multi-GHz Frequency Synthesis & Division:
Frequency Synthesizer Design for 5GHz Wireless LAN Systems”, Kluwer Academic Publishers, 2001
[13] C. Lam, B. Razavi, “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-µm CMOS technology”, IEEE Journal of Solid-State Circuits, Volume 35, Issue 5, May 2000 Page(s):788 - 794 Digital Object Identifier 10.1109/4.841508
[14] N. Foroudi, T.A Kwasniewski, “CMOS High-Speed Dual-Modulus Frequency Divider For RF Frequency Synthesis”, IEEE Journal of Solid-State Circuits, Volume 30, Issue 2, Feb. 1995 Page(s):93 - 100 Digital Object Identifier 10.1109/4.341735.
[15] Jung-Eim Lee; Eun-Chul Park; Choong-Yul Cha; Hyun-Su Chae; Chun-Deok Suh;
Jeongwook Koh; Hanseimg Lee; Hoon-Tae Kim,” A frequency synthesizer for UWB transceiver in 0.13/spl mu/m CMOS technology”, Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on 18-20 Jan.
2006 Page(s):4 pp. Digital Object Identifier 10.1109/SMIC.2005.1587974
[16] Weilun Shen, Kangmin Hu, Xiaofeng Yi, Ye Zhou, Zhiiang Hong, “A 5GHz CMOS
monolithic fractional-N frequency synthesizer”, ASIC 2005, ASICON 2005. 6th International Conference on Volume 2, 24-27 Oct. 2005 Page(s):624 – 627.
[17] Herzel, F, Fischer, G.; Gustat, H. ”An integrated CMOS RF synthesizer for 802.11a wireless LAN”, IEEE Journal of Solid-State Circuits, Volume 38, Issue 10, Oct. 2003 Page(s):1767 - 1770 Digital Object Identifier 10.1109/JSSC.2003.817601.
[18] Marsolais, A.; El-Gamal, M.N.; Sawan, M. “A CMOS frequency synthesizer covering the lower and upper bands of 5GHz WLANs”, Circuits and Systems, 2003. MWSCAS 2003, Proceedings of the 46th IEEE International Midwest Symposium on Volume 3, 27-30 Dec. 2003 Page(s):1146 - 1149 Vol. 3
[19] Leung, L.L.K.; Luong, H.C. ”A 1-V, 9.7mW CMOS frequency synthesizer for WLAN 802.11a transceivers”, VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on 16-18 June 2005 Page(s):252 - 255 Digital Object Identifier 10.1109/
VLSIC.2005.1469379.
[20] Yan Dan Lei, “A low power CMOS 2.4-GHz monolithic integer-N synthesizer for wireless sensor”, Radio-Frequency Integration Technology: Integrated Circuits for Wideband Communication and Wireless Sensor Networks, 2005. Proceedings. 2005 IEEE International Workshop on 30 Nov.-2 Dec. 2005 Page(s):219 - 222 Digital Object Identifier 10.1109/RFIT.2005.1598915
[21] Mano, M., “Digital Design: Second Edition”, Prentice-Hall Inc., USA, 1991.
[22] Sulaiman, M.S.; Khan, N ”A novel low-power high-speed programmable dual modulus divider for PLL-based frequency synthesizer”, Semiconductor Electronics, 2002.
Proceedings. ICSE 2002. IEEE International Conference on 19-21 Dec. 2002 Page(s):77 - 81 Digital Object Identifier 10.1109/SMELEC.2002.1217779
[23] Ali, S. Margala, M. “A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time”, Circuits and Systems, 2004. ISCAS 2004. Proceedings of the 2004 International Symposium on Volume
4, 23-26 May 2004 Page(s):IV - 237-40 Vol.4.
[24] Rahul Magoon, Alyosho Molnar, Jeff Zachan, Geoff Hatcher, Woogeun Rhee, “A Single-Chip Quad-Band (850/900/1800/1900 MHz) Direct Conversion GSM/GPRS RF Transceiver with Integrated VCOs and Fractional-N Synthesizer”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002
[25] Rogers, J.W.M., Cavin, M, Dai, F. and Rahn, D., “A ∆Σ Fractional-N Frequency Synthesizer with Multi-Bands PMOS VCOs for 2.4GHz and 5GHz WLAN
[25] Rogers, J.W.M., Cavin, M, Dai, F. and Rahn, D., “A ∆Σ Fractional-N Frequency Synthesizer with Multi-Bands PMOS VCOs for 2.4GHz and 5GHz WLAN