Chapter I Introduction
1.2 Thesis Organization
1.1 Motivation
A RF power detection circuit for auto-compensating I/Q mismatch and LO-feedthrough of the direct up-conversion mixer is necessary to form a closed-loop design in my senior’s project [1]. The first task was to design cascading stages of RF power detection circuits, including a pre-amplifier, a power detector, and a comparator, that can meet the specifications given. Some of the design backgrounds of RF power detection during this work is covered up. Furthermore, this motivates research topics on applications for the power detectors, such as built-in self test (BIST) designs for RF-circuits.
In this thesis, a RF BIST design using power comparing method instead of designing wide dynamic range and low error power detectors to test the gain of a low noise amplifier is described. Another work of modifying the original idea is also proposed to break-through the bottleneck of process variations.
1.2 Thesis organization
In Chapter II, some of the backgrounds of the RF detection techniques will be cover. In Section 2.1, basics of Meyer power detector along with its design equations are introduced. The successive detection theory of the logarithmic amplifier is written in Section 2.2. In Chapter III, the power detection circuit design in a WiMAX transmitter is introduced. In Chapter IV, BIST circuit designs for 5GHz LNA are described. Finally, some conclusion and future work is written in Chapter V
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Chapter II
Fundamentals of RF detection circuits
2.1 Introduction
This chapter introduces some of the recent approaches of detecting RF signals.
The surveyed publications can be categorized into two groups. One group is the circuits that detect RF signals directly and convert it into a DC value [2]-[12] which are able to work at frequencies GHz-frequencies, such as power detector, peak detector, amplitude detector, RMS detector, rectifier, etc.
The other one is the logarithmic amplifier (log amp) [13]-[20] that can convert a large dynamic range dB-linear input into small dynamic range linear output which usually works at MHz-frequencies. Logarithmic amplifiers are typically used in AGC-loops as RSSIs (received signal strength indicator) to detect the signal amplitude. Especially in communication systems, it is very important to know the incoming signal level accurately so that a reliable decision between a successful or a failed connection can be made. Also the required number of bits for the A/D-converter which is usually placed as the following circuit block can be more relaxed with an AGC amplifier. This implies that the dynamic range, accuracy, and process dependency are the major design challenges. Logarithmic amplifier can also be arranged as the succeeding stage of a power detector [10]-[12] (or the other detectors mentioned above) that compress the large dynamic range to a readable output during detection.
In Section 2.2, a popular Meyer power detector is analyzed by means of Taylor
2
series. In Section 2.3, an overview of the logarithmic amplifier is given.
2.2 Meyer power detector
A monolithic low power RF power detector using bipolar transistors (fT=8GHz) was first invented by Meyer [2] in 1995. This detector can be used for embedded RFIC test because it has the advantages of simplicity, wide bandwidth, low power, small chip size, and temperature stability. The detector was also analyzed by Zhang using similar approach, such as Bessel function [3]. A modified design was also proposed to extend its dynamic range. The following will repeat their analysis by means of Taylor series and replace the bipolar transistors with MOSFET biased at sub-threshold region which the current is also expressed in exponential function.
Fig. 2-1 Meyer power detector
Fig. 2-1 is the schematic of a Meyer power detector (Meyer PD). M1 acts as the nonlinear rectifying element on signal voltage Vi. Transistor M2 sets up a replica circuit so that DC voltage VO(=VO+−V )O− is zero for zero AC signal input at Vi. Notice that M1 and M2 are identical and are biased at their sub-threshold region. C1
and C2 are large enough to filter out the unwanted high frequency components and generate a pure DC output as possible. VO can be expressed as:
3
( ) ( ) 2
O O O X O X O GS GS
V =V +−V −= V −V − − V −V + =V −V 1 (2.1) The sub-threshold current of M1 can be expressed as:
1 0 1
Set cos , where is the amplitude of the input signal and is the input frequency 1 cos 2
Since identical current sources are used, the equation can be written as:
1 2
2 2
(2.6) shows that when the input signal is small, the differential DC output will be proportional to the square of the input signal amplitude and this is referred as the square law region of the power detector. Besides, it is apparent that the output is approximately inversely proportional to absolute temperature. Temperature could be compensated by dividing by a quantity proportional to temperature. Meyer also derived the equation for large Vin and the DC output can be expressed as:
ln 2 in
We can conclude shortly that the power detector can work in the linear region for large signal detection and in square law region for small signal detection. Fig. 2-2 is a simulation of a Meyer PD using TSMC 0.18um technology to verify the mathematical derivation above. The transition power level of the linear and square law region is about -15dBm. The dynamic range is at least -35dB for the square law region and 25dB for the linear region. Notice that the output of Meyer PD is logarithmic linear..
A logarithmic amplifier can be added behind the PD to convert linear in dB input into linear output.
Instead of examining the Meyer PD by tedious mathematical equations, we can still use our “engineer’s intuition” to explain the mechanism. Re-visit Fig. 2-1 and assume that there isn’t any input signal. Hence, the VGS of both transistors will ideally be the same since they are biased with identical current sources. While there is an input signal, M1 then adjusts its VGS to maintain the constant DC current. Since the gate voltage of M1 is fixed, its source (VO+) will change proportionally to the strength
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of the input.
RF input power (dBm to 50Ohm)
PD outout voltage (V)
Fig. 2-2 Transfer curve of the Meyer power detector
In [3], an analysis of a periodic input signal of any shape instead of a pure sinusoidal is given. It shows that the possibilities of Meyer PD in multi-tone detections. The input periodic signal can be represented as the sum of N harmonics, where N is a positive integer.
, Thus, the current of M1 can be expressed as:
1 0 1 The equation above can be re-written in the form of Bessel functions [23].
6
cos( )
It is seen in (2.10) that each harmonic (ith harmonic) produces a DC component
0( )i
I b and other AC components. The total current depends on all of the harmonics.
Sinceω ωi ≠ j, ∀ ≠ , cross-modulation among them does not produce any DC i j component. Thus, the DC current component of iD1can be viewed as the result of DC components produced by the corresponding harmonics.
For small signal detection, where thebi'sare small,
2 Therefore, the DC current will be:
1 Similarly, since identical DC current sources are used.
1 2 2 Combining (2.1) and (2.13),
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,2
It shows that the output voltage is linearly proportional to the sum of the squares of all harmonics’ amplitudes, which corresponds to the total power. However, no mathematical analysis for the linear region is given in [3] any further. Maybe analysis for multi-tone large signal detection will be another interesting research topic in the future.
Fig. 2-3 Frequency response of the Meyer power detector
Fig. 2-3 shows that the Meyer PD can work in the GHz range. The low frequency response depends on the size of the loading capacitor.
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2.3 Logarithmic amplifier
2.3.1 Ideal logarithmic transfer function
The general transfer function of a logarithmic amplifier can be given as [13]
1log 1log
out in
V = K V +K K2 (2.8) where K1 and K2 are constants associated with the logarithmic amplifier. Fig. 2-2 shows the equation above graphically with three sets of K1 and K2. The design parameter K2 can be solved by setting Vout =0
In Fig. 2-3(a) K2 can be visualized to determine the starting point of logarithmic action. The larger K2, the smaller Vin for Vout =0. Increasing K1 changes the degree of output compression. However, Fig. 2-3(b) is the best illustration which has a logarithmic x-axis. As can be seen, the output is a straight line. We will go one step further and define the x-axis in terms of dBm, as depicted in Fig. 2-3(c).
The corresponding voltage magnitude of RF power referring to 50Ohm can be expressed as:
Substituting (2.10) into (2.8)
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30 Thus, (2.11) is a straight line with logarithmic slope (LS) of
1
The start of logarithmic action
out 0
dBm
V
Vin = , the input power level that makes output voltage equals to zero, may be found from (2.11) as:
20( 1 log 2) 30
in dBm
V = − − K +
(2.13) By (2.13), the zero crossing points in Fig. 2-3 can be calculated for K2=1,2 respectively. The designer usually controls the starting point and LS of a logarithmic transfer function to the desired values.
(a)
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(b)
(c)
Fig. 2-4 Logarithmic transfer curve (a) in linear scale (b) in log scale (c) The corresponding RF input power of
Vin Vin
Vin
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2.3.2 Transfer function implementations
An inverting OP amp with PN-junction feedback and successive detection are mainly the two approaches of implementing the logarithmic transfer function. Fig. 2 -5 gives an example of PN-junction based log amp.
Fig. 2-5 PN-junction based log amp
Since the bipolar transistor forms a negative feedback around the OP amp, the current passing through R and the bipolar transistor can be expressed as follows:
exp[ 1] *exp[ ] So the output can be derived as:
*ln in However, this type of log amp has limited dynamic range at high frequencies due to the gain-bandwidth product limitation [16]. As such, the PN-junction has strong temperature dependency and affects the accuracy. Furthermore, offset voltages has to be compensated at very low signal levels.
An alternative structure is the successive detection based on the piecewise-linear approximation of the logarithmic transfer function. It has commonly been used because of better accuracy [13]-[20]. Fig. 2-6(a) is the principle diagram of the successive detection log amp and Fig. 2-6(c) shows circuit building clocks of a typical successive detection log amp.
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Each stage represents a linear limiting amplifier that has the transfer curve shown in Fig. 2-6(b), where AV is the gain and is the maximum output of the limiting amplifier. When the input of each limiting stage exceeds
VL
L V
V
A , the output will be saturated to . So it is very straight forward to see that when increases slowly, stage n will be saturated first, then stage (n-1), and so on until all stages are limited.
V
L Vin= A and increasesAV times larger each step until all stages are limited (let n=4).
Σ
L
V
V A
Fig. 2-6 (a) Principle diagram of successive detection logarithmic amplifier (b) Limiting amplifier transfer curve (c) Circuit block diagram
Here, we give a simple example of logarithmic amplifier that convert 70 dB dynamic range from -60 to10dBm (0.1mV~1000mV) input into a 0~1.8V output with four stages of limiting amplifier. Since four stages are used, then and choose . The first transition point is at -50dBm, and means that
4VL≤ 81.
L 0.45 V =
4 1
L v
V mV
A = andAV =4.605. Fig. 2-7 is the simulation done by behavior model in
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ADS environment.
The logarithmic function is useful but at the cost of hardware and design complexities. The following two chapters are some RF power detection designs that use comparing methods instead of trying to obtain the absolute power levels.
1 1E1 1E2
Fig. 2-7 Behavior model simulation of a log amp (a) Vout vs. Vin in log-scale (b) Vout vs. corresponding of Vin to 50Ohm
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Chapter III
RF power detection circuit design in WiMAX transmitter
3.1 Motivation
The standard of IEEE 802.16 family, popularly known as WiMAX, provides wireless transmissions of high data rates over metropolitan areas. The transmitted signal format may include complicated modulation such as 64-QAM. To ensure correct data receiving, the measure of EVM (error vector magnitude) quantifies the error of transmitted signals and defines the performance of digital radio transmitters.
It is therefore critical to minimize the EVM. Many non-ideal circuit effects contribute to EVM degradation in the RF end, including LO phase noise, carrier feed-through, I/Q imbalance, and nonlinearity. The normal figure of transmitter circuitry achieves the level from -20dB to -25dB. In the latest released WiMAX mobile standard, however, it defines a severe EVM level of -30dB which implies more advanced circuit designs is necessary.
Fig. 3-1 is the architecture of the proposed direct up-conversion mixer with auto-calibration for I/Q imbalance and LO feedthrough. The IF and RF frequency is designed at 10MHz and 2.6GHz respectively. The dotted box is the open loop design done by me senior [1]. It consists of two LO buffers to tune the gain/phase mismatch errors and IDACs on the transconductance stage of the Gilbert cell mixers to suppress the LO feedthrough. All of them are digitally controlled by the 3-wire shift register.
In order to accomplish an auto-calibrated closed loop system, a RF power
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detection circuitry that consists of a pre-amplifier, a power detector, sample and hold circuit (S/H), and a comparator is necessary. This RF to digital interface first samples the RF power of a bit and holds the converted DC output of the PD. After that, we tune the next control bit, this signal is also converted to DC by the PD. The comparator distinguishes which one if larger and gives logic output to the digital circuits to tune the bit higher or lower.
In LO feedthrough compensation mode, baseband signals are not fed to the mixers so that LO feedthrough signals can be directly detected at the RF output of the mixers. Fig. 3-2(a) plots the simulation results of LO feedthrough of one side of the differential output. An external balun is used to combine the differential output of I/Q mixer since the power detection circuit is single-ended input. Fig. 3-2(b) is the calculation of equivalent output voltage of the balun to 50 Ohm.
In gain imbalance compensation mode, we use baseband test vectors (A,0) and (0,A). The gain imbalance can be suppressed which means the ratio of the output power is minimized by tuning the LO Q buffer. In phase calibration mode, we use baseband vectors (A,A) and (A,-A) and the phase mismatch is minimized by tuning the I buffer. According to my senior’s simulation and calculations, the levels of RF output signals during gain and phase calibration are the same. However, the bit difference of gain error is smaller which means phase error can be detected so long as gain error is detected. Fig. 3-3(a) plots the simulation results of gain error and Fig.
3-3(b) is the equivalent output voltage of the balun to 50 Ohm.
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Vθ
Vθ
Fig .3-1 Direct up-conversion mixer with auto-calibration for I/Q imbalance and LO feedthrough
(a)
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(b)
Fig. 3-2 (a) LO feedthrough of one side of the I/Q mixer’s output vs. control bits (b) Related output voltage after balun vs. control bits
(a)
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(b)
Fig. 3-3 (a) The RF output signal of I/Q mixer’s during gain error test vs. control bits (b) Related output voltage after balun vs. control bits
3.2 RF power detection circuit design
From the previous section, we can know that detection circuit must be capable to detect wide dynamic and small differences RF signals, such as LO feedthrough from 0.84mV to 11.14mV with minimum bit difference of 0.66mV and gain error signal from 321mV to 516mV with minimum bit difference of 2.9mV.
Fig. 3-4(a) and (b) are the architecture and schematic of the RF detection block.
In order to have lower losses, a source follower (SF) is employed as an input buffer at the front-end of the detection path. Since only the linear region of a Meyer PD can produces a comparable input for the comparator, small LO signals need to be amplified first. Therefore, the detection path is divided into two: an amplification path for the LO leakage and a bypassing path or the gain/phase error. A simple control switch is used o choose which path is turned on. The Meyer PD then converts the
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detected RF signals to a DC level. However, not only the DC output levels but also their differences are too low for the comparator to compare. An additional PD buffer is necessary to amplify the DC signals once again. Besides, it also supports a good isolation between the Meyer PD and the comparator. The following are some descriptions for each circuit building block.
Latch Input buffer
Pre-amp
Path control
Meyer PD PD buffer
Cs
Cs Comparator
(a)
(b)
Fig. 3-4 (a) RF power detection architecture (b) Schematic of the RF power detection circuits before the comparator
3.2.1 Input buffer
As depicted in Fig. 3-4(b), the source follower is designed to match 50 Ohm taking the parasitic effects of pad and bond wire into account. Hence, measurements
21
can be made with open loop design or alone. If the size of Rbias it too large, the source follower output impedance contains an inductive component. The dependence of this inductive component upon Rbias implies that if a source follower is driven by a large resistance, then it exhibits substantial inductive behavior [22]. Here, a small size of 50Ohm is used both for preventing this effect and matching to the input 50Ohm port.
Fig. 3-5 is the simulation result of the input impedance of the RF detection circuit. It shows that a smaller than -20dB of input return loss is sufficient.
Vctrl=0.000
Fig. 3-5 Simulation of input matching
3.2.2 Pre-amplifier
The pre-amplifier uses a simple cascode topology with inductive shunt peaking
22
to amplify the LO feedthrough signals with 25dB at 2.59~2.61GHz. Fig. 3-6 is the simulation results of the switching path in amplification mode and bypass mode.
1.5 2.0 2.5 3.0 3.5
Fig. 3-6 Simulation of the switching path
3.2.3 Meyer power detector & PD buffer
As discussed in the previous chapter, there are two regions in the transfer curve of the Meyer PD: square law and linear. If the square law region is used, the output voltage is too small to compare. So it is necessary to add a stage of log amp. In order to reduce the circuit complexities and to save power, we use the linear region instead.
The schematic of the Meyer PD is the same as Fig. 2-2. In order to make the M1 and M2’s sub-threshold current sources Ib1 and Ib2 work at their saturation region properly, the dimensions of M1 and M2 are chosen as large as 5um*50/0.18um. As depicted in Fig. 3-7(a), the transfer curve of a Meyer PD is plotted a little bit different from Fig. 2-2, which x-axis and y-axis are changed to linear voltage, so as to make observations of linear region easier. Fig. 3-7(b) shows the slope of Fig. 3-7(a). As can be seen, the slope of the Meyer PD is below unity. It implies that the output difference of each bit is below the comparable difference. Notice that the comparator’s threshold
23
voltage is assumed conservatively 1.3mV.
A PD buffer, which is a simple differential-pair, is added to solve this problem.
As shown in Fig. 3-8(a) the differential pair is designed to have a wide linear input range. Fig. 3-8(b) plots the slope of Fig. 3-8(a) to check how much the bit difference can be amplified. In practical implementations, DC offsets is unpreventable both on the Meyer PD and PD buffer. As indicated in Fig. 3-4(b), the DC offset is compensated by tuning the current sources of the Meyer PD and observing the DC output voltage of the PD buffer. Fig. 3-9 is the combination simulation results of the circuits before the comparator. Fig. 3-9(a) is a 0.84mV, 2.59GHz input signal and changes 0.66mV larger after 2usec. Fig. 3-9(b) shows that the DC output difference of the PD buffer changes 3mV larger.
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
(b)
Fig. 3-7 (a) Meyer PD transfer curve (b) slope of the transfer curve
0.1 0.2 0.3 0.4
Fig. 3-8 (a) PD buffer transfer curve (b) slope of the transfer curve
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1. 998 1. 999 2. 000 2. 001 2. 002 2. 003
Fig. 3-9 Simulation results of the circuits before comparator
3.2.4 Comparator
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Fig. 3-10 Schematic of comparator (a) Pre-amplifier (b) Latch
Fig. 3-10 is the schematic of the comparator employed in the power detection circuitry. This topology merges S/H and comparator together. In order to prevent kickback noise, the comparator is separated into pre-amp and latch. The differential mode gain of the cross couple load of the pre-amp can be expressed as (3.1). The
Fig. 3-10 is the schematic of the comparator employed in the power detection circuitry. This topology merges S/H and comparator together. In order to prevent kickback noise, the comparator is separated into pre-amp and latch. The differential mode gain of the cross couple load of the pre-amp can be expressed as (3.1). The