R-72R voltage attenuator

A new configuration of R-72R voltage attenuator is proposed to deal with the process variation problems of the DSA. The bottleneck of DSA design is that specific power attenuation levels can only be generated by certain resistor values of an

πattenuator and causes both matching and attenuation level varies with the process and temperature variations dependently. Intuitively speaking, relative voltage division by means of resistor string can be independent of any process and temperature variations. Here, we utilize this characteristic to design a voltage attenuator with -1dB/step.

The following equations show the required relative resistor values to produce a -1dB attenuation, depicted in Fig. 4-21(a).

1 1 Thus -1dB attenuation can be achieved by the voltage division of R and 8R coincidentally. Notice that the actual attenuation level of R and 8R is -1.023dB but we still approximate it as - 1dB.

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Fig. 4-21 (a) -1dB calculation (b) -1&-2dB calculation (c) R-72R ladder where R is an arbitrary value.

Fig. 4-22 shows a simulation result of the R-72R ladder in Fig. 4-21(c). Notice that 72R is an enormous value if we use identical resistors for R. By replacing 8R with R, R with 8 parallel R, and 72R with 9 series R, the number of resistors used is reduced.

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1E1 1E2 1E3 1E4 1E5 1E6 1E7 1E8 1E9

Fig. 4-22 Simulation result of the R-72R ladder

4.3.3 R-72R ladder and power detector combination

The BIST circuitry would definitely need a high input impedance (in contrast to 50Ohm) to minimize the loading effects to our CUT since we move the attenuation circuit from power domain to voltage domain. It also implies that the power detector acting as the following stage of the R-72R ladder needs an even higher input impedance in order not to break the excellent voltage division relation of the ladder.

The schematics depicted in Fig. 4 are the history of several combination ideas.

A very straight forward approach is to add switches as path control between the ladder and the PD which is shown in Fig. 4-23(a). Varactors are used for bypass capacitors instead of MIM capacitors to minimize the area of BIST circuitry. Besides, an additional source follower is employed as a buffer between CUT and BIST module.

A resistor of 9R is added for high impedance loading at the buffer’s output. Although the input impedance of the PD can be designed as high as possible, the voltage division relation is drastically effected by the loading of PD flipping around the

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output nodes of the ladder. An alternative approach depicted in Fig. 4-23(b) adds dummy loadings whose values are the same with the PD. When one of the attenuation paths is selected, the others are switched to the dummy loadings to make the loading of the ladder fixed. However, the area of switch is increased two times and the exact input impedance of the PD is difficult to implement. The approach depicted in Fig, 4-23(c) is the best I can think of. In this configuration, identical PDs with extremely high input impedance are used. The simulation of input impedance of a PD wibb be shown in the next section. The PDs can all share the common part, RLOAD and low pass filter, in order to minimize the area.

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Fig. 4-23 Combination ideas

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4.3.4 Current amp PD with high input impedance

The current amp PD is re-designed to an extremely high impedance by using.

The parasitic effects can be by selecting a small dimension MOS. Fig. 4-24(a) plots the real part. Fig. 4-24(b) is a check of the PD curve. A 15mV of DC output difference between -24 and -25dBm input power relaxes the design of comparator’s threshold voltage. With input power 17.78mV (-25dBm to 50Ohm), Fig. 4-24(c) shows the response time of the PD to reach its steady state is around 100nsecs. Since small size of the MOS are used, current consumption is only 87.87uA for the turn on PD cell plus a total of 10.15 (7*1.45uA) for the turned off cells.

(a)

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(b)

(c)

Fig. 4-24 High impedance power detector (a) real part of input impedance (b) PD transfer curve (c) Transient response

4.3.5 Comparator

In this version of RF BIST design, a comparator is integrated in for function completeness. Fig. 4-25 is a brief review of the conventional input offset cancellation mechanism. Vos is the input offset voltage and V1, V2 are the two voltages to be compared. CLK1a advances CLK1 a bit to let the circuit only affected by the charge injection of SW1. In CLK1, both V1 and the offset voltage are stored into the sampling capacitor, Cs. The voltage stored can be expressed as:

1 -1

Vc V A Vos

= A

+ (4.14) where A is the gain of the comparator.

In CLK2, the output voltage Vo can be expressed as:

2 1 The equation above indicates a larger gain can compress the offset voltage.

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Fig. 4-25 Input offset cancellation

Since the PD needs 100nsec to reach its steady state, we arranged another 100nsec of margin for storing or comparing. Thus, the clock width will be 200nsec (period of 400nsec) for CLK1a, CLK1, and CLK2. This means that a high speed comparator is not required.

Depicted in Fig. 4-26, a conventional single-end output OP amp is employed for the comparator. The transistor Mz operates as a null resistor to eliminate the effect of RHP zero from feedforward through the compensating capacitor, Cc. In order to speed up the comparison time, we can disconnect the compensating capacitor during the comparison phase. In the storing phase, the OP amp acts like a unity gain buffer which has stability issues, we can then connect Cc back again. Two extra inverters are placed to make the compared output reaches an accurate logic level.

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Fig. 4-26 Schematic of the comparator

4.3.6 Modified BIST architecture

Fig. 4-27(a) is a modified BIST architecture that replaces the DSA with R-72R ladder and also integrates a comparator into it. An identical buffer is added between the CUT and the RF output port so as to make measure comparable to the BIST module. CLK1, CLK1a and CLK2 are arranged for merging the input offset cancellation techniques of a comparator and the BIST loop together. A 3 to 8 decoder is added to minimize the number of the control pads. The NAND gates are adopted for enable control of the whole path Fig. 4(b). Although clocks are usually undesirable to appear in RF frontends, they are used only in off-line tests.

The operating mode is indicated in Fig. 4(b) where the CLK2 is turn off and the buffer in the BIST module is shut down in order to make our CUT operates normally.

The test mode can be separated into two timings, CLK1 and CLK2. In CLK1 phase as Fig. 4(c), the RF test signal is converted to a DC level by means of the PD1 and then stored in the sampling capacitor, Cin. Beside, input offset of the comparator is also stored in the sampling capacitor. A little bit of different from the former design is that

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the PD1 must also match with the test port. In CLK2 phase as Fig. 4(d), the test signal travels through the CUT, the R-72R ladder, and finally compares with the voltage stored. By few bits of iterations, the gain of the CUT can be readout from us.

Fig. 4-27 (a) Modified BIST architecture (b) operating mode (c) & (d) test mode

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4.4 Summary

The BIST design of a 5GHz that uses power comparing method is fabricated in TSMC 0.18um technology, consist of a 5GHz LNA as CUT, two power detectors, digital step attenuator. However, function verifications cannot be made due to antenna effect. Only partial measurements are made: S parameters, P1dB, and noise figure of LNA, power detector. Table 3 is the performance comparison table of recent RF BIST designs. The variations issues that cause error in the BIST function are explored. An alternative approach of R-72R ladder is proposed that is tolerance to PT variations.

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Table 3 Compare with recent RF BIST designs

CUT/performance LNA VGA LNA LNA

CUT Testable items Gain

P1dB

Chapter V

Conclusion and future work

5.1 Conclusion

In this thesis, two application circuits of RF power detector are designed. The main design principle is using power comparing instead of obtaining the absolute power levels. The first application is the power detection design in WiMAX transmitter. Although fabrication was not made, a design methodology is given. The architecture is suitable for wide dynamic range detection and small difference comparing.

Another application of RF power detector is the BIST design for a 5GHz LNA.

The circuit under test is test by a variable attenuation and power comparing.

Unfortunately, function verifications cannot be made due violations of the antenna rule.

5.2 Future work

For the auto-calibrated IQ modulator, the 3-wire needs to be re-designed o avoid latch up. The power detection design can be integrated in the open loop chip for function completeness.

The modified BIST architecture is proposed. Further design and chip implementations can be made. Layout of digital controls of attenuation path should avoid large pieces of metal connecting to their gates.

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Vita

謝易耕 Yi-Keng Hsieh 出生日期: 1983/05/29 出生地:台北,台灣 教育程度:

2002/09~2006/06

國立交通大學電機與控制工程學系學士 2006/08~2008/08

國立交通大學電子研究所 碩士

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