Chapter II Fundamentals of RF detection circuits
2.3 Logarithmic amplifier
2.3.1 Ideal logarithmic transfer function
The general transfer function of a logarithmic amplifier can be given as [13]
1log 1log
out in
V = K V +K K2 (2.8) where K1 and K2 are constants associated with the logarithmic amplifier. Fig. 2-2 shows the equation above graphically with three sets of K1 and K2. The design parameter K2 can be solved by setting Vout =0
In Fig. 2-3(a) K2 can be visualized to determine the starting point of logarithmic action. The larger K2, the smaller Vin for Vout =0. Increasing K1 changes the degree of output compression. However, Fig. 2-3(b) is the best illustration which has a logarithmic x-axis. As can be seen, the output is a straight line. We will go one step further and define the x-axis in terms of dBm, as depicted in Fig. 2-3(c).
The corresponding voltage magnitude of RF power referring to 50Ohm can be expressed as:
Substituting (2.10) into (2.8)
9
30 Thus, (2.11) is a straight line with logarithmic slope (LS) of
1
The start of logarithmic action
out 0
dBm
V
Vin = , the input power level that makes output voltage equals to zero, may be found from (2.11) as:
20( 1 log 2) 30
in dBm
V = − − K +
(2.13) By (2.13), the zero crossing points in Fig. 2-3 can be calculated for K2=1,2 respectively. The designer usually controls the starting point and LS of a logarithmic transfer function to the desired values.
(a)
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(b)
(c)
Fig. 2-4 Logarithmic transfer curve (a) in linear scale (b) in log scale (c) The corresponding RF input power of
Vin Vin
Vin
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2.3.2 Transfer function implementations
An inverting OP amp with PN-junction feedback and successive detection are mainly the two approaches of implementing the logarithmic transfer function. Fig. 2 -5 gives an example of PN-junction based log amp.
Fig. 2-5 PN-junction based log amp
Since the bipolar transistor forms a negative feedback around the OP amp, the current passing through R and the bipolar transistor can be expressed as follows:
exp[ 1] *exp[ ] So the output can be derived as:
*ln in However, this type of log amp has limited dynamic range at high frequencies due to the gain-bandwidth product limitation [16]. As such, the PN-junction has strong temperature dependency and affects the accuracy. Furthermore, offset voltages has to be compensated at very low signal levels.
An alternative structure is the successive detection based on the piecewise-linear approximation of the logarithmic transfer function. It has commonly been used because of better accuracy [13]-[20]. Fig. 2-6(a) is the principle diagram of the successive detection log amp and Fig. 2-6(c) shows circuit building clocks of a typical successive detection log amp.
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Each stage represents a linear limiting amplifier that has the transfer curve shown in Fig. 2-6(b), where AV is the gain and is the maximum output of the limiting amplifier. When the input of each limiting stage exceeds
VL
L V
V
A , the output will be saturated to . So it is very straight forward to see that when increases slowly, stage n will be saturated first, then stage (n-1), and so on until all stages are limited.
V
L Vin= A and increasesAV times larger each step until all stages are limited (let n=4).
Σ
L
V
V A
Fig. 2-6 (a) Principle diagram of successive detection logarithmic amplifier (b) Limiting amplifier transfer curve (c) Circuit block diagram
Here, we give a simple example of logarithmic amplifier that convert 70 dB dynamic range from -60 to10dBm (0.1mV~1000mV) input into a 0~1.8V output with four stages of limiting amplifier. Since four stages are used, then and choose . The first transition point is at -50dBm, and means that
4VL≤ 81.
L 0.45 V =
4 1
L v
V mV
A = andAV =4.605. Fig. 2-7 is the simulation done by behavior model in
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ADS environment.
The logarithmic function is useful but at the cost of hardware and design complexities. The following two chapters are some RF power detection designs that use comparing methods instead of trying to obtain the absolute power levels.
1 1E1 1E2
Fig. 2-7 Behavior model simulation of a log amp (a) Vout vs. Vin in log-scale (b) Vout vs. corresponding of Vin to 50Ohm
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Chapter III
RF power detection circuit design in WiMAX transmitter
3.1 Motivation
The standard of IEEE 802.16 family, popularly known as WiMAX, provides wireless transmissions of high data rates over metropolitan areas. The transmitted signal format may include complicated modulation such as 64-QAM. To ensure correct data receiving, the measure of EVM (error vector magnitude) quantifies the error of transmitted signals and defines the performance of digital radio transmitters.
It is therefore critical to minimize the EVM. Many non-ideal circuit effects contribute to EVM degradation in the RF end, including LO phase noise, carrier feed-through, I/Q imbalance, and nonlinearity. The normal figure of transmitter circuitry achieves the level from -20dB to -25dB. In the latest released WiMAX mobile standard, however, it defines a severe EVM level of -30dB which implies more advanced circuit designs is necessary.
Fig. 3-1 is the architecture of the proposed direct up-conversion mixer with auto-calibration for I/Q imbalance and LO feedthrough. The IF and RF frequency is designed at 10MHz and 2.6GHz respectively. The dotted box is the open loop design done by me senior [1]. It consists of two LO buffers to tune the gain/phase mismatch errors and IDACs on the transconductance stage of the Gilbert cell mixers to suppress the LO feedthrough. All of them are digitally controlled by the 3-wire shift register.
In order to accomplish an auto-calibrated closed loop system, a RF power
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detection circuitry that consists of a pre-amplifier, a power detector, sample and hold circuit (S/H), and a comparator is necessary. This RF to digital interface first samples the RF power of a bit and holds the converted DC output of the PD. After that, we tune the next control bit, this signal is also converted to DC by the PD. The comparator distinguishes which one if larger and gives logic output to the digital circuits to tune the bit higher or lower.
In LO feedthrough compensation mode, baseband signals are not fed to the mixers so that LO feedthrough signals can be directly detected at the RF output of the mixers. Fig. 3-2(a) plots the simulation results of LO feedthrough of one side of the differential output. An external balun is used to combine the differential output of I/Q mixer since the power detection circuit is single-ended input. Fig. 3-2(b) is the calculation of equivalent output voltage of the balun to 50 Ohm.
In gain imbalance compensation mode, we use baseband test vectors (A,0) and (0,A). The gain imbalance can be suppressed which means the ratio of the output power is minimized by tuning the LO Q buffer. In phase calibration mode, we use baseband vectors (A,A) and (A,-A) and the phase mismatch is minimized by tuning the I buffer. According to my senior’s simulation and calculations, the levels of RF output signals during gain and phase calibration are the same. However, the bit difference of gain error is smaller which means phase error can be detected so long as gain error is detected. Fig. 3-3(a) plots the simulation results of gain error and Fig.
3-3(b) is the equivalent output voltage of the balun to 50 Ohm.
17
Vθ
Vθ
Fig .3-1 Direct up-conversion mixer with auto-calibration for I/Q imbalance and LO feedthrough
(a)
18
(b)
Fig. 3-2 (a) LO feedthrough of one side of the I/Q mixer’s output vs. control bits (b) Related output voltage after balun vs. control bits
(a)
19
(b)
Fig. 3-3 (a) The RF output signal of I/Q mixer’s during gain error test vs. control bits (b) Related output voltage after balun vs. control bits
3.2 RF power detection circuit design
From the previous section, we can know that detection circuit must be capable to detect wide dynamic and small differences RF signals, such as LO feedthrough from 0.84mV to 11.14mV with minimum bit difference of 0.66mV and gain error signal from 321mV to 516mV with minimum bit difference of 2.9mV.
Fig. 3-4(a) and (b) are the architecture and schematic of the RF detection block.
In order to have lower losses, a source follower (SF) is employed as an input buffer at the front-end of the detection path. Since only the linear region of a Meyer PD can produces a comparable input for the comparator, small LO signals need to be amplified first. Therefore, the detection path is divided into two: an amplification path for the LO leakage and a bypassing path or the gain/phase error. A simple control switch is used o choose which path is turned on. The Meyer PD then converts the
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detected RF signals to a DC level. However, not only the DC output levels but also their differences are too low for the comparator to compare. An additional PD buffer is necessary to amplify the DC signals once again. Besides, it also supports a good isolation between the Meyer PD and the comparator. The following are some descriptions for each circuit building block.
Latch Input buffer
Pre-amp
Path control
Meyer PD PD buffer
Cs
Cs Comparator
(a)
(b)
Fig. 3-4 (a) RF power detection architecture (b) Schematic of the RF power detection circuits before the comparator
3.2.1 Input buffer
As depicted in Fig. 3-4(b), the source follower is designed to match 50 Ohm taking the parasitic effects of pad and bond wire into account. Hence, measurements
21
can be made with open loop design or alone. If the size of Rbias it too large, the source follower output impedance contains an inductive component. The dependence of this inductive component upon Rbias implies that if a source follower is driven by a large resistance, then it exhibits substantial inductive behavior [22]. Here, a small size of 50Ohm is used both for preventing this effect and matching to the input 50Ohm port.
Fig. 3-5 is the simulation result of the input impedance of the RF detection circuit. It shows that a smaller than -20dB of input return loss is sufficient.
Vctrl=0.000
Fig. 3-5 Simulation of input matching
3.2.2 Pre-amplifier
The pre-amplifier uses a simple cascode topology with inductive shunt peaking
22
to amplify the LO feedthrough signals with 25dB at 2.59~2.61GHz. Fig. 3-6 is the simulation results of the switching path in amplification mode and bypass mode.
1.5 2.0 2.5 3.0 3.5
Fig. 3-6 Simulation of the switching path
3.2.3 Meyer power detector & PD buffer
As discussed in the previous chapter, there are two regions in the transfer curve of the Meyer PD: square law and linear. If the square law region is used, the output voltage is too small to compare. So it is necessary to add a stage of log amp. In order to reduce the circuit complexities and to save power, we use the linear region instead.
The schematic of the Meyer PD is the same as Fig. 2-2. In order to make the M1 and M2’s sub-threshold current sources Ib1 and Ib2 work at their saturation region properly, the dimensions of M1 and M2 are chosen as large as 5um*50/0.18um. As depicted in Fig. 3-7(a), the transfer curve of a Meyer PD is plotted a little bit different from Fig. 2-2, which x-axis and y-axis are changed to linear voltage, so as to make observations of linear region easier. Fig. 3-7(b) shows the slope of Fig. 3-7(a). As can be seen, the slope of the Meyer PD is below unity. It implies that the output difference of each bit is below the comparable difference. Notice that the comparator’s threshold
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voltage is assumed conservatively 1.3mV.
A PD buffer, which is a simple differential-pair, is added to solve this problem.
As shown in Fig. 3-8(a) the differential pair is designed to have a wide linear input range. Fig. 3-8(b) plots the slope of Fig. 3-8(a) to check how much the bit difference can be amplified. In practical implementations, DC offsets is unpreventable both on the Meyer PD and PD buffer. As indicated in Fig. 3-4(b), the DC offset is compensated by tuning the current sources of the Meyer PD and observing the DC output voltage of the PD buffer. Fig. 3-9 is the combination simulation results of the circuits before the comparator. Fig. 3-9(a) is a 0.84mV, 2.59GHz input signal and changes 0.66mV larger after 2usec. Fig. 3-9(b) shows that the DC output difference of the PD buffer changes 3mV larger.
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
(b)
Fig. 3-7 (a) Meyer PD transfer curve (b) slope of the transfer curve
0.1 0.2 0.3 0.4
Fig. 3-8 (a) PD buffer transfer curve (b) slope of the transfer curve
25
1. 998 1. 999 2. 000 2. 001 2. 002 2. 003
Fig. 3-9 Simulation results of the circuits before comparator
3.2.4 Comparator
26
Fig. 3-10 Schematic of comparator (a) Pre-amplifier (b) Latch
Fig. 3-10 is the schematic of the comparator employed in the power detection circuitry. This topology merges S/H and comparator together. In order to prevent kickback noise, the comparator is separated into pre-amp and latch. The differential mode gain of the cross couple load of the pre-amp can be expressed as (3.1). The common mode gain can be expressed as (3.2).
1,2
5,6 3,4
1
DM m
m m
A G
G G
= − (3.1)
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1,2
Fig. 3-11 Timing of the comparator
In order to compare the RF power of two control bits, the timing is set as Fig. 3-11.
1. CLK1=”1”, CLK1d=”1”, CLK=”0”:
The PD converts the RF output power of the first bit to DC The pre-amplifier acts as a unit gain buffer. Both DC offset and the converted DC output of the first bit, Vtime1 is hold in the sampling capacitor, Cs while latch is in the reset mode and outputs “logic 1”.
2. CLK1=”0”, CLK1d=”1”, CLK=”0”:
After switching to next compensation bit in the open loop circuits, the PD converts RF output power to a DC voltage, Vtime2. The pre-amplifier then compares Vtime1 and Vtime2. DC offset is cancelled. The latch still remains in the reset mode.
3. CLK1=”1”, CLK1d=”1”, CLK=”1”:
The amplified difference of Vtime1 and Vtime2 is past to the latch. The latch pulls it to logic high or low. Fig. 3-12 is the simulation result of the comparator.
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0.002
0.002
Fig. 3-12 Simulation results of the comparator
3.3 Simulation results
The simulation results of LO feedthrough compensating modes and gain error compensating mode is shown in Fig. 3-13.
30
-30 -20 -10 0 10 20 30
-40 40
1.1 1.2 1.3 1.4
1.0 1.5
gain error control bit change
Detection block output (V) 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010
0.000 0.011
0.05 0.10 0.15
0.00 0.20
LO leakage output voltage (V)
Detection block output (V)
Fig. 3-13 Simulation results of (a) gain error (b) LO feedthrough
3.4
Chip layout & summary
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Fig. 3-14 Layout of the RF power detection circuit
Fig. 3-14 is the chip layout in TSMC 0.18m technology. The chip size is mainly limited by the number o pads. Therefore, using large area of RF P-cells for the comparator doesn’t matters. The layout area is 1.055X0.9 mm2.
Unfortunately, the 3-wire control of open loop chip is latched-up and no functional verifications for practical implementations can be made. Hence, the power detection design that is to meet the specifications of that chip has not been fabricated yet. In the future, identifications of the chip failure and re-consider some of the design issues will be made first. After that, we will integrate both designs and complete an auto-calibrated I/Q modulator.
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Chapter IV
Built-in self-test circuit designs for 5GHz LNA
4.1 Introduction
With the mature progress in CMOS technology nowadays, integrating more and more functional analog and digital building blocks into a single chip solution is a trend. However, this increases not only the cost but also the complexities of test.
Embedded built-in self-test (BIST) on chip seems to be a good solution. In contrast to digital and analog circuits that BIST has been widely utilized, RF BIST circuit designs are still in the early-age development.
The recent proposed BIST architectures can be categorized into loop back test for overall RF transceiver [8] and individual circuit block tests with the aid of embedded power detectors (or RMS detectors) [6]-[10]. The latter testing methods depend on the accuracy of power detector (PD) to measure the absolute input and output power level of the circuit under test (CUT). As such, a logarithmic amplifier (Log amp) is necessary to convert the output level from dB-linear into linear scale [10].
In this chapter we proposed a power comparing method to monitor the status of the CUT. This technique alleviates the loading of the PDs and shifts the accuracy difficulties to a digital step attenuator (DSA). Meanwhile, a low dynamic range PD is sufficient. By using a 3-bit digital control, the goal of monitoring our CUT, a 5GHz low noise amplifier (LNA) can be achieved. Moreover, an invention of the R-72R that deals with the process variations of the most critical block of the BIST circuitry, the DSA, is also introduced in this chapter.
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Section 4.2 gives detailed descriptions of RF BIST design with a digital step attenuator. Both simulation results and experimental are also shown in this section. In Section 4.3, a new configuration of R-72R ladder gives a solution to the process variation issue in Section 4.2. Last, a conclusion and summary is given in Section 4.4.
4.2 RF BIST design with a digital step attenuator
4.2.1 The BIST architecture
Fig. 4-1 Proposed BIST architecture
Fig. 4-1 is the proposed BIST architecture including a 15.XXdB 5GHz LNA as our CUT and the BIST module. Two PDs are employed to convert RF signals into DC levels. The switch at the left hand side (SWA) contributes -2dB attenuation. The switch at the right hand side (SWB) along with a 3 bit 8 level DSA contributes a tunable attenuation from -8dB to -15dB. The overall attenuation of the detection circuit is
B
34
therefore -10dB~-17dB. The comparator in the bottom compares the DC levels of Vpd1 and Vpd2. In this work, the comparator has not been integrated in yet. Instead, a DC voltage meter will be used in the measurement to verify the idea.
Fig. 4-2 (a) Operating mode (b) Test mode
As shown in Fig. 4-2, the BIST circuit can be switched between two modes:
(a) Operating mode:
As shown in Fig. 4-2(a), we turn off SWA and SWB in order to make the LNA operates normally. The RF signal delivers from RF
B
in to RFout. We can use network analyzer and signal generator along with spectrum analyzer to do the LNA measurement as what we always do.
(b) Test mode:
As shown in Fig. 4-2(b), we turn on SWA and SWB to connect our CUT with the BIST module and move our input from RF
B
in to RFtest. The test RF signals will be generate from the local oscillator (LO) when this architecture is integrated into a transceiver in the future. For verifying the idea, signal generator will be used instead.
The test signals will be swept around 5GHz since we cannot know exactly whether the CUT is still peaking at 5GHz or not due to the process variations and all kinds of
35
design uncertainties. The test power level cannot be too high a level due to the linearity of the CUT and cannot be set too low that will generate a too low DC level from the PD. Thus, I fixed it at an appropriate value of -25dBm.
As indicated in Fig. 4-2(b), there are two paths for the 5GHz test signal. It travels downwards to let PD1 convert it into a DC level Vpd1. It travels upwards through SWA, CUT (LNA), SWB, DSA, and finally PD2 convert it to another DC level Vpd2.
We can tune the 3 control bits of the DSA with 1dB/step.
B
Initially, we start from the control bit 000 which is a lowest attenuation level and Vpd2 will be greater than Vpd1. The comparator will give us a “logic 1” output. By tuning controls bits, the attenuation level increases 1dB higher per bit that eventually makes Vpd2 larger than Vpd1. The comparator output will then switch from “logic 1”
to “logic 0”. At this certain bit, the gain of the CUT can be known by us. In this work, the CUT is designed with the gain of 15~16dB in the TT corner. From Table.1 below, we can know that when we switch from 101 to 110, Vpd (=Vpd2-Vpd1) will switch from positive to negative ideally.
Table 1 Attenuation levels
Control bit Attenuation (dB)
In this version the comparator is not integrated in the BIST module yet.
36
Neglecting the threshold voltage of the comparator, we postulate that Vpd=Vpd2-Vpd1>0, gives “logic 1” and Vpd=Vpd2-Vpd1≦0, gives “logic 0” for simplicity. The following sections are the circuit building blocks in Fig. 4-1.
4.2.2 Low noise amplifier
M2
Fig. 4-3 is the CUT that uses a conventional cascode LNA topology [21]. Ls, Lg, and Cex give us the simultaneous input impedance and noise matching. The transistor
Fig. 4-3 is the CUT that uses a conventional cascode LNA topology [21]. Ls, Lg, and Cex give us the simultaneous input impedance and noise matching. The transistor