Chip layout & summary

Chapter III RF power detection circuit design in WiMAX

3.4 Chip layout & summary

Fig. 3-14 Layout of the RF power detection circuit

Fig. 3-14 is the chip layout in TSMC 0.18m technology. The chip size is mainly limited by the number o pads. Therefore, using large area of RF P-cells for the comparator doesn’t matters. The layout area is 1.055X0.9 mm².

Unfortunately, the 3-wire control of open loop chip is latched-up and no functional verifications for practical implementations can be made. Hence, the power detection design that is to meet the specifications of that chip has not been fabricated yet. In the future, identifications of the chip failure and re-consider some of the design issues will be made first. After that, we will integrate both designs and complete an auto-calibrated I/Q modulator.

Chapter IV

Built-in self-test circuit designs for 5GHz LNA

4.1 Introduction

With the mature progress in CMOS technology nowadays, integrating more and more functional analog and digital building blocks into a single chip solution is a trend. However, this increases not only the cost but also the complexities of test.

Embedded built-in self-test (BIST) on chip seems to be a good solution. In contrast to digital and analog circuits that BIST has been widely utilized, RF BIST circuit designs are still in the early-age development.

The recent proposed BIST architectures can be categorized into loop back test for overall RF transceiver [8] and individual circuit block tests with the aid of embedded power detectors (or RMS detectors) [6]-[10]. The latter testing methods depend on the accuracy of power detector (PD) to measure the absolute input and output power level of the circuit under test (CUT). As such, a logarithmic amplifier (Log amp) is necessary to convert the output level from dB-linear into linear scale [10].

In this chapter we proposed a power comparing method to monitor the status of the CUT. This technique alleviates the loading of the PDs and shifts the accuracy difficulties to a digital step attenuator (DSA). Meanwhile, a low dynamic range PD is sufficient. By using a 3-bit digital control, the goal of monitoring our CUT, a 5GHz low noise amplifier (LNA) can be achieved. Moreover, an invention of the R-72R that deals with the process variations of the most critical block of the BIST circuitry, the DSA, is also introduced in this chapter.

Section 4.2 gives detailed descriptions of RF BIST design with a digital step attenuator. Both simulation results and experimental are also shown in this section. In Section 4.3, a new configuration of R-72R ladder gives a solution to the process variation issue in Section 4.2. Last, a conclusion and summary is given in Section 4.4.

4.2 RF BIST design with a digital step attenuator

4.2.1 The BIST architecture

Fig. 4-1 Proposed BIST architecture

Fig. 4-1 is the proposed BIST architecture including a 15.XXdB 5GHz LNA as our CUT and the BIST module. Two PDs are employed to convert RF signals into DC levels. The switch at the left hand side (SWA) contributes -2dB attenuation. The switch at the right hand side (SW_B) along with a 3 bit 8 level DSA contributes a tunable attenuation from -8dB to -15dB. The overall attenuation of the detection circuit is

therefore -10dB~-17dB. The comparator in the bottom compares the DC levels of Vpd1 and Vpd2. In this work, the comparator has not been integrated in yet. Instead, a DC voltage meter will be used in the measurement to verify the idea.

Fig. 4-2 (a) Operating mode (b) Test mode

As shown in Fig. 4-2, the BIST circuit can be switched between two modes:

(a) Operating mode:

As shown in Fig. 4-2(a), we turn off SWA and SWB in order to make the LNA operates normally. The RF signal delivers from RF

in to RFout. We can use network analyzer and signal generator along with spectrum analyzer to do the LNA measurement as what we always do.

(b) Test mode:

As shown in Fig. 4-2(b), we turn on SW_A and SW_B to connect our CUT with the BIST module and move our input from RF

in to RFtest. The test RF signals will be generate from the local oscillator (LO) when this architecture is integrated into a transceiver in the future. For verifying the idea, signal generator will be used instead.

The test signals will be swept around 5GHz since we cannot know exactly whether the CUT is still peaking at 5GHz or not due to the process variations and all kinds of

design uncertainties. The test power level cannot be too high a level due to the linearity of the CUT and cannot be set too low that will generate a too low DC level from the PD. Thus, I fixed it at an appropriate value of -25dBm.

As indicated in Fig. 4-2(b), there are two paths for the 5GHz test signal. It travels downwards to let PD1 convert it into a DC level Vpd1. It travels upwards through SW_A, CUT (LNA), SW_B, DSA, and finally PD2 convert it to another DC level Vpd2.

We can tune the 3 control bits of the DSA with 1dB/step.

Initially, we start from the control bit 000 which is a lowest attenuation level and Vpd2 will be greater than Vpd1. The comparator will give us a “logic 1” output. By tuning controls bits, the attenuation level increases 1dB higher per bit that eventually makes Vpd2 larger than Vpd1. The comparator output will then switch from “logic 1”

to “logic 0”. At this certain bit, the gain of the CUT can be known by us. In this work, the CUT is designed with the gain of 15~16dB in the TT corner. From Table.1 below, we can know that when we switch from 101 to 110, Vpd (=Vpd2-Vpd1) will switch from positive to negative ideally.

Table 1 Attenuation levels

Control bit Attenuation (dB)

In this version the comparator is not integrated in the BIST module yet.

Neglecting the threshold voltage of the comparator, we postulate that Vpd=Vpd2-Vpd1>0, gives “logic 1” and Vpd=Vpd2-Vpd1≦0, gives “logic 0” for simplicity. The following sections are the circuit building blocks in Fig. 4-1.

4.2.2 Low noise amplifier

Fig. 4-3 is the CUT that uses a conventional cascode LNA topology [21]. Ls, Lg, and Cex give us the simultaneous input impedance and noise matching. The transistor M2 is adopted for excellent reverse isolation and the output LC-tank composed of Ld

and C_dmake the S21 peak at 5GHz. For measurement considerations, a source follower, consists of M3 and M4, is added to match the output port to 50 Ohm.

4.2.3 Switch A (SW

)

Fig. 4-4 Switch A

Depicted in Fig. 4-4, an πattenuator that has -2dB attenuation is adopted for SWA for the sake of matching the CUT with the test port. The linearity issue of the attenuator can be ignored since the test signal is as low as -25dBm. Therefore, resistors of an π attenuator can all be replaced by MOSFETs as switches. A large HRI resistor of several Kilo-Ohms is connected from the bulk of M1 to ground for the purpose of minimizing the parasitic effects. Furthermore, two large resistors RB are connected to from source and drain to ground to prevent DC level uncertainties.

4.2.4 Power detector (PD)

Fig. 4-5 (a) Threshold voltage of the comparator (b) PD characteristic curve

In this BIST architecture, the power detectors are not only to convert RF signals into DC voltages but also need generate a comparable voltage difference for the comparator. In Fig. 4-5(a), we can define the threshold voltage of the comparator as Vx. The comparator outputs a “logic 0” if the input is below it. For the following analysis, we simply model the transfer function of a power detector as:

pd in

V =KV

(4.1) where K is a constant representing the PD characteristic.

The input of the comparator which is the output difference of the PDs can be expressed as: attenuator, and Vtest is the test voltage. We also assume perfect matching to 50Ohm between inter stages. The design parameters will then be simplified to K and Vtest by (4.2). We can know that the larger the K the more relaxed for the comparator.

Employing the Meyer PD in Section 2.2 is the first thought came to mind. However, the following analysis tells us that Meyer PD has its own limitations in this application.

Fig. 4-6 (a) Meyer power detector (b) Current amplifier power detector A bit different from Fig. 2-1, the Meyer PD in Fig. 4-6(a) has input signals on both transistors, M1 and M2.

Using the results of (2.3), the DC current of M1 can be re-written as:

2 4 Since identical current sources are used:

1 2 By means of the Maclaurin Series below,

2 3 4 1 (4.5) can be approximated as:

1 2 2

Depicted in Fig. 4-6(b), the topology of current amplifier PD [3] is adopted to overcome the design difficulties due to small K of Meyer PD. The concept of nonlinearities of a transistor is much similar to Meyer PD if we bias M1 at its sub-threshold region. M2 and M3 compose a current mirror and amplify the sub-threshold current generated from M1 by their ratio. RL then converts this current into voltage. Last, two stages of low pass filter are added to filter out the high

frequencies and just to keep their DC levels.

We can express the descriptions above all in one equation:

2 Therefore, the difference of the PDs’ output can be derived as follow:

2 Obviously, the K for current amp PD can be designed suitable in this application.

Notice that the path in test mode is designed in power domain which is a 50Ohm-environment in order to make the detected voltage closed to the power gain (S21). The bias resistor, Rbias, of PD2 is set to a value near 50Ohm. Since SWA is already has input impedance matched to 50Ohm, we only need a large Rbias for PD1 to minimize the loading effects.

Fig. 4-7 is the simulation results of a current amp PD designed in TSMC 0.18um technology. We can see from Fig. 4-7(a) that the output of the PD rises from its initial DC bias point (517.5mV) when there is a RF signal input. The output reaches its steady state around 25ns. Fig. 4-7(b) is result of the harmonic balance simulation. The input power is swept from -30dBm to 10dBm. The simulation results show that the output difference of -25dBm and -24dBm input is around 3mV which is sufficient for the comparator.

5 10 15 20 25

RF input power (dBm to 50Ohm)

PD DC ouput voltage

(b)

Fig. 4-7 (a) Time response with different input levels (b) DC output voltage vs. input power

4.2.5 Digital step attenuator (DSA)

Fig. 4-8 (a) shows the configuration of the DSA. By switching between the two attenuation levels of the attenuation cell a -8~-15dB with -1dB/step can be achieved.

Fig. 4-8 (b) is the attenuation cell used. Here I called it a

“complementary

π

attenuator”. Matching closed to 50 Ohm while switching between

the two attenuation levels is a merit. Besides this, the signal at the output of the LNA is larger and causes linearity to be an issue. Resistive network, however, has high linearity that will be suitable here. Here, inverter is used to give us D1 and D1b. For larger attenuation levels, we can turn on D1 and turn off D1b to make the series resistance larger and shunt resistance smaller and vice versa for smaller attenuation levels.

Fig. 4-8 (a) Digital step attenuator (b) attenuation cell

In order to make the power gain equal to the voltage gain, the DSA is designed to make the input impedances closed to 50Ohm (or S11<-20dB). Besides, a very linear 1dB-attenuation is necessary simultaneously at each step. Besides the lowest attenuation level -7dB of the DSA itself, an additional 1dB loss is contributed from

SW2 and the AC couple capacitor between the DSA output and the gate of PD’s M1 to make the lowest attenuation of this path -8dB.

Fig. 4-9 are some simulation results of Fig. 4-8 (a) using a -10dBm which has 50Ohm source resistance 5GHz input test tone. Fig. 4-9(a) shows the power level at Vg2 referring to 50Ohm. If we view the DSA as a DAC, the bit difference or DNL can be simply define as:

( ) ( 1)

( ) (LSB)

output power i output power i Bit difference i

− −

(4.11) where LSB equals to 1dB. Fig. 4-9(b) is a plot of bit difference after calculations. Fig.

4-9(c) plots the variations of input impedance.

(a)

(b)

(c)

Fig. 4-9 (a) Output power of the DSA with -10dBm test tone (b) Bit difference (c) Input impedance check

4.2.6 Design guidelines of the DSA

One may wonder how the DSA is designed so perfectly as the Fig. 4-9. No doubt a beginner may spend hours and hours, days and days on trimming owing to the non-idealities of the component values, such as parasitic effects and turn on/off resistance of the MOS. Here, we came up to some design guidelines not great as a theory but just to let us never become an “ADS tuning monkey!” The following steps are the designer’s “know how.” Belief it or not, rapid and efficient design can be made by following them.

Step I: One can first calculate the ideal values of Rs, Rsb, Rp, and Rpb in Fig.

4-8(b). Construct an ideal attenuation cell with the calculated resistor values, an ideal switch, and an inverter. Double check the attenuation levels (or S21) of the two modes and the input impedance Zin. Make sure that one designs one attenuation cell at a time. Please don’t haste to combine the attenuation cells altogether at the very beginning or you might in big trouble.

Step II: Change the ideal series switch to Ms and sweep the dimension of it. Take a glance at both S21 and Zin. One can notice that larger dimensions of Ms result in a more ideal S21. However, this causes the real part of Zin to shrink more than smaller dimensions. One may stupidly want to make the Rsb smaller, since it is series with an on resistance of Ms. However, the results are even worse. The smaller the Rsb, the more Zin shrinks

Step III: Sweep the size of Rp instead. One may notice that by making the size few tens Ohms larger than the calculated value, the results will be closer to the ideal value. Besides, Zin doesn’t shrink anymore. We can conclude shortly that the series branch of an attenuation cell is the most sensitive part. Don’t ever try to change it.

Step IV: Change the ideal parallel switch to Mp. Larger dimension size results in a smaller on resistance and a bigger off capacitance that makes “000” the smallest Zin when combing the attenuation cells together. As Rs, Rsb, and Rp are fixed already from Steps I~III, Rpb is the only degree of freedom left.

Chance of fixing the attenuation cell closer to ideal is to make Mp smaller and Rpb bigger.

Step V: Since the estimated values is given from steps above, change the resistors to practical ones, such as HRI, RP-poly, etc. A little bit of fine tuning the component size afterwards is necessary since there are still some parasitic effects of the practical resistors.

Step VI: Finally, do the same steps to design each attenuation cell and combine them together.

A point to mention is that attenuation cells are easier to design if the difference of the two desired attenuation levels is not so high since Zin won’t be switched so severely.

4.2.7 Post-simulation results

Fig. 4-10 is the results of the operating mode using Cadence Spectre RF and Ansoft Designer for post layout EM simulation. I organized these data in Table 2 that can give us the reference information for the test mode.

(a) Operating mode

SS TT

(b)

Fig. 4-10 Post simulation results of the CUT (a) S11 &S21 (b) Noise figure (c) S11

Smith Chart (d) S22 Smith Chart

Table 2 Performance summary of the CUT in operating mode

Corner case TT SS FF

S21 peak 15.68 dB @5GHz 12.81 dB @4.60GHz 18.35 dB @5.45GHz S11 dip -30.88 dB @5GHz -21.72dB @4.67GHz -31.49dB @5.419dB S22 dip -22.20 dB @5GHz -19.45dB @4.58GHz -26.81dB@5.51dB Noise figure 2.867 dB @5GHz 3.33dB @4.67GHz 2.541dB @5.42dB

(b) Test mode

According to Table 1&2, the zero crossing point of Vpd (Vpd2-V_pd1) should occurs at 101 to 110 for TT corner case, 010 to 011 for SS ideally. Since the gain of the FF corner is out of range, we just consider the quantity is larger than 17dB. The simulation result is plotted in Fig. 4-11. Since the BIST module is designed in TT corner case, its function is correct. However, the zero crossing occurs at 011 to 100 or SS corner which is a bit next to the ideal. This is somewhat tricky. In order to obtain a correct BIST function, an invariable circuit is to test a variable circuit (CUT).

However, we forgot that that the BIST circuitry also varies with process and temperature variations during design. This issue will be discussed further in Section 4.3.

Fig. 4-11 Test mode: The output difference of the two power detectors vs. control bit

4.2.8 Chip implementations and measurement

Fig. 4-12 Die photo

The RF BIST module integrated with a 5GHz LNA is implemented in TSMC 0.18um CMOS technology. Fig. X shows the die photo of the fabricated circuit with total active area (excluding the pads) of 0.698mm x 0.622mm. The BIST area is 10.79% of the active area. MIM capacitors used for AC coupling and low pass filter dominants the whole BIST area. Baseband MOS and resistors which don’t have large area of deep N well guarding them are utilized to minimize the BIST area. Layout techniques such as dummy resistors are used to reduce the mismatches for the DSA.

Unfortunately, the digital controls of the DSA and the power detector back of it are both failed by antenna effects. Therefore, observations of DSA cannot be made.

Without noticing to check the antenna rules, large pieces of metal are connected to the gates of these circuits whose dimensions are designed particularly small, as depicted in Fig 4-13.

Fig. 4-13 Violations of antenna rule

The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. The word “antenna” is somewhat misleading. The problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to/from electrical currents. The antenna effect generates stress-induced leakage currents that can lead to either immediate or delayed failure of the overstressed dielectrics.

A solution to fix violations of the antenna rule is to add M1-Nactives on the biasing resistors for ESD protection.

By the symptoms below, it is confirmed that the chip failure is caused by antenna effect.

(1) Current consumption from VDD is as large as 1.9mA while the other bias voltages of the circuit are off.

(2) Currents passing through the gates of the DSA digital controls are as large as 110mA.

(3) Currents passing through the gate bias of PD2 are as large as 1.23mA

Another problem of the chip is that the maximum gain of the LNA is only around 7dB. We first speculate that the performance of the LNA during maybe affected by the BIST module. Therefore, laser-cut were made on the connections between the LNA and the BIST module. Fig. 4-14 shows the S parameter measurements of the LNA performance before and after after-laser-cutting. It can be see that the gain didn’t enhance greatly. There are ripples on the curve of S21. Fig. 4-15 shows the P1dB is around -12dBm. Measurement result of noise figure is sown in Fig, 4-16.Luckily, PD1 can still be measured, as shown in Fig. 4-17.

4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8

4.0 6.0

0 5

-5 10

freq, GHz

S 21 ( d B)

(a)

3 4 5 6 7

2 8

-45 -40 -35

-50 -30

freq, GHz

S 12 ( d B)

(b)

4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8

4.0 6.0

-15 -10 -5

-20 0

freq, GHz

S 11 ( d B)

(c)

freq (2.000GHz to 8.000GHz)

S11

After laser cut Before laser

cut

(d)

3 4 5 6 7

2 8

-10.5 -10.0 -9.5 -9.0 -8.5

-11.0 -8.0

freq, GHz

S22 (dB)

(e)

freq (2.000GHz to 8.000GHz)

S22

(f)

Fig. 4-14 (a) S21 (b) S12 (c) S11 (d) S11 Smith Chart (e) S22 (f) S22 Smith Chart

Fig. 4-15 P1dB measurements

Fig. 4-16 Noise figure

Fig. 4-17 Power detector curve measurement

4.3 RF BIST design with R-72R Ladder

4.3.1 Variations of the DSA

Fig. 4-18 Observation of process variations for the DSA

The proposed BIST architecture depends on the accuracy of the DSA. This

在文檔中射頻功率偵測器的應用 (頁 43-0)

Chapter III RF power detection circuit design in WiMAX

3.4 Chip layout &amp; summary

Chapter IV

Built-in self-test circuit designs for 5GHz LNA

4.1 Introduction

4.2 RF BIST design with a digital step attenuator

4.2.1 The BIST architecture

4.2.2 Low noise amplifier

4.2.3 Switch A (SW

)

4.2.4 Power detector (PD)

4.2.5 Digital step attenuator (DSA)

π

4.2.6 Design guidelines of the DSA

4.2.7 Post-simulation results

4.2.8 Chip implementations and measurement

4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8

4.0 6.0

0 5

-5 10

freq, GHz

S 21 ( d B)

3 4 5 6 7

2 8

-45 -40 -35

-50 -30

freq, GHz

S 12 ( d B)

4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8

4.0 6.0

-15 -10 -5

-20 0

freq, GHz

S 11 ( d B)

4.3 RF BIST design with R-72R Ladder

4.3.1 Variations of the DSA

3.4 Chip layout & summary