Input buffer - RF power detection circuit design

Chapter III RF power detection circuit design in WiMAX

3.2 RF power detection circuit design

3.2.1 Input buffer

As depicted in Fig. 3-4(b), the source follower is designed to match 50 Ohm taking the parasitic effects of pad and bond wire into account. Hence, measurements

can be made with open loop design or alone. If the size of Rbias it too large, the source follower output impedance contains an inductive component. The dependence of this inductive component upon Rbias implies that if a source follower is driven by a large resistance, then it exhibits substantial inductive behavior [22]. Here, a small size of 50Ohm is used both for preventing this effect and matching to the input 50Ohm port.

Fig. 3-5 is the simulation result of the input impedance of the RF detection circuit. It shows that a smaller than -20dB of input return loss is sufficient.

Vctrl=0.000

Fig. 3-5 Simulation of input matching

3.2.2 Pre-amplifier

The pre-amplifier uses a simple cascode topology with inductive shunt peaking

to amplify the LO feedthrough signals with 25dB at 2.59~2.61GHz. Fig. 3-6 is the simulation results of the switching path in amplification mode and bypass mode.

1.5 2.0 2.5 3.0 3.5

Fig. 3-6 Simulation of the switching path

3.2.3 Meyer power detector & PD buffer

As discussed in the previous chapter, there are two regions in the transfer curve of the Meyer PD: square law and linear. If the square law region is used, the output voltage is too small to compare. So it is necessary to add a stage of log amp. In order to reduce the circuit complexities and to save power, we use the linear region instead.

The schematic of the Meyer PD is the same as Fig. 2-2. In order to make the M1 and M₂’s sub-threshold current sources Ib1 and Ib2 work at their saturation region properly, the dimensions of M1 and M2 are chosen as large as 5um*50/0.18um. As depicted in Fig. 3-7(a), the transfer curve of a Meyer PD is plotted a little bit different from Fig. 2-2, which x-axis and y-axis are changed to linear voltage, so as to make observations of linear region easier. Fig. 3-7(b) shows the slope of Fig. 3-7(a). As can be seen, the slope of the Meyer PD is below unity. It implies that the output difference of each bit is below the comparable difference. Notice that the comparator’s threshold

voltage is assumed conservatively 1.3mV.

A PD buffer, which is a simple differential-pair, is added to solve this problem.

As shown in Fig. 3-8(a) the differential pair is designed to have a wide linear input range. Fig. 3-8(b) plots the slope of Fig. 3-8(a) to check how much the bit difference can be amplified. In practical implementations, DC offsets is unpreventable both on the Meyer PD and PD buffer. As indicated in Fig. 3-4(b), the DC offset is compensated by tuning the current sources of the Meyer PD and observing the DC output voltage of the PD buffer. Fig. 3-9 is the combination simulation results of the circuits before the comparator. Fig. 3-9(a) is a 0.84mV, 2.59GHz input signal and changes 0.66mV larger after 2usec. Fig. 3-9(b) shows that the DC output difference of the PD buffer changes 3mV larger.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

(b)

Fig. 3-7 (a) Meyer PD transfer curve (b) slope of the transfer curve

0.1 0.2 0.3 0.4

Fig. 3-8 (a) PD buffer transfer curve (b) slope of the transfer curve

1. 998 1. 999 2. 000 2. 001 2. 002 2. 003

Fig. 3-9 Simulation results of the circuits before comparator

3.2.4 Comparator

Fig. 3-10 Schematic of comparator (a) Pre-amplifier (b) Latch

Fig. 3-10 is the schematic of the comparator employed in the power detection circuitry. This topology merges S/H and comparator together. In order to prevent kickback noise, the comparator is separated into pre-amp and latch. The differential mode gain of the cross couple load of the pre-amp can be expressed as (3.1). The common mode gain can be expressed as (3.2).

1,2

5,6 3,4

DM m

m m

A G

G G

= − (3.1)

1,2

Fig. 3-11 Timing of the comparator

In order to compare the RF power of two control bits, the timing is set as Fig. 3-11.

1. CLK1=”1”, CLK1d=”1”, CLK=”0”:

The PD converts the RF output power of the first bit to DC The pre-amplifier acts as a unit gain buffer. Both DC offset and the converted DC output of the first bit, V_time1 is hold in the sampling capacitor, Cs while latch is in the reset mode and outputs “logic 1”.

2. CLK1=”0”, CLK1d=”1”, CLK=”0”:

After switching to next compensation bit in the open loop circuits, the PD converts RF output power to a DC voltage, Vtime2. The pre-amplifier then compares Vtime1 and Vtime2. DC offset is cancelled. The latch still remains in the reset mode.

3. CLK1=”1”, CLK1d=”1”, CLK=”1”:

The amplified difference of V_time1 and V_time2 is past to the latch. The latch pulls it to logic high or low. Fig. 3-12 is the simulation result of the comparator.

0.002

Fig. 3-12 Simulation results of the comparator

3.3 Simulation results

The simulation results of LO feedthrough compensating modes and gain error compensating mode is shown in Fig. 3-13.

-30 -20 -10 0 10 20 30

-40 40

1.1 1.2 1.3 1.4

1.0 1.5

gain error control bit change

Detection block output (V) 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010

0.000 0.011

0.05 0.10 0.15

0.00 0.20

LO leakage output voltage (V)

Detection block output (V)

Fig. 3-13 Simulation results of (a) gain error (b) LO feedthrough

3.4 Chip layout & summary

Fig. 3-14 Layout of the RF power detection circuit

Fig. 3-14 is the chip layout in TSMC 0.18m technology. The chip size is mainly limited by the number o pads. Therefore, using large area of RF P-cells for the comparator doesn’t matters. The layout area is 1.055X0.9 mm².

Unfortunately, the 3-wire control of open loop chip is latched-up and no functional verifications for practical implementations can be made. Hence, the power detection design that is to meet the specifications of that chip has not been fabricated yet. In the future, identifications of the chip failure and re-consider some of the design issues will be made first. After that, we will integrate both designs and complete an auto-calibrated I/Q modulator.

Chapter IV

Built-in self-test circuit designs for 5GHz LNA

4.1 Introduction

With the mature progress in CMOS technology nowadays, integrating more and more functional analog and digital building blocks into a single chip solution is a trend. However, this increases not only the cost but also the complexities of test.

Embedded built-in self-test (BIST) on chip seems to be a good solution. In contrast to digital and analog circuits that BIST has been widely utilized, RF BIST circuit designs are still in the early-age development.

The recent proposed BIST architectures can be categorized into loop back test for overall RF transceiver [8] and individual circuit block tests with the aid of embedded power detectors (or RMS detectors) [6]-[10]. The latter testing methods depend on the accuracy of power detector (PD) to measure the absolute input and output power level of the circuit under test (CUT). As such, a logarithmic amplifier (Log amp) is necessary to convert the output level from dB-linear into linear scale [10].

In this chapter we proposed a power comparing method to monitor the status of the CUT. This technique alleviates the loading of the PDs and shifts the accuracy difficulties to a digital step attenuator (DSA). Meanwhile, a low dynamic range PD is sufficient. By using a 3-bit digital control, the goal of monitoring our CUT, a 5GHz low noise amplifier (LNA) can be achieved. Moreover, an invention of the R-72R that deals with the process variations of the most critical block of the BIST circuitry, the DSA, is also introduced in this chapter.

Section 4.2 gives detailed descriptions of RF BIST design with a digital step attenuator. Both simulation results and experimental are also shown in this section. In Section 4.3, a new configuration of R-72R ladder gives a solution to the process variation issue in Section 4.2. Last, a conclusion and summary is given in Section 4.4.

4.2 RF BIST design with a digital step attenuator

4.2.1 The BIST architecture

Fig. 4-1 Proposed BIST architecture

Fig. 4-1 is the proposed BIST architecture including a 15.XXdB 5GHz LNA as our CUT and the BIST module. Two PDs are employed to convert RF signals into DC levels. The switch at the left hand side (SWA) contributes -2dB attenuation. The switch at the right hand side (SW_B) along with a 3 bit 8 level DSA contributes a tunable attenuation from -8dB to -15dB. The overall attenuation of the detection circuit is

therefore -10dB~-17dB. The comparator in the bottom compares the DC levels of Vpd1 and Vpd2. In this work, the comparator has not been integrated in yet. Instead, a DC voltage meter will be used in the measurement to verify the idea.

Fig. 4-2 (a) Operating mode (b) Test mode

As shown in Fig. 4-2, the BIST circuit can be switched between two modes:

(a) Operating mode:

As shown in Fig. 4-2(a), we turn off SWA and SWB in order to make the LNA operates normally. The RF signal delivers from RF

in to RFout. We can use network analyzer and signal generator along with spectrum analyzer to do the LNA measurement as what we always do.

(b) Test mode:

As shown in Fig. 4-2(b), we turn on SW_A and SW_B to connect our CUT with the BIST module and move our input from RF

in to RFtest. The test RF signals will be generate from the local oscillator (LO) when this architecture is integrated into a transceiver in the future. For verifying the idea, signal generator will be used instead.

The test signals will be swept around 5GHz since we cannot know exactly whether the CUT is still peaking at 5GHz or not due to the process variations and all kinds of

design uncertainties. The test power level cannot be too high a level due to the linearity of the CUT and cannot be set too low that will generate a too low DC level from the PD. Thus, I fixed it at an appropriate value of -25dBm.

As indicated in Fig. 4-2(b), there are two paths for the 5GHz test signal. It travels downwards to let PD1 convert it into a DC level Vpd1. It travels upwards through SW_A, CUT (LNA), SW_B, DSA, and finally PD2 convert it to another DC level Vpd2.

We can tune the 3 control bits of the DSA with 1dB/step.

Initially, we start from the control bit 000 which is a lowest attenuation level and Vpd2 will be greater than Vpd1. The comparator will give us a “logic 1” output. By tuning controls bits, the attenuation level increases 1dB higher per bit that eventually makes Vpd2 larger than Vpd1. The comparator output will then switch from “logic 1”

to “logic 0”. At this certain bit, the gain of the CUT can be known by us. In this work, the CUT is designed with the gain of 15~16dB in the TT corner. From Table.1 below, we can know that when we switch from 101 to 110, Vpd (=Vpd2-Vpd1) will switch from positive to negative ideally.

Table 1 Attenuation levels

Control bit Attenuation (dB)

In this version the comparator is not integrated in the BIST module yet.

Neglecting the threshold voltage of the comparator, we postulate that Vpd=Vpd2-Vpd1>0, gives “logic 1” and Vpd=Vpd2-Vpd1≦0, gives “logic 0” for simplicity. The following sections are the circuit building blocks in Fig. 4-1.

4.2.2 Low noise amplifier

Fig. 4-3 is the CUT that uses a conventional cascode LNA topology [21]. Ls, Lg, and Cex give us the simultaneous input impedance and noise matching. The transistor M2 is adopted for excellent reverse isolation and the output LC-tank composed of Ld

and C_dmake the S21 peak at 5GHz. For measurement considerations, a source follower, consists of M3 and M4, is added to match the output port to 50 Ohm.

4.2.3 Switch A (SW

)

Fig. 4-4 Switch A

Depicted in Fig. 4-4, an πattenuator that has -2dB attenuation is adopted for SWA for the sake of matching the CUT with the test port. The linearity issue of the attenuator can be ignored since the test signal is as low as -25dBm. Therefore, resistors of an π attenuator can all be replaced by MOSFETs as switches. A large HRI resistor of several Kilo-Ohms is connected from the bulk of M1 to ground for the purpose of minimizing the parasitic effects. Furthermore, two large resistors RB are connected to from source and drain to ground to prevent DC level uncertainties.

4.2.4 Power detector (PD)

Fig. 4-5 (a) Threshold voltage of the comparator (b) PD characteristic curve

In this BIST architecture, the power detectors are not only to convert RF signals into DC voltages but also need generate a comparable voltage difference for the comparator. In Fig. 4-5(a), we can define the threshold voltage of the comparator as Vx. The comparator outputs a “logic 0” if the input is below it. For the following analysis, we simply model the transfer function of a power detector as:

pd in

V =KV

(4.1) where K is a constant representing the PD characteristic.

The input of the comparator which is the output difference of the PDs can be expressed as: attenuator, and Vtest is the test voltage. We also assume perfect matching to 50Ohm between inter stages. The design parameters will then be simplified to K and Vtest by (4.2). We can know that the larger the K the more relaxed for the comparator.

Employing the Meyer PD in Section 2.2 is the first thought came to mind. However, the following analysis tells us that Meyer PD has its own limitations in this application.

Fig. 4-6 (a) Meyer power detector (b) Current amplifier power detector A bit different from Fig. 2-1, the Meyer PD in Fig. 4-6(a) has input signals on both transistors, M1 and M2.

Using the results of (2.3), the DC current of M1 can be re-written as:

2 4 Since identical current sources are used:

1 2 By means of the Maclaurin Series below,

2 3 4 1 (4.5) can be approximated as:

1 2 2

Depicted in Fig. 4-6(b), the topology of current amplifier PD [3] is adopted to overcome the design difficulties due to small K of Meyer PD. The concept of nonlinearities of a transistor is much similar to Meyer PD if we bias M1 at its sub-threshold region. M2 and M3 compose a current mirror and amplify the sub-threshold current generated from M1 by their ratio. RL then converts this current into voltage. Last, two stages of low pass filter are added to filter out the high

frequencies and just to keep their DC levels.

We can express the descriptions above all in one equation:

2 Therefore, the difference of the PDs’ output can be derived as follow:

2 Obviously, the K for current amp PD can be designed suitable in this application.

Notice that the path in test mode is designed in power domain which is a 50Ohm-environment in order to make the detected voltage closed to the power gain (S21). The bias resistor, Rbias, of PD2 is set to a value near 50Ohm. Since SWA is already has input impedance matched to 50Ohm, we only need a large Rbias for PD1 to minimize the loading effects.

Fig. 4-7 is the simulation results of a current amp PD designed in TSMC 0.18um technology. We can see from Fig. 4-7(a) that the output of the PD rises from its initial DC bias point (517.5mV) when there is a RF signal input. The output reaches its steady state around 25ns. Fig. 4-7(b) is result of the harmonic balance simulation. The input power is swept from -30dBm to 10dBm. The simulation results show that the output difference of -25dBm and -24dBm input is around 3mV which is sufficient for the comparator.

5 10 15 20 25

RF input power (dBm to 50Ohm)

PD DC ouput voltage

(b)

Fig. 4-7 (a) Time response with different input levels (b) DC output voltage vs. input power

4.2.5 Digital step attenuator (DSA)

Fig. 4-8 (a) shows the configuration of the DSA. By switching between the two attenuation levels of the attenuation cell a -8~-15dB with -1dB/step can be achieved.

Fig. 4-8 (b) is the attenuation cell used. Here I called it a

“complementary

π

attenuator”. Matching closed to 50 Ohm while switching between

the two attenuation levels is a merit. Besides this, the signal at the output of the LNA is larger and causes linearity to be an issue. Resistive network, however, has high linearity that will be suitable here. Here, inverter is used to give us D1 and D1b. For larger attenuation levels, we can turn on D1 and turn off D1b to make the series resistance larger and shunt resistance smaller and vice versa for smaller attenuation levels.

Fig. 4-8 (a) Digital step attenuator (b) attenuation cell

In order to make the power gain equal to the voltage gain, the DSA is designed to make the input impedances closed to 50Ohm (or S11<-20dB). Besides, a very linear 1dB-attenuation is necessary simultaneously at each step. Besides the lowest attenuation level -7dB of the DSA itself, an additional 1dB loss is contributed from

SW2 and the AC couple capacitor between the DSA output and the gate of PD’s M1 to make the lowest attenuation of this path -8dB.

Fig. 4-9 are some simulation results of Fig. 4-8 (a) using a -10dBm which has 50Ohm source resistance 5GHz input test tone. Fig. 4-9(a) shows the power level at Vg2 referring to 50Ohm. If we view the DSA as a DAC, the bit difference or DNL can be simply define as:

( ) ( 1)

( ) (LSB)

output power i output power i Bit difference i

− −

(4.11) where LSB equals to 1dB. Fig. 4-9(b) is a plot of bit difference after calculations. Fig.

4-9(c) plots the variations of input impedance.

(a)

(b)

(c)

Fig. 4-9 (a) Output power of the DSA with -10dBm test tone (b) Bit difference (c) Input impedance check

4.2.6 Design guidelines of the DSA

One may wonder how the DSA is designed so perfectly as the Fig. 4-9. No doubt a beginner may spend hours and hours, days and days on trimming owing to the non-idealities of the component values, such as parasitic effects and turn on/off resistance of the MOS. Here, we came up to some design guidelines not great as a theory but just to let us never become an “ADS tuning monkey!” The following steps are the designer’s “know how.” Belief it or not, rapid and efficient design can be made by following them.

Step I: One can first calculate the ideal values of Rs, Rsb, Rp, and Rpb in Fig.

4-8(b). Construct an ideal attenuation cell with the calculated resistor values, an ideal switch, and an inverter. Double check the attenuation levels (or S21) of the two modes and the input impedance Zin. Make sure that one designs one attenuation cell at a time. Please don’t haste to combine the attenuation cells altogether at the very beginning or you might in big trouble.

Step II: Change the ideal series switch to Ms and sweep the dimension of it. Take a glance at both S21 and Zin. One can notice that larger dimensions of Ms result in a more ideal S21. However, this causes the real part of Zin to shrink more than smaller dimensions. One may stupidly want to make the Rsb smaller, since it is series with an on resistance of Ms. However, the results are even worse. The smaller the Rsb, the more Zin shrinks

Step III: Sweep the size of Rp instead. One may notice that by making the size few tens Ohms larger than the calculated value, the results will be closer to the ideal value. Besides, Zin doesn’t shrink anymore. We can conclude shortly that the series branch of an attenuation cell is the most sensitive part. Don’t ever try to change it.

Step IV: Change the ideal parallel switch to Mp. Larger dimension size results in a smaller on resistance and a bigger off capacitance that makes “000” the smallest Zin when combing the attenuation cells together. As Rs, Rsb, and Rp are fixed already from Steps I~III, Rpb is the only degree of freedom left.

Chance of fixing the attenuation cell closer to ideal is to make Mp smaller and Rpb bigger.

Step V: Since the estimated values is given from steps above, change the resistors to practical ones, such as HRI, RP-poly, etc. A little bit of fine tuning the component size afterwards is necessary since there are still some parasitic effects of the practical resistors.

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