Chapter 1 Introduction
1.2 Thesis Organization
Chapter 2 introduces the basic principles and the crucial considerations of RF ESD protection design as well as basics of RF LNA and RF PA. The issues of RF ESD protection design are investigated. Some practical RF ESD protection designs are exhibited.
Chapter 3 exhibits ESD protection designs for 60 GHz RF circuits. Two ESD protection designs with inductors, capacitors, and diodes are proposed. The architecture, corresponding design equations, and simulation results are presented. The measurement results of the RF performances and the ESD levels of both ESD protection designs, which are fabricated in a 65-nm CMOS process, are summarized. According to the experimental results, the two proposed ESD protection designs exhibit required ESD levels without serious RF performance degradation, and therefore is suitable for 60 GHz RF circuits.
Chapter 4 exhibits an ESD protection design for 2.4-GHz RF PA. A Zener-diode-triggered SCR, which is appropriate for PA ESD protection, is proposed. The architecture of the ESD protection design is presented in detail. In addition, a 2.4 GHz CMOS PA used to verify the ESD level of the proposed ZTSCR is also designed. Both unprotected PA and ESD-protected PA are fabricated in a 65-nm CMOS process. The experimental results of RF performances and ESD levels of the unprotected PA and the ESD-protected PA are
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summarized and compared. According to the results, the proposed ZTSCR indeed has enough ESD protection ability without degrading the RF performances of the 2.4 GHz CMOS PA.
Besides, a useful ESD protection design for PA with on-chip RF choke inductor at the output stage is also presented and verified in a 65-nm CMOS process.
Chapter 5 is the conclusions of this thesis and the future works on this topic.
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Chapter 2
Basics of RF and ESD Protection
2.1 General Considerations of LNA Design
2.1.1 S-Parameters and Noise Figures
To deal with a high-frequency network, conventional method of measuring voltage and current is no longer suitable. Direct measurement under high-frequency conditions usually involves the magnitude and phase of a traveling wave, so the concepts of equivalent voltage, equivalent current, and the related impedance and admittance become abstract. Scattering parameters (S-parameters) with the concepts of incident, reflected, and transmitted waves are more suitable and widely used to describe the characteristics and behaviors of high-frequency networks [9].
Fig. 2.1 shows a two-port network characterized by S-parameters. The S-parameters are defined in waves of each port, respectively. Each term in the S-parameters matrix is defined in (2.3).
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S11 is the reflection coefficient seen at port 1 when port 2 is terminated with a load of 50 ;
S22 is the reflection coefficient seen at port 2 when port 1 is terminated with a load of 50 .
S21 is the forward gain from port 1 to port 2; S12 is the reverse gain from port 2 to port 1.
In high-frequency measurement, S11 describes input matching condition, and S22 describes output matching condition. S21 describes the forward gain from port 1 to port 2, and S12 describes the reverse isolation condition.
Fig. 2.1. A two-port network described with S-parameters.
For receivers, noise is another important concern. Noise factor is a figure of merit to describe a noisy system [10]. Noise factor is defined as
i
where SNRi represents the signal-to-noise ratio measured at input, and SNRo represents the signal-to-noise ratio measured at output. It is a measure of SNR degradation when signal passes through the described system. A commonly used figure of merit named noise figure (NF) is
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10log ( )
NF F dB
(2.5) The physical meaning can be realized as
Total output noise power NF Output noise power due to source only
(2.6)
Form (2.6), if the described system adds no noise of its own, NF would be zero.
Considering a cascade multi-stage system shown in Fig. 2.2, each stage has gain (G) and noise factor (F). The noise factor can be characterized by Friis formula
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It is clear that noise of a multi-stage system is mainly contributed by the first stage. For this reason, LNA, which is the first stage of an RF receiver, needs much consideration on noise.
Fig. 2.2. A cascade multi-stage RF system described with gain and noise factor.
2.1.2 Stability
Stability, which can be extracted from S-parameters, is a crucial consideration in RFIC design. To an RF amplifier, it is important to operate stably without going into oscillation under any condition. For unconditionally stable, both input impedance and output impedance cannot be negative resistive. The sufficient and necessary conditions are
S 1
(2.8)
L 1
(2.9)
8 reflection coefficient; OUT is output reflection coefficient.
These equations can be further derived to
2 2 2 (2.12) and (2.14) represents the necessary and sufficient conditions for unconditional stability.
2.2 General Considerations of PA Design
2.2.1 Efficiency and Large Signal Characteristics
Since PA consumes large amounts of DC power and simultaneously amplifies and delivers RF power to a load, the problem of whether PA delivers and amplifies RF power efficiently or not is needed to be concerned. Some figures of merit can help evaluating the efficiency. There are three kinds of indicators which are used to evaluate efficiency:
Drain Efficiency:
9 input power. Commonly, PAE is a reasonable and usually used indication of PA performance about efficiency.
To design an RF power amplifier, large signal characteristics are undoubtedly important concern. Ideally, an RF amplifier is considered as a linear amplifier. The power gain remains constant and the relationship between output power and input power is linear. However, the large signal transfer characteristics are different. As input power increases larger and larger, the output power starts to gradually saturate. This makes the linear transfer relationship between input power and output power no longer hold. Under large signal operating conditions, the MOS devices used in PA cannot be considered as linear devices anymore, and the output power will be gradually compressed. Since the power transfer characteristic is no longer linear after the output power starts to be compressed, one indicator, 1-dB gain compression point, is commonly used to estimate the upper limitation of the linear operating region of PA.
At 1-dB gain compression point (P1dB), the power gain is 1 dB smaller than the constant power gain, as shown in Fig. 2.3. IP1dB is the input power at P1dB. The power transfer characteristic is shown in Fig. 2.4. In Fig. 2.4, OP1dB represents the output power at P1dB, and Psat represents saturated output power. OP1dB is often treated as the maximum linear output power of PA, so it is an important indicator of linearity of PA.
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Fig. 2.3. The plots of power gain versus input power.
Fig. 2.4. The plots of output power versus input power.
2.2.2 Load-Line Theory and Load-Pull Characterization
A general PA is shown in Fig. 2.5. RFC represents an RF choke inductor used to feed DC power to the drain of the output transistor. DC block is a capacitor used to block from losing to the output load (RL). Output matching network is used to transform the impedance of RL to an optimal output impedance seen from the drain of the output transistor. With optimal output impedance, PA can deliver the maximum output power.
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Fig. 2.5. Architecture of general RF power amplifier.
One evident difference between RF PA and linear RF amplifier such as LNA is the output matching design. Conjugate matching method, which is commonly used in RF amplifier, is no longer suitable for PA [11].
Fig. 2.6 (a) shows a simple current generator. The generator, for example, has a maximum output current of 1 A and an output resistance (RS) of 100 . According to the conjugate matching theory, the load resistance (RL) should be chosen as 100 . However, the voltage across the terminals of the generator would be 50 V. If the current generator is the output MOS transistor of a PA, the voltage would exceed the maximum output voltage of the output transistor, which is assumed to be 10 V here. For such physical restriction, another matching method named “load-line match” is selected to acquire maximum output power for PA. With this method, the optimal load resistor (RL,opt) is chosen as
max maximum output power with the RF voltage swing still being kept within specified limits.
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(a)
(b)
Fig. 2.6. (a) A simple current generator and (b) the comparison of its two output matching methods.
To obtain the optimal output impedance of PA, load-pull measurement is an accurate method which has been commonly used. A simple architecture of load-pull measurement is shown in Fig. 2.7. The device or amplifier under test (DUT) is set between an input tuner and an output tuner. The first step is to find the optimal output impedance which can be utilized to acquire the maximum output power. This forms the center point of the load-pull loci on Smith Chart. Next, the output impedance is adjusted repeatedly to get a constant output power which is lower than the maximum output power by 1 dB. A constant power contour will be presented on Smith Chart, too. This procedure is repeated many times and a set of constant output power contours are generated and shown on Smith Chart, as shown in Fig. 2.8. For PAE, this procedure needs to be done again, since the optimal output impedance for
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maximum output power is different from the optimal output impedance for maximum PAE.
Finally, two sets of contour are shown on Smith Chart, as shown in Fig. 2.9. The optimal output impedance for a well balance between output power and PAE can be chosen with the load-pull system.
Fig. 2.7. Typical Load-pull system.
Fig. 2.8. Load-pull contour – delivered power contour.
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Fig. 2.9. Load-pull contours – delivered power contour and PAE contour.
2.2.3 Classes of Conventional Linear PA
There are four types of linear PA which are distinguished primarily with bias conditions.
In class A type, the bias levels are chosen so that the output transistors can operate in the active region at all time, and it is clear that the transistors always dissipate power. The maximum drain efficiency of class A operation is 50 %. This is undoubtedly a theoretical number, since the variation of bias conditions, inevitable losses, and other non-ideal effects always exist. Class A PA provides good linearity but poor efficiency.
In class B type, the bias levels are chosen to shot off the output transistors half of every cycle. The product of the drain voltage and current of class B operation is not always positive, and the power dissipation would diminish in comparison with that of class A operation. The theoretical maximum drain efficiency is 78 %. Class B PA has worse linearity in exchange of better efficiency.
In class AB type, the bias levels are chosen so that the amplifier conducts between 50 % and 100 % cycle. Thus, class AB amplifier has better efficiency than class A amplifier, and better linearity than class B amplifier. Class AB operation can be considered as a compromise between class A and class B operation.
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In class C type, the bias levels are chosen to make the output transistor conduct less than half cycle. As the conduction angle decreases to zero, the efficiency can achieve toward 100
%, but the gain and output power decrease to zero. Though the efficiency of class C amplifier is pretty high, the linearity is lost.
The difference among different types of PA is the bias point. Fig. 2.10 shows different bias points and their corresponding types of PA on MOS I-V curves. Imax represents the maximum output current of a transistor, Vmax represents the maximum voltage drops across the drain and the source of the transistor, and Vknee represents the knee voltage of the transistor. The center point of the dashed line is the bias point of class A operation. The other bias points of class AB, class B, and class C are also shown, respectively.
Fig. 2.10. Comparison among different bias points and there corresponding types of PA.
2.3 Conventional ESD Protection Design
2.3.1 Architecture of Conventional Whole-Chip ESD Protection Design
Fig. 2.11 shows a whole-chip ESD protection design which can provide effective ESD protection for CMOS ICs [2]. The typical design consists of a pair of ESD protection devices inserted beside the I/O pad and a power-rail ESD clamp circuit placed between the VDD and
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VSS power lines. The pair of ESD protection devices is used to clamp ESD stress and provide ESD discharge paths among I/O pad and powerlines. The power-rail ESD clamp circuit is used to clamp the VDD-to-VSS ESD stress and provide an ESD discharge path between VDD
and VSS power lines.
Fig. 2.11. Architecture of whole-chip ESD protection design.
2.3.2 Power-Rail ESD Clamp Circuit and I/O ESD Clamp Device
A typical power-rail ESD clamp circuit, which is shown in Fig. 2.12, consists of an ESD-transient detection circuit and an NMOS (MESD) used as a VDD-to-VSS ESD clamp device. The ESD-transient detection circuit is expected to detect ESD stress and then turn on the ESD clamp device to provide an ESD discharge path right after ESD events occur, while turn off the ESD clamp device under normal power-on conditions.
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Fig. 2.12. Typical power-rail ESD clamp circuit.
A conventional ESD-transient detection circuit is an RC-detector. Since the pulse rise time of ESD events is on the order of nanosecond but that of the normal power-on events is on the order of millisecond. The RC time constant of the RC-detector should be designed to be on the order of microsecond, so the RC-detector is able to distinguish ESD events from normal power-on events.
MESD is used as a main ESD clamp device. It provides a low-impedance path for ESD current and clamps the ESD voltage between VDD and VSS power lines when it is triggered on by the ESD-transient detection circuit.
The pair of ESD protection devices inserted beside the I/O pad is expected to provide low-impedance ESD discharge paths among the I/O pad and power lines. A practical solution is a pair of diodes. Diode can endure a large amount of current with small device dimension.
Furthermore, diode can clamp the voltage of I/O at about 0.7V when it is forward biased to discharge ESD current. The low clamping voltage is beneficial to protecting MOS devices used in the internal circuits from being damaged by ESD stress.
In conclusion, a typical and conventional whole-chip ESD protection design is shown in Fig. 2.13. Since this ESD protection design provides proper ESD discharge paths under every
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ESD zapping mode, inclusive of positive-to-VDD mode (PD-mode), positive-to-VSS mode (PS-mode), negative-to-VDD mode (ND-mode), negative-to-VSS mode (NS-mode), VDD-to-VSS mode, and VSS-to-VDD mode, well ESD robustness is guaranteed. All the ESD discharge paths are shown in Fig. 2.14.
Fig. 2.13. Conventional whole-chip ESD protection design.
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(a)
(b)
(c)
Fig. 2.14. ESD-discharge paths under (a) PS-mode and NS-mode, (b) PD-mode and ND-mode, and (c) VDD-to-VSS mode and VSS-to-VDD mode.
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2.4 Issues of RF ESD Protection Design
2.4.1 Impacts of ESD Protection Design on RF Performance
The simple and effective ESD protection architecture in Fig. 2.13 would cause negative impacts while being applied to RF circuits. It is mainly because of the RF performance degradation caused by the parasitic capacitances of diodes.
To investigate the negative impacts caused by ESD protection diodes, some calculations with the concepts of S-parameters can help us. A conventional double-diode ESD protection design with a power-rail ESD clamp circuit for LNA is shown in Fig. 2.15.
Fig. 2.15. Conventional ESD protection design with double diodes and a power-rail ESD clamp circuit for LNA.
In the circuit in Fig. 2.15, the parasitic effects of ESD protection diodes, DP and DN, cause RF performance degradation. Some equations can be calculated to describe the impact [9]. The insertion loss of ESD protection diodes can be expressed as
21 where Z0 is the 50-Ω normalization impedance, and ZESD is the parasitic impedance of ESD protection diodes at the input node. Using the expression in dB, the insertion loss (ILESD) is equal to the absolute value of S21 parameter (S21, ESD).
The power gain of an RF LNA with ESD protection devices can be calculated from its schematic circuit diagram, as shown in Fig. 2.16. A simple expression of the input impedance (Zin, LNA) of LNA at resonance is [12] where T is the unity-gain frequency of the MOS transistor. The overall input impedance (Zin) of the LNA with ESD protection diodes is
Zin ZESD//Zin LNA, ZESD//Z0 (2.22) Therefore, the overall transconductance (Gm) of the LNA is
0 0 0 0 input and output were assumed to be conjugately matched. The transducer power gain (GT) is
where PL is the average power delivered to the load, Pavs is the average power available from the source, Ro is the output impedance of the cascoded NMOS transistors, and 0 is the operating frequency of input RF signal.
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Fig. 2.16. LNA with parasitic impedance of input pad and ESD protection diodes for calculating the power gain.
The calculations demonstrate the disadvantages to the transducer power gain of LNA. It is caused by the insertion loss of ESD protection diodes. If the parasitic impedance of ESD protection diodes (ZESD) can be increased to infinite, the transducer power gain of LNA in Fig.
2.16 would converge to that of an LNA without any ESD protection diode. Therefore, ESD protection device with high parasitic impedance, namely, low insertion loss, is needed for RF ESD protection.
2.4.2 Challenges of RF ESD Protection Design
Once the parasitic impedance of ESD protection diodes can be increased, the degradation of RF performance of LNA would be improved. Reducing the device dimensions of ESD protection diodes can increase (decrease) the parasitic impedance (capacitance). Hence, the RF performance degradation caused by ESD protection diodes would be reduced.
Unfortunately, such demand is on the opposite side of the demand of ESD robustness. The device dimensions of ESD protection diodes cannot be shrunk unlimitedly in consideration of
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ESD robustness. Moreover, the ZESD will further decrease as the operating frequency of RF circuits increases. Designing an effective ESD protection design for RF circuits operating in higher frequency with minimum RF performance degradation is a terrible dilemma.
2.4.3 Conventional RF ESD protection designs
To overcome these problems, many RF ESD protection designs have been developed.
One method is trying to cancel or isolate the parasitic capacitances from RF circuits, such as
“ESD cancellation” and “ESD isolation”; other method is trying to fundamentally reduce the parasitic capacitances of ESD protection devices in order to minimize the influence on RF performance [13] [14]. Some of these methods will be briefly introduced in this section.
“ESD isolation” is a method to protect RF circuits under ESD events, and “isolate” the parasitic capacitances of ESD protection devices from RF circuits under normal operating conditions. Well designed “ESD isolation” can provide enough ESD robustness without serious RF performance degradation. An example is using LC-tanks, as shown in Fig. 2.17 [6].
The impedance of LC-tank is infinite when LC-tank operates at its resonant frequency. For this reason, the pair of LC-tanks can be designed to resonate at the operating frequency of the internal RF circuit, and the RF input port will see infinite impedance through ESD clamp devices with the LC-tank, ideally. Therefore, the parasitic effects of ESD protection devices would not influence the RF circuit under normal operating conditions. The resonant frequency of LC-tanks is
The inductances and capacitances of LC-tanks can be chosen with (2.25).