Proposed ESD Protection Design for PA

To shorten ESD discharge paths and lower the clamping voltage, SCR is a proper choice.

SCR is a bilateral-conduction ESD protection device, so it can provide shorter ESD discharge paths. Besides, SCR has lower holding voltage than diode string. Another advantage of SCR is its low capacitance with small layout area. Thus, SCR with proper trigger mechanism would be a suitable choice.

Fig. 4.2 shows the proposed practical ESD protection design which is suitable for PA.

The ESD protection design consists of a power-rail ESD clamp circuit, an SCR with an ESD detection circuit which acts as a trigger circuit, and a pair of diodes, DN and DP.

The ESD detection circuit is used to detect ESD stress in order to send trigger message to the SCR and help turning it on. Since high trigger voltage is a drawback of typical SCR, extra trigger mechanism is needed to lower the trigger voltage. The ESD level would boost with lower trigger voltage. Considering the high voltage swing at the output node of PA, the ESD

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detection circuit should be high-voltage-tolerant to avoid being damaged under normal operating conditions.

Fig. 4.2. The proposed ESD protection design for PA.

An implementation of this ESD protection design is shown in Fig. 4.3. The ESD protection design utilizes a Zener diode (DZ) as a high-voltage-tolerant ESD detection circuit.

The breakdown voltage of D_Z should be low enough so D_Z can be quickly turned on to trigger the SCR under ESD stress conditions. On the other hand, the breakdown voltage of DZ should be high enough so that it would not be turned on to mistrigger the SCR under normal operating conditions. A diode Dp is placed between RF output pad and ESD bus in order to keep the ESD bus at high voltage level to avoid signal loss under normal operating conditions.

A diode DN is placed between RF output pad and VSS to provide an ESD discharge path extra from the SCR. The used power-rail ESD clamp circuit is the same as that used in section 3.2.

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Fig. 4.3. The proposed ESD protection design with a Zener diode as the trigger circuit of the SCR.

Fig. 4.4 (a) shows the proposed ESD protection device which implements this architecture, and Fig. 4.4 (b) shows its equivalent circuit. The P-ESD is a diffusion area which has higher doping concentration than P-sub but lower doping concentration than P+. The junction N+/P-ESD acts as a Zener diode embedded in the SCR and has lower breakdown voltage compared with P-well/N-well junction. D_P consists of P+/N-Well junction. D_N, which consists of P-well/N+ junction, is combined with the SCR for the consideration of layout area.

The Zener-diode-triggered SCR (ZTSCR) is an ESD protection device designed for RF PA.

Assume that positive ESD stress is applied to the node which will be added to the RF output pad. At the beginning, the voltage applied to the anode is less than the breakdown voltages of DZ as well as the N-well/P-well junction on the SCR path, so the ZTSCR acts like an open circuit. When the voltage applied to the anode is greater than the breakdown voltage of DZ, the trigger current starts to flow from DZ through P-well to P+ diffusion connected to V_SS. Once the voltage drops across the P-well resistor (R_P-well) is large enough, the parasitic NPN transistor will be turned on. The parasitic NPN transistor starts to inject electron current to bias the PNP transistor, and then the positive-feedback regenerative mechanism helps the

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SCR be successfully triggered into its latching state.

The trigger voltage of the ZTSCR would be lower than the typical SCR described in chapter 2. Since the breakdown voltage of DZ is lower than that of the N-well/P-well junction, the trigger current would more rapidly flow through R_P-well to turn on the parasitic NPN transistor.

Next assume that negative ESD stress is applied to the node which will be added to the RF output pad. This negative voltage drops across DN. As long as DN diode is forward biased, the ESD current can be discharged and the negative voltage will be clamped at the low cut-in voltage of DN.

(a)

(b)

Fig. 4.4. The (a) cross-section view and (b) the equivalent circuit of the ZTSCR.

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Figs. 4.5 to 4.9 show the ESD discharge paths of ZTSCR under ESD stress conditions.

For PS-mode, the ESD current first goes through D_P and then turned on the Zener diode to trigger the SCR. After the SCR is turned on, the ESD current can be discharged through the SCR path. For NS-mode, the ESD current is discharged through D_N. For PD-mode, the ESD current is discharged through the SCR path and the power-rail ESD clamp circuit. For ND-mode, the ESD current is first shunted from V_DD to V_SS through the power-rail ESD clamp circuit and then discharged through DN. For VDD-to-VSS and VSS-to-VDD mode, the power-rail ESD clamp circuit provides ESD discharge paths.

Fig. 4.5. ESD discharge path of the ZTSCR under PS-mode.

Fig. 4.6. ESD discharge path of the ZTSCR under NS-mode.

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Fig. 4.7. ESD discharge path of the ZTSCR under PD-mode.

(d)

Fig. 4.8. ESD discharge path of the ZTSCR under ND-mode.

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Fig. 4.9. ESD discharge path of the ZTSCR under VDD-to-VSS mode and VSS-to-VDD mode.