PA ESD Protection Design Consists of RF Choke Inductor and

Chapter 4 ESD Protection Design for 2.4 GHz CMOS RF PA

4.7 PA ESD Protection Design Consists of RF Choke Inductor and

The above sections present ESD protection design for PA with an off-chip RF choke inductor at the output stage and PA with all RF choke inductors off-chip. In some other applications, the RF choke inductor at the output stage of PA may be on-chip. For this kind of applications, a probable ESD protection design is shown in Fig. 4.47.

Fig. 4.47. ESD protection strategy for PA with the RF choke inductor LESD and a power-rail ESD clamp circuit.

Fig. 4.47 shows a simple structure of a PA with an on-chip inductor at the output stage and a power-rail ESD clamp circuit between VDD and VSS power lines. The Moutput represents the transistor at the output stage of the PA. L_ESD is an RF choke inductor used to feed DC power to the PA circuit, which exhibits very low impedance at low frequency, and therefore can also be treated as a low-impedance path to ESD current under ESD events. Since PA is used to deliver large power, the RF choke inductor at the output stage needs to be designed with large metal width so as to sustain large current density. This characteristic is also

beneficial to treating the RF choke inductor as an ESD discharge path. In addition, a power-rail ESD clamp circuit is inserted between V_DD and V_SS power lines to provide ESD paths.

Fig. 4.48 and Fig. 4.49 show ESD discharge paths under every discharge mode. For PS-mode, the ESD current first goes through LESD and then be discharged through the power-rail ESD clamp circuit. For NS mode, the ESD current is discharged through the power-rail ESD clamp circuit and then goes through LESD. For PD-mode, the ESD current is discharged from the output pad to V_DD through L_ESD. For ND-mode, the discharge path is in an opposite direction. The ESD protection design merely consists of an on-chip RF choke inductor at the output stage of PA and a power-rail ESD clamp circuit, and contributes no parasitic capacitances to the RF output. Without extra ESD protection devices, the design complexity of RF circuit is greatly reduced.

Fig. 4.48. ESD discharge paths under PS-mode and NS-mode ESD stress.

Fig. 4.49. ESD discharge paths under PD-mode and ND-mode ESD stress.

To implement this ESD protection design, a 2.4 GHz CMOS PA circuit which is shown in Fig. 4.50 has been designed as an ESD-protected PA. The output matching network was also removed from the test circuit for the same reason mentioned above. The used power-rail ESD clamp circuit is the same as that used in chapter 3.

Fig. 4.50. Circuit diagram of the ESD-protected PA circuit.

This ESD protection design has been designed and fabricated in a 65-nm CMOS process.

Fig. 4.51 shows the die photo of the ESD-protected PA. The PS-mode, PD-mode, NS-mode, and ND-mode 4-kV ESD stresses were applied to the output pad of the ESD-protected PA. To investigate the ESD robustness, the S-parameters of ESD-protected PA before and after ESD zapping were measured with the vector network analyzer. The measured S₂₁ parameters of the ESD-protected PA before and after 4-kV HBM ESD zapping of every mode mentioned above are shown in Fig. 4.52. According to Fig. 4.52, the S₂₁ parameter still maintains well.

Fig. 4.51. Die photo of the ESD-protected PA.

Fig. 4.52. Measured S21 parameters of the ESD-protected PA before and after HBM ESD stress of 4 kV.

The ESD protection strategy for PA with on-chip choke inductor at the output stage has been successfully verified in a 65-nm CMOS process. According to the measurement results, the S21 parameter of the ESD-protected PA after 4-kV HBM ESD zapping still maintains well.

This ESD protection strategy merely utilizes an RF choke inductor of the PA circuits and a power-rail ESD clamp circuit, but can provide at least 4-kV HBM ESD robustness and decrease the complexity of RF circuits design.

Chapter 5 Conclusions and Future Works

5.1 Conclusions

In this thesis, the issues of RF ESD protection design are presented. The parasitic effects of ESD protection devices may cause signal loss, change input matching conditions, and induce other undesired RF performance degradation. Designing RF ESD protection devices or circuits with good ESD level and less influence on RF performance is quite a challenge. Two RF ESD protection design are proposed to advance this goal.

One is for 60 GHz RF circuits. Since the circuit operating frequency of 60 GHz RF applications is quite high, the parasitic capacitance of ESD protection design is greatly limited.

The ESD protection design for 60 GHz RF circuits has been proposed, fabricated, and examined in a 65-nm CMOS process. The proposed ESD protection design simply consists of a pair of diodes, a supplement capacitor, and a series inductor and capacitor. The pair of diodes acts as ESD clamp device. The series inductor and capacitor are used to tune out the parasitic capacitances of ESD protection diodes. In addition, the supplement capacitor is added to lower the layout area. The proposed ESD protection design has small layout area and required 2-kV HBM ESD robustness with 1.8dB insertion loss at 60 GHz. Therefore, the compact ESD protection design for 60 GHz RF circuits can provide enough ESD level with tiny influence on RF performance. The proposed compact ESD protection design can be used for 60 GHz RF ESD protection.

Another one is for RF CMOS PA. PA plays an important role in RF ICs, but the ESD protection designs for CMOS PA have not been widely investigated. The ESD protection design for RF CMOS PA, named ZTSCR, has also been proposed, fabricated, and examined

in a 65-nm CMOS process. The ZTSCR is a Zener-diode-triggered SCR. With the well designed trigger mechanism, the ZTSCR is suitable for CMOS PA since the characteristics of PA has been involved in the design phase. Besides, a 2.4 GHz CMOS PA is also designed to verify the ESD protection ability of the ZTSCR. Three experimental circuits, including unprotected PA and two ESD-protected PA are fabricated in a 65-nm CMOS process. One ESD-protected PA is design for PA circuits with off-chip RF choke inductor at the output stage. Another one is for PA circuits with every RF choke inductor off-chip. The experimental results show that the unprotected PA has terrible ESD level, while the two types of ESD-protected PA have enough HBM ESD level. Moreover, the measurement results before ESD stress also show that the ZTSCR would not influence the RF performances of PA under normal operating conditions. The experimental results reveal the truth that the ZTSCR indeed do its work. Therefore, the proposed ZTSCR for PA ESD protection can provide enough ESD level without serious PA performances degradation. Besides, an ESD protection design for PA with on-chip RF choke inductor at the output stage is also fabricated and verified in a 65-nm CMOS process. For such kind of PA applications, the simple ESD protection strategy consists of an on-chip RF choke inductor and a power-rail ESD clamp circuit can provide enough HBM ESD level without serious PA performance degradation.

5.2 Future Works

The proposed ZTSCR is for PA with output voltage swing higher than 2 × V_DD. However, it may not be suitable for class-E PA. Since the output voltage swing of a class-E PA would higher than 3.6 × V_DD, the trigger voltage of the proposed ZTSCR is too low to avoid being mistriggered. Unfortunately, boosting the trigger voltage of SCR will decrease its ESD level.

In order to apply the ZTSCR to class-E PA, the ZTSCR still needs some modification.

Reference

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173-183, Jan. 1999.

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Microwave Theory and Techniques, vol. 57, no. 2, pp. 298-305, Feb. 2009.

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115-118.

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Chun, C. Ito, and R. Dutton, “RF ESD protection strategies-Codesign vs. low-C protection,” Microelectron. Reliab., vol. 47, no. 7, pp. 1008-1015, Jul. 2007.

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Vita

姓名：蔡翔宇學歷：

台北市立建國高級中學 (91 年 9 月~94 年 6 月) 國立交通大學電子工程學系 (94 年 9 月~99 年 6 月) 國立交通大學電子研究所碩士班 (99 年 9 月~101 年 9 月)

研究所修習課程：

類比積體電路吳介琮教授

數位積體電路周世傑教授

積體電路之靜電放電防護設計特論柯明道教授

類比濾波器設計陳巍仁教授

半導體物理及元件(一) 汪大暉教授

射頻積體電路郭建男教授

數位通訊林大衛教授

奈米電子元件荊鳳德教授

永久地址：新北市板橋區國慶路 149 巷 10 號 3 樓 Email：kplus.ee94@nctu.edu.tw

Publication

(A) Referred Journal Paper:

[1] C.-Y. Lin, L.-W. Chu, Shiang-Yu Tsai, and M.-D. Ker, “Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology,” IEEE Trans. Device Mater. Reliab., vol. 12, no. 3, pp. 554-561, Sep. 2012.

[2] C.-Y. Lin, Shiang-Yu Tsai, L.-W. Chu, and M.-D. Ker, “Large-swing-tolerant ESD protection circuit for giga-Hz power amplifier in a 65-nm CMOS process,” submitted to IEEE Trans. Microwave Theory and Techniques.

Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, and T.-H. Chang, “Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology,” in Proc.

IEEE International Symposium on Circuits and Systems, 2012, pp. 2127-2130.

[3] L.-W. Chu, C.-Y. Lin, Shiang-Yu Tsai, M.-D. Ker, M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C.

Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, T.-H. Chang, and Y.-L. Wei, “Design of ESD protection cell for dual-band RF applications in a 65-nm CMOS process,” in Proc.

Electrical Overstress / Electrostatic Discharge Symposium, 2012, in press.

[4] Shiang-Yu Tsai, C.-Y. Lin, L.-W. Chu, and Ming-Dou Ker, “Design of ESD protection for RF CMOS power amplifier with inductor in matching network,” submitted to IEEE Asia Pacific Conference on Circuits and Systems, 2012.

(C) Local Conference Paper:

[1] 竹立煒、林群祐、蔡翔宇、柯明道、盧澤華、許村來、洪彬舫、宋明相、曾仁洲、

張子恒、蔡銘憲, “以改良式電感電容共振腔實現之60-GHz射頻靜電放電防護電路,”

in Proc. Taiwan ESD and Reliability Conference, 2011, pp. 50-53.

(D) Patent:

[1] L.-W. Chu, C.-Y. Lin, Shiang-Yu Tsai, M.-D. Ker, M.-H. Tsai, T.-L. Hsu, C.-P. Jou,

“ESD protection design for high-speed interfaces,” U.S. and R.O.C. patent pending.

在文檔中應用於射頻積體電路之靜電放電防護設計 (頁 97-0)