Chapter 2 Basics of RF and ESD Protection
2.4 Issues of RF ESD Protection Design
2.4.3 Conventional RF ESD protection designs
To overcome these problems, many RF ESD protection designs have been developed.
One method is trying to cancel or isolate the parasitic capacitances from RF circuits, such as
“ESD cancellation” and “ESD isolation”; other method is trying to fundamentally reduce the parasitic capacitances of ESD protection devices in order to minimize the influence on RF performance [13] [14]. Some of these methods will be briefly introduced in this section.
“ESD isolation” is a method to protect RF circuits under ESD events, and “isolate” the parasitic capacitances of ESD protection devices from RF circuits under normal operating conditions. Well designed “ESD isolation” can provide enough ESD robustness without serious RF performance degradation. An example is using LC-tanks, as shown in Fig. 2.17 [6].
The impedance of LC-tank is infinite when LC-tank operates at its resonant frequency. For this reason, the pair of LC-tanks can be designed to resonate at the operating frequency of the internal RF circuit, and the RF input port will see infinite impedance through ESD clamp devices with the LC-tank, ideally. Therefore, the parasitic effects of ESD protection devices would not influence the RF circuit under normal operating conditions. The resonant frequency of LC-tanks is
The inductances and capacitances of LC-tanks can be chosen with (2.25).
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Fig. 2.17. ESD protection design with LC-tanks for RF circuits.
Another method is using series inductor and diode as ESD protection device, as shown in Fig. 2.18 [5]. The diode can be considered as a capacitor because of its parasitic effect. The impedance of the series inductor and diode is extremely small when the two devices operate at their resonant frequency, but extremely high when the two devices operate at frequencies above the resonant frequency. The resonant frequency of the series inductor and capacitor is the same as (2.9). Choose the resonant frequency of the series inductor and diode far away from the operating frequency of the RF circuit, and therefore the RF input port can see infinite impedance through the series inductor and diode under normal operating conditions. Thus, the parasitic effects of ESD protection devices would not influence the RF circuit. Of course, the diode serves the same function as an ESD clamp device does.
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Fig. 2.18. ESD protection design with series diodes and inductors for RF circuits.
“ESD cancellation” is a method to turn ESD protection devices into a part of RF circuit so as to “cancel” the parasitic capacitances introduced by ESD protection devices.
A commonly used method is considering ESD protection devices as parts of matching network [15]. If an ESD protection device is simply added in front of an RF circuit, the parasitic capacitance of the ESD protection device might change the input matching condition.
Merging the ESD protection device into the input matching network can minimize the influence. Fig. 2.19 shows this method. CP,ESD is the parasitic capacitance of an ESD protection device which changes the input matching condition. By adding extra capacitor CC
and inductor LG, the input impedance of the internal RF circuit can be changed from Zi1 to Zi2 of 50Ω. Hiding ESD protection devices in input matching network can cancel the RF performance degradation caused by the parasitic capacitance of ESD protection devices.
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Fig. 2.19. Input matching co-design of RF circuits with ESD protection devices.
In addition, this method can be extended to broadband RF applications [16], as shown in Fig. 2.20. The ESD protection devices, which are diodes here, are allocated with decreasing size from the I/O pad to the internal RF circuit. The ESD protection devices are divided into several small devices rather than one large device for broad-band RF performance. For ESD robustness, dividing the ESD protection devices into decreasing size is better than dividing them into equal size, since a larger ESD protection device inserted right beside the I/O pad is beneficial to providing a high-current-tolerant ESD discharge path under ESD events. Z0
represents the impedance of transmission lines, coplanar waveguides, or inductors which are used to do input matching. This architecture successfully combines ESD protection devices with input matching network, and it can provide enough ESD robustness without serious RF performance degradation.
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Fig. 2.20. ESD protection devices with decreasing size for broad-band RF circuits.
The methods mentioned above are a little complex to RF circuit designers since ESD protection circuits have to be co-designed with RF circuits. Considering ESD protection designs throughout RF design phase needs more effort. Therefore, a more straightforward direction is to fundamentally decrease the parasitic capacitances of ESD protection devices.
RF designers can therefore easily add low-C ESD protection devices to RF circuits without complex co-design methodology. To meet these requirements, silicon-controlled rectifier (SCR) can serve. With well ESD robustness within a small layout area and lower parasitic capacitance, SCR is useful to RF ESD protection design [8].
Fig. 2.21 shows the cross-section view and the equivalent circuit of a typical SCR. The SCR structure consists of P-plus (P+) diffusion, N-well, P-well, and N-plus (N+) diffusion, as shown in Fig. 2.21 (a). This four-layer structure can be regarded as a two-terminal device consists of a lateral NPN and a vertical PNP bipolar transistor, as shown in Fig. 2.21 (b).
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(a)
(b)
Fig. 2.21. The (a) cross-section view and (b) equivalent circuit of a typical SCR.
The DC I–V characteristics of SCR under ESD stress is shown in Fig. 2.22. Assume that positive ESD stress is applied to the anode of SCR and its cathode is relatively grounded. At the beginning, the voltage applied to the anode is less than the breakdown voltage of the N-well/P-well junction, so SCR acts like an open circuit. When the voltage applied to the anode is greater than the breakdown voltage, avalanche breakdown mechanism starts to work.
Hole current flows through the P-well to the P+ diffusion connected to ground, and
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meanwhile electron current flows through the N-well to the N+ diffusion connected to the anode. Once the voltage drops across the P-well resistor (RP-well) (N-well resistor (RN-well)) is larger than 0.7 V, the parasitic NPN (PNP) transistor will be turned on. Furthermore, the parasitic NPN (PNP) transistor injects electron (hole) current to bias the PNP (NPN) transistor, and then the positive-feedback regenerative mechanism helps SCR to be successfully triggered into its latching state and have a low holding voltage (Vhold) ~1.5 V.
Next, assume that negative ESD stress is applied to the anode of SCR and its cathode is relatively grounded. This negative voltage drops across the parasitic diode, which consists of the P-well/N-well junction, in SCR. As long as the parasitic diode is forward biased, ESD current can be discharged and the negative voltage will be clamped at the low cut-in voltage of the parasitic diode.
SCR provides suitable ESD discharging ability under every ESD stress condition, as described above. It can provide high ESD protection level within a small layout area. A smaller layout area introduces less parasitic capacitance, and therefore is beneficial to RF ESD protection.
Fig. 2.22. I–V characteristics of SCR device under positive and negative voltage biases.
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Chapter 3
ESD Protection Design for 60 GHz RF Circuits
3.1 Challenges of ESD Protection Design for 60 GHz RF Circuits
To design an ESD protection design for 60 GHz RF Circuits, a crucial problem needs to be concerned. The impedance of an ESD protection device can be expressed as
1
The higher the operating frequency is, the lower the impedance of ESD protection device is.
Low impedance causes large signal loss, and therefore causes serious RF performance degradation. Since the operating frequency of 60 GHz RF circuits is pretty high, the parasitic capacitance of ESD protection device needs to be extremely suppressed. However, extremely suppressing the parasitic capacitances of ESD protection devices such as SCR to fit the requirement of 60 GHz RF circuits is difficult. Thus, low-C ESD protection device may not be a good option.
ESD isolation would be a proper method, since the limitation of the parasitic capacitance of ESD protection device is not that tough, and it would not increase the design complexity of RF circuits. Nevertheless, the drawback of the ESD isolation method shown in Fig. 2.17 is its high clamping voltage. The clamping voltage of the ESD protection design under ESD stress conditions is the sum of the clamping voltages of LC-tank and ESD protection diode. It is better to lower the clamping voltage so as to enhance its ESD protection ability.
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3.2 Architecture of The Proposed ESD Protection Designs
Fig. 3.1 shows the circuit of one proposed ESD protection design for 60 GHz RF circuits.
The ESD protection design A, which consists of a pair of ESD protection diodes (DP and DN), a series inductor and capacitor (LN and CN), and a supplement capacitor (CS), is placed beside the I/O pad. The diodes provide ESD discharge paths from the input pad to VDD / VSS. In addition, a power-rail ESD clamp circuit is placed between VDD and VSS power lines so as to provide a discharge path between VDD and VSS.
The inductor in series with the capacitor can block the dc leakage path from input pad to VSS under normal operating conditions. The equivalent inductance of the series inductor and capacitor (Leq) can be expressed as Leq can be used to eliminate the parasitic capacitance of ESD protection diodes (CDiodes) at the operating frequency of the RF circuit by careful design. The resonant frequency of the parallel Leq and CDiodes is designed to be equal to the operating frequency of the RF circuit. Under this condition, the RF input port will see a large impedance from the ESD protection circuit (ZESD), where the parasitic capacitance (CDiodes) has been eliminated, and the parasitic resistance (RDiodes) remains large.
The resonant frequency of parallel Leq and CDiodes can be calculated by
0
1
eq Diodes
L C
(3.3)
From Eq. (3.2) and (3.3), another equation is obtained as
2
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determined, (3.4) can be used to find the required inductance and capacitance. Besides, the resonant frequency of the series inductor and capacitor should be far away from the operating frequency, since the impedance would be extremely small at its resonant frequency. The
To investigate the ESD robustness of ESD protection designs with different sizes of ESD protection diodes, several splits with DN and DP in different sizes are studied. Since the CDiodes varies with the size of ESD protection diode, a supplement capacitor (CS) is added between RF input and VSS to keep the total capacitance of CDiodes and CS. Therefore, the sizes of LN The power-rail ESD clamp circuit consists of an RC-detector, a CMOS inverter, and an RC-inverter-triggered NMOS. The RC-detector is designed to distinguish ESD transients from normal operating conditions. The R1 (~10 kΩ) and C1 (~10 pF) with time constant of 0.1 μs ~ 1 μs can meet such requirement, since the rise time of turn-on events are on the order of millisecond whereas that of ESD events are on the order of nanosecond. The NMOS (MESD) with ~2000-μm width is used as an ESD clamp device.
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Fig. 3.1. Proposed ESD protection design A with supplement capacitor and power-rail ESD clamp circuit.
Another proposed ESD protection design is shown in Fig. 3.2. The ESD protection design B also consists of a pair of ESD protection diodes (DP and DN), but the series inductor and capacitor (LP and CP) are placed between RF input and VDD. The operation of design B is similar to design A, and the design parameters can be calculated with (3.2) by replacing the LN by LP.
Fig. 3.2. Proposed ESD protection design B and power-rail ESD clamp circuit.
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3.3 ESD Discharge Paths of the Proposed ESD Protection Designs
With this architecture, proper ESD discharge paths under every ESD zapping mode are guaranteed. For PS-mode, the ESD current first goes through DP, and then it is discharged through the power-rail ESD clamp circuit. For PD-mode, the ESD current is discharged through DP. For NS-mode, the ESD current is discharged through DN. For ND-mode, the ESD current is first shunted from VDD to VSS through the power-rail ESD clamp circuit and then discharged through DN. For VDD-to-VSS and VSS-to-VDD mode, the power-rail ESD clamp circuit can provide ESD discharge paths. All the ESD discharge paths are shown in Figs. 3.3 to 3.7. The proposed designs A and B have the same ESD discharge paths.
Fig. 3.3. ESD discharge path of the proposed design A under PS-mode.
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Fig. 3.4. ESD discharge path of the proposed design A under PD-mode.
Fig. 3.5. ESD discharge path of the proposed design A under NS-mode.
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Fig. 3.6. ESD discharge path of the proposed design A under ND-mode.
Fig. 3.7. ESD discharge path of the proposed design A under VDD-to-VSS and VSS-to-VDD
mode.
Since the ESD current is discharged through only one diode from I/O pad to power lines, the clamping voltage under ESD stress conditions is lower than that of the structure shown in Fig. 2.17. It is beneficial to its ESD protection ability.
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3.4 Simulation Results
The proposed designs are simulated by using ideal lumped devices. A 0.11-nH inductor and a 300-fF capacitor are used as the series inductor (LN) and capacitor (CN). The diodes DN and DP are simplified to an ideal capacitor model, CDiodes. The sum of CDiodes and CS, that is, CESD in (3.6), is chosen as an 80-fF capacitor. Since ideal devices are used, the proposed designs A and B have the same simulation results. The simulated S21 parameter (S21, ESD) of the proposed design is shown in Fig. 3.8. The S21 value at 60 GHz can be designed to be 0 dB, which means that insertion loss from ESD protection circuit is also 0 dB.
Fig. 3.8. Simulated S21 parameter of the proposed design.
3.5 Experimental Results
3.5.1 Test Circuits
Increasing device sizes of ESD protection diodes provides better ESD robustness but worse RF performance, and decreasing device sizes of ESD protection diodes makes opposite results. In order to find a well balance between ESD robustness and RF performance, both
38 40 fF, and 20 fF are added to the test circuits A1 (B1), A2 (B2), and A3 (B3), respectively. To facilitate the on-wafer RF measurement, these test circuits are arranged with G-S-G style in layout. Part of the layout top view of the test circuit A4 is shown in Fig. 3.9. In other splits, CS was added beside DN. Every test circuit has the same layout area, 130×100 m2, as A4 does, since almost the same components are used in every test circuit.
Table 3.1
Device Parameters of Proposed ESD Protection Designs
Test Circuit
Proposed Design A Proposed Design B
A1 A2 A3 A4 B1 B2 B3 B4
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Fig. 3.9. Layout top view of the test circuit A4.
3.5.2 Measured RF Performance
The two-port S-parameters of the test circuits from 0 to 67 GHz were measured by using the vector network analyzer. During the S-parameter measurement, the port 1 and port 2 were biased at 0.5 V, which is VDD/2 in the given 65-nm CMOS process. The dc bias of 1-V VDD was also supplied to the test circuits.In order to extract the intrinsic characteristics of the test circuits in high frequencies, the parasitic effects of the G-S-G pads had been removed by using the de-embedding technique [17]. The source and load resistances to the test circuits were kept at 50 Ω.
The measured S21 parameters of the test circuits are shown in Figs. 3.10 and 3.11. For the proposed design A, the test circuits A1, A2, A3, and A4 have about 1.3-dB, 1.4-dB, 1.6-dB, and 1.8-dB insertion loss, respectively, at 60-GHz. For the proposed design B, the test circuits B1, B2, B3, and B4 have about 1.4-dB, 1.6-dB, 2.0-dB, and 2.3-dB insertion loss, respectively, at 60 GHz. Since the diodes used in simulation are simplified to ideal equivalent capacitor models rather than real diode models, the measured signal loss were larger than the simulated signal loss. The insertion loss of the proposed design B seems a little bit larger than the proposed design A. This is perhaps because of the more complex metal routing in layout. The
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noise figures are also measured at 60 GHz. For design A, the test circuits A1, A2, A3, and A4 have 0.9-dB, 1.2-dB, 1.6-dB, and 2-dB noise figures, respectively. For design B, the test circuits B1, B2, B3, and B4 have 0.9-dB, 1.3-dB, 1.7-dB, and 2.2-dB noise figures, respectively.
(a)
(b)
Fig. 3.10. Measured S21 parameters of proposed design A within (a) 0~67 GHz and (b) 57~63 GHz.
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(a)
(b)
Fig. 3.11. Measured S21 parameters of proposed design B within (a) 0~67 GHz and (b) 57~63 GHz.
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3.5.3 Measured ESD Robustness
ESD robustness of every ESD test circuit is evaluated by ESD tester. For the HBM ESD robustness, each test circuit is zapped by ESD pulses under PS-mode, PD-mode, NS-mode, and ND-mode ESD stress conditions. The failure criterion is defined as the I-V characteristics seen at RF input shifting over 30% from its original curve. The PS-mode, PD-mode, NS-mode, and ND-mode HBM ESD robustness of all ESD test circuits are measured, as listed in Table 3.2. According to the test results, the HBM ESD robustness of the proposed designs can be obtained from the lowest level of the robustness of the four modes. For the proposed design A, the test circuits A1, A2, A3, and A4 have 0.25-kV, 1.25-kV, 1.75-kV, and 2-kV HBM ESD robustness, respectively. For the proposed design B, the test circuits B1, B2, B3, and B4 have 0.25-kV, 1.25-kV, 1.75-kV, and 2.25-kV HBM ESD robustness, respectively. The measurement results of RF performance are also summarized in Table 3.2, inclusive of the measured S11 parameters. The measured S11 parameters show that all test circuits exhibit good input matching (S11 < -15 dB) at 60 GHz.
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Table 3.2
Comparisons of Experimental Results Among ESD Protection Circuits in Silicon
Proposed Design A Proposed Design B [18]
A1 A2 A3 A4 B1 B2 B3 B4
The HBM ESD robustness and the measured S21 parameters at 60 GHz of the proposed ESD protection designs A and B are compared in Table 3.2. Among the splits of the proposed designs A and B, the test circuit A4 (B4) can achieve 2-kV HBM ESD robustness with 1.8-dB (2.3-dB) insertion loss. Since the signal loss of B4 is a little higher than that of A4, A4 is the suitable ESD protection design for 60 GHz RF circuits in these splits.
There is another reference ESD protection design, which is also applied on 60 GHz RF circuits and had been verified in a 65-nm CMOS process, is compared with the proposed designs in Table 3.2 [18]. The reference ESD protection design also consists of some simple
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passive devices - two diodes and two inductors. The drawback is its large layout area.
Compared with the reference design, the layout area of the proposed designs can be reduced from 110×220 m2 to 100×130 m2. Moreover, the test circuit A4 can provide the required 2-kV HBM ESD robustness with lower insertion loss. Therefore, the compact ESD protection circuit for 60 GHz RF circuits can be realized by using the test circuit A4. The proposed design can easily be used for 60 GHz RF circuits.
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Chapter 4
ESD Protection Design for 2.4 GHz CMOS RF PA
4.1 Traditional ESD Protection Design for PA
To design an ESD protection circuit or device which is suitable for PA, the characteristics of PA should be involved in the ESD protection design concept. Fig. 4.1 shows a traditional ESD protection design for PA [19]. The ESD protection design consists of a power-rail ESD clamp circuit, a diode connected between RF output pad and VSS, and a diode string between VDD and RF output pad. The voltage at the output of a PA would swing to more than twice of VDD under normal operating conditions. In order not to cause signal loss, stacking several diodes between VDD and RF output pad is needed. However, the clamping voltage of the diode string would be high when ESD current is discharged through the diode string, and it is disadvantageous to ESD protection. Moreover, the diode string and the power-rail ESD clamp circuit make up the longest ESD discharge path, which is also disadvantageous to ESD protection.
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Fig. 4.1. Traditional ESD protection design for PA and its longest ESD discharge path.
Fig. 4.1. Traditional ESD protection design for PA and its longest ESD discharge path.