Chapter 1 Introduction
1.2 Thesis Organization
This thesis is organized into six chapters.
Chapter 1 briefly introduces the motivation of the thesis.
Chapter 2 describes the concepts of analog-to-digital conversion and performance parameters used to characterize ADCs. Then, several ADC architectures are introduced and the evolution of the pipelined ADC is presented.
Chapter 3 concentrates on the characteristics of the pipelined ADC. The nonlinearity of components is also need to take into account. Finally, the technique of double sampling is introduced, and it will apply to our design in order to speed the throughput rate of the pipelined ADC.
Chapter 4 illustrates the design and implementation of the double-sampling pipelined ADC. Circuit designs and the behavior model of the key blocks will be introduced in detail. Among them are the operational amplifier, the common mode feedback, the comparator, the bootstrapped switch, the sample-and-hold amplifier (SHA), the 1.5-bit architecture, and the 2-bit flash converter. Then, the transistor level simulated results of each circuit are presented. Finally, the simulation of the whole
pipelined ADC and its layout and floor plan are presented.
Chapter 5 presents the testing environment, including the component circuits on the DUT (device under test) board and the instruments. Then, the double-sampling pipelined ADC described in Chapter 4 is fabricated in a standard TSMC 0.18µm CMOS Mixed-Signal process and the measured results of this chip are summarized.
Finally, Chapter 6 is the conclusions of this work. Some suggestions and improved recommendations are proposed for the future work.
Chapter 2
Fundamentals of Analog-to-Digital Converter
2.1 Introduction
An analog-to-digital converter quantizes an analog signal into digital code at discrete time points. The performance of A/D converters depends on static specifications and dynamic specifications. This chapter first introduces the concept of the analog-to-digital converters and presents the static and dynamic performance parameters for A/D converters. Second, some of the prominent ADC architectures are introduced and the characteristics of these ADCs are described. Third, the technique of double sampling is discussed and the behavior model of the pipelined A/D converter with the double sampling technique is established by simulink.
2.2 The Concept and Performance of A/D Converters
An analog to digital converter (ADC) is a device converting analog signals into digital codes to link the real world and the digital systems. Figure 2.1 shows a block diagram of a traditional A/D converter at Nyquist rate. A low pass filter called an anti-aliasing filter is necessary to avoid the aliasing of higher frequency signals back into the baseband of ADC. The low pass filter is followed by a sample-and-hold amplifier (SHA) that maintains the signal in discrete time. The conversion is accomplished by a quantizer that segments the reference into subranges. Typically,
there are 2N subranges, where N is the number of digital output codes. Finally, the digital encoder is allowed to encode the corresponding digital bits according to the reference of subranges.
Figure 2.1 block diagram of an ADC
The frequency response of the ADC is also illustrated in Figure 2.1. At first we define the bandwidth of the signal, fb, and the sampling frequency, fs. The spectrum of the input signal is aliased at the sampling frequency. If the bandwidth of the signal, fb, is above 1/2fs, the spectrum of the signal will overlap with that of its image. It will result in the unrecoverable area around the frequency 1/2fs. This concept is formalized in the Nyquist rate, which states that the sampling frequency must be at least twice the bandwidth of the signal in order for the signal to be recovered from the samples. The types of ADCs operate in the concept of the Nyquist rate are called Nyquist analog-to-digital converters. [01]
Figure 2.2 illustrates the ideal conversion characteristic of a 4-bit ADC. The transition voltage can be written as
2 ,
ref
tn N
V =V ⋅ n n∈
{
0,1, 2,..., 2N −1 ,}
(2.1)where N and Vref represent the bit numbers and the applied reference voltage respectively. The quantization step (VLSB) is the difference of two transition voltages and it can be written as
Figure 2.2 Ideal conversion characteristic of a 4-bit ADC
2.2.1 Static Specifications
The static error of an A/D converter is based on the input-output characteristics shown below. Static parameters are directly related with a comparison between the ideal and the expected conversion characteristics. These static characteristics that define the static performance of A/D converters are offset error, gain error, integral nonlinearity (INL), and differential nonlinearity (DNL). These errors will cause inaccuracy output digital codes converted by the ADC. As in most applications these errors really impact the performance of ADC, some of calibration techniques have
been proposed. We will discuss some calibration methods applying in the A/D converter later.
2.2.1.1 Offset Error
The offset error is the deviation between the ideal transition voltage and the actual transition voltage relatively to the quantization step, VLSB. For an ADC with offset error, the ideal characteristic line is shifted horizontally. Offset error is illustrated in Figure 2.3.
Figure 2.3 illustrates Offset Error.
2.2.1.2 Gain Error
The gain error can be defined as the ratio between the slopes of the actual and other the ideal straight lines defined using the two endpoints of both conversion characteristics. Gain error can be measured as the horizontal difference in LSBs between actual and ideal finite resolution characteristics at highest digital code. Gain
error is illustrated in Figure 2.4. [02]
Figure 2.4 Illustrates Gain Error
2.2.1.3 Differential Non-Linearity Error (DNL)
Differential non-linearity error is defined as the difference between two adjacent analog signal values compared to the step size of converter generated by transitions between adjacent pairs of digital code numbers over the whole range of the converter.
In other words, DNL is the value compared the actual step size with the ideal step size voltage (1
2
ref N
LSB=V ). To achieve a maximum DNL error of ± 0.5 LSB defined at the
resolution level of the ADC (N-bit) , the transition voltages should be within 0.5 to 1.5 LSB at N-bit level.
If the maximum DNL error is larger than -1 LSB at N-bit level, it is guaranteed that the ADC is monotonic, which means that the digital output always increases or is kept constant as the input increases. If DNL error is larger or equal to 1 LSB, it guarantees a non-monotonic transfer function with more missing codes.
DNL error is defined as follows:
2.2.1.4 Integral Non-Linearity Error (INL)
INL error is defined as the deviation of the output code of a converter from the straight line drawn through zero and full-scale excluding a possible zero offset. The integral non-linearity error (INL) should not deviate more than ±1/2 LSB of the straight line drawn. INL is also specified after the static gain error has been removed.
It is defined as follows:
( )
( ), ( ),Figure 2.5 displays examples of DNL and INL errors in 3-bit ADC . [02] [03]
Figure 2.5 DNL and INL errors in a 3-bit ADC
2.2.2 Dynamic Specifications
Dynamic performance parameters depend on the resolution, the sampling frequency and the input signal frequency of an A/D converter and include information about dynamic linearity, distortion, sampling time uncertainty, noise and settling time errors. The most commonly analysis are related to the spectrum of the output signal.
With the input of full-scale sine wave, the resulting spectral analysis is rich in information about the dynamic behavior of the ADC.
2.2.2.1 Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the signal power, corresponding to the maximum amplitude of the signal component, and the noise power present at the output of ADC. The SNR includes the quantization noise and other circuits noise excluding any harmonic component of the input signal.
Assuming that the quantization error of an ADC is evenly distributed, the rms value of the generated noise signal, VQ(rms) ,is given by
( )
12
LSB Q rms
V =V (2.5)
where VLSB is the quantization step, and N is the resolution of the ADC. Assuming Vin
is a sinusoidal waveform between 0 and Vref , and considering only the ac power of the signal, the SNR is given by
( )
2.2.2.2 Signal-to-Noise and Distortion Ratio (SNDR)
Signal-to-Noise and Distortion Ratio is defined as the ratio of the signal power to the total noise power including all spurs and harmonics of the ADC. SNDR is measured for a sinusoidal input and is normally represented as a function of the frequency of the input signal. [04]
2.2.2.3 Spurious Free Dynamic Range (SFDR)
The spurious free dynamic range is defined as the ratio between the maximum rms amplitude of the signal and the rms value of the largest distortion component in a specified frequency range. SFDR indicates the usable dynamic range of an ADC, beyond which a spectral analysis poses special detection and thresholding problems.
To get much more understanding between SNR, SNDR, and SFDR, we can realize the difference between these parameters by the power spectrum illustrated in Figure.
2.6, where S is the fundamental of the input tones, D is the harmonic distortion component, and N is the noise floor. The Spurious Free Dynamic Range (SFDR) is depicted in Figure 2.6. SNR and SNDR are defined as
SFDR D
S Power Spectrum
fi 2fi 3fi
f N
Figure 2.6 the power spectrum with the fundamental and noise[05]
2.2.2.4 Effective Number of Bits (ENOB)
For actual ADCs, a specification often used in place of the SNR or SNDR is ENOB, which is a global indication of ADC accuracy at a specific input frequency and sampling rate. ENOB can be defined as follows:
1.76 6.02 ENOB SNDR−
= bits. (2.8)
2.2.2.5 Dynamic Range (DR)
Dynamic range (DR) is the input power range for which the signal-to-noise ratio of the ADC is greater than 0 dB. The dynamic range of a converter is usually specified as the ratio of the rms value of the maximum amplitude input sinusoidal signal to the rms SNR measured when the same sinusoid is present at the output. The dynamic range can be obtained by measuring the SNR as a function of the input power.
2.2.2.6 Sampling-Time Uncertainty (Aperture jitter)
The aperture jitter comes from the fact that there is a random variation between the clock signal and the effective holding time. For a sinusoidal waveform, the sampling time uncertainty is less of a problem near the peak values. However, the sampling time uncertainty will cause severe errors at the zero crossing where the maximum rate of change occurs.
A ADC with a full-scale sinusoidal input is illustrated in Figure 2.7.
∆V
∆t
X(t) X(k)
Figure 2.7 the aperture jitter for full-scale sinusoidal input
For the continuous-time input X(t), the discrete-time output is generated through the ADC which is controlled by the clock fclk. Taking account of the aperture jitter ∆t, we can get
( ) ( s ) s 1
CLK
X k X kT t T
= + ∆ = f (2.9)
For a full-scale sinusoidal input with the frequency fin, we can find that ( ) 1 sin(2 ) 2
2
N
FS in FS
X t = A πf t A = LSB (2.10)
At the zero corssing, we find that the aperture error voltage ∆V must be less than 1
In consequence, we get the limit of the aperture jitter ∆t for the N bit ADC as follows, 1
2N in t π f
∆ < (2.12)
In the other way, the signal-to-noise ratio (SNR) is limited by the aperture jitter.
Let 1
The total signal power and noise power can be calculated to be
2 1 2 1 2 2 2 2
( ) 8 FS 2 FS in s n
X k = A + A π f × ∆ =t P + (2.14) P
By the equation (2.14), the signal-to-noise ratio of X(k) is
20log(2 )
From the equation (2.15), it can be seen that SNR is independent of signal amplitude and that it decrease as the signal frequency fin and the rms value jitter ∆trms increases.
[01][06]
2.3 ADC Architectures Overview
Architectures for realizing analog-to-digital converters can be divided into three categories shown in Table 2.1 --- low-to-medium speed, medium speed, and high speed. These different types of A/D converts are designed for several kinds of applications, such as video systems, communication systems, and audio system, etc.
In this section, we will discuss some of the prominent A/D converters. In many applications, it is necessary to have a smaller conversion time. Therefore, it has led to the development of high-speed ADCs that use parallel techniques to achieve short conversion times or increase the speed of the individual components in ADCs.
However, the high speed ADCs usually cannot be design for very high resolution, like 14-bit resolution or even more. The speed and resolution of A/D converter is a trade off and it is difficult to design ADCs satisfying both demands at the same time.
Generally, the oversampling architecture of the ADC is adopted for high resolution design. Table 2.1 Different A/D converter architectures [04]
2.3.1 Flash ADC
Flash ADCs are the very-high-speed converters. The input signal in a flash is fed to 2N-1 comparators in parallel, as shown in Figure 2.8. For a N-bit flash converter, It performs 2N-1 level quantization by dividing the full-scale reference voltage into 2N segments. The reference voltages of the comparators are generated by using a resistor ladder which is connected between the positive and the negative reference voltage:
+Vref and –Vref respectively. Each comparator is also connected to a different node of a resistor string. Any comparator connected to a resistor string node where the reference of each comparator is larger than the input signal will have a 1 output, while those connected to nodes with less reference voltages than the input voltage will have 0 outputs. The set of 2N-1 comparator outputs is often referred to as thermometer code and is converted to N-bit binary word with a logic circuit. The input signal of the flash ADC is directly connected to the inputs of the comparators, and all comparators compare the input signal with the reference voltages in the resistor string simultaneously. Thus the speed of the flash ADC is very fast and the speed is only limited by the speed of the comparators. Therefore the flash ADC is capable of high speed.
The flash ADCs are fast but they require a large number of comparators, which typically take up a large area and consume much power. Both area and power become isseues in the parallel ADC as the resolution increases. Therefore the flash ADC is not suitable for high resolution application; typical resolutions are seven bits or below.
Besides, the bubble error is a serious problem. The outputs of the comparators should be a thermometer code with a single transition. However, sometimes a lone 1
will occur within the strings of 0s due to comparator metastability, noise, cross talk, limited bandwidth, etc. To combat the bubble noise, one can widen the input of the 1-of-2N detector. For example, use three-input OR gate to detect the 011 transition in the thermometer input. [04]
+Vref
-Vref Vin
2N-1 comparators
N-bit digital output
1 of 2N
Thermometer
Figure 2.8 N-bit Flash ADC
2.3.2 Two-Step ADC (or Subranging ADC)
In high speed applications, it is difficult to realize high-resolution flash ADCs which have the exponential growth of size and power. In order to overcome these drawbacks, two-step ADC has been proposed. The two-step ADC is demonstrated by separating coarse and fine converters into two paths, as shown in Figure 2.9.
The two-step ADC consists of an S/H circuit, a coarse flash ADC, a DAC, and a fine ADC. The conversion takes two steps. First, the S/H circuit samples the input signal and the M-bit MSB are generated through the coarse flash ADC. These M-bits will correspond to output voltage of the DAC. Second, the output voltage is subtracted from the former analog input voltage. The residue voltage is determined by the fine flash ADC to get the N-bit LSB. Therefore, the M+N bits resolution is reached by combining M-bit MSB and N-bit LSB.
coarse
Compared with the flash ADC, the number of the comparators for the architecture of the two-step ADC is reduced from 2M+N-1 to 2M-1+2N-1. For example, to achieve 10-bit resolution, we can reduce the number of comparators from 1023 (in flash architecture) to 62 (in two-step architecture). The area and power consumption is also reduced greatly.
However, the two-step converter has a longer latency delay than the flash
converter but it can allow for higher resolutions than the flash converter because of reducing the number of comparators.
2.3.3 Pipelined ADC
In a pipeline A/D converter, the quantization is distributed along a pipelined signal chain resulting in an effective architecture for high-resolution high-speed ADCs. By the idea of the two-step architecture, it is spread to a multi-stage architecture to construct the pipelined ADC. It has features that improve the throughput rate and tolerance to comparator offsets. The block diagram of the pipelined ADC is shown in Figure 2.10. It consists of M low-resolution stages and each stage generates k bit output codes. Finally, the last pipelined stage is followed by a flash ADC providing p bits. [07]
Figure 2.10 m-bit/stage pipelined ADC
The input signal is first sampled by the front-end S/H circuit and then the output is delivered to Stage 1. For each stage, the input signal is the output of the previous
stage except for the last stage. Each stage comprises a low-resolution sub-analog-to digital converter (sub-ADC) and an arithmetic unit called the multiplying digital-to-analog converter (MDAC) that performs a sample-and-hold (S/H) operation, coarse D/A conversion, subtraction, and amplification. In operation, each stage performs an A/D conversion of k bits, converts the digital output back to analog and subtracts it from the sampled and held analog input. The resulting residue voltage is amplified by 2k.
The architecture of pipelined ADC is the good compromise between area and speed. However, the major limitation on the accuracy in pipelined ADC is the gain amplifier, especially in the first few stages, where accuracy requirements are most stringent. The bandwidth of the gain amplifiers will decide the total throughput rate of the pipelined ADC. And the gain of gain amplifiers influences the total resolution greatly. Therefore, the gain amplifier plays the most important role in the pipelined ADC.
2.3.4 Cyclic ADC
A cyclic ADC is based on a pipelined ADC, as shown in Figure 2.11. It has only one stage but uses the stage repeatedly in a cycle. A cyclic ADC consisted of a single pipeline stage with the output fed back to the input. The delay from the input sample to complete digital output is the same as the pipelined ADC. The cyclic ADC completes N bits by reusing the stage multiple times thus it uses very little chip area and dissipates very low power. However, the throughput rate of the cyclic ADC is much less than the pipelined ADC. For N bit resolution, the cyclic ADC samples the single input signal every (N*clock cycle), and thus the throughput rate of the cyclic
ADC is only 1/N times compared with the pipelined ADC. [08]
Figure 2.11 Cyclic ADC
2.3.5 Time-Interleaved ADC
Figure 2.12 shows the block diagram of an architecture in which four ADCs are used on parallel to achieve four times the sampling rate of a single converter. This method is often known as time-interleaved architecture . The sample-and-hold circuits consecutively sample and apply the input analog signal to their respective ADCs. The digital outputs of the channels are combined with a multiplexer to a single bit-stream.
[02] [06]
Figure 2.12 Four-channel time-interleaved ADC and its clock signals
Chapter 3
The System of Pipelined
Analog-to-Digital Converters and the Double-Sampling Technique
3.1 Introduction
In this chapter we will concentrate on the pipelined ADC. We will discuss the pipelined architecture in more detail. As we know, the pipelined ADC has large tolerance to the offset of comparators due to the use of the redundancy and digital
In this chapter we will concentrate on the pipelined ADC. We will discuss the pipelined architecture in more detail. As we know, the pipelined ADC has large tolerance to the offset of comparators due to the use of the redundancy and digital