Operational Amplifier

The double-sampling pipelined ADC is composed of the front-end SHA, 8 MDACs in stages, final 2-bit flash, and digital error correction logics. And operational amplifiers are applied in the SHA and MDACs of eight stages. All analog circuits are fully differential. The advantages of the fully-differential circuit are that it can reduce even-order harmonic distortion, substrate noise, and common-mode disturbances. It also improves the power supply rejection ratio (PSRR) and the common-mode rejection ratio (CMRR). One drawback in the fully-differential circuit is that it needs the common-mode feedback circuit and it will be illustrated in the following sections.

4.4.1 Operational Amplifier

The opamp is the most important element in the SHA and every stage of the pipelined ADC. However, many limitations such as finite gain, bandwidth, stability, and linearity have to be considered when designing the opamp. To speed the converting rate of the pipelined ADC, the frequency bandwidth of the op-amp need to be increased. To improve the resolutions of the pipelined ADC, we have to increase the dc gain of the op-amp. Therefore, the specifications of the opamp require high gain and wide bandwidth so as to reach the demands of the high resolution and high throughput rate. Through it is a tradeoff between the opamp gain and bandwidth.

A two-stage opamp may achieve higher DC gain than a single-stage amplifier.

However, the optimal design can be achieved by using single-stage amplifier topology, because it has higher bandwidth and smaller power consumption. Therefore, the

opamp is implemented as a fully differential folded cascade amplifier, a close relative of the telescopic with a slightly better output swing. It allows the DC level of the output signal to be the same as the DC level of the input signal.

The folded cascode op-amp is shown in Figure 4.18. For the requirement of higher resolution accuracy, it is necessary to use the op-amp open-loop gain enhancement technique to increase the dc gain of the op-amp. This method is called gain-boosting, and the theory will be illustrated as follows. [23] [24] [25]

Vinp Vinn

Figure 4.18 Fully-differential folded cascode op-amp with gain boosting

The dc gain of the fully-differential folded cascode op-amp without gain boosting can be written as

v m out

A =G ×R . (4.18)

R_out =⎡⎣

(

)

(

) (

)

The transconductance G is approximately equal to _m g_m2. Substituting equation (4.19) into equation (4.18), we obtain

With the application of gain boosting the output impedance of the folded-cascode opamp is further increased without adding more cascade devices. Assuming that the GBP and GBN have the feedback loops, and they are the gain boosting amplifiers of PMOS and NMOS respectively. We can derive the output impedance enhanced by gain boosting amplifiers as

(

)

(

) (

)

out GBN m mb o o GBP m mb o o o

R =⎡⎣A g +g r r ⎤ ⎡⎦ ⎣A g +g r r r ⎤⎦ (4.21)

And the dc gain can be rewritten as

( ) ( ) ( )

{ }

2 9 9 11 9 || 7 7 7 2|| 5

v m GBN m mb o o GBP m mb o o o

A =g ⎡⎣A g +g r r ⎤ ⎡⎦ ⎣A g +g r r r ⎤⎦ (4.22)

Because of the single-stage topology, the second pole is far away from the unity-gain frequency. Assuming the output capacitance and resistance are CL and Rout, the frequency response of the folded-cascode opamp is derived by

( ) 2

For the high frequency response, because of sRoutCL >> 1 we can get the transfer function as follows

( ) ^m2 L

A s g

= sC (4.24)

The unity-gain frequency is given by

( ) ^m2 1

Since the folded-cascode opamp is adopted in fully-differential, it is therefore necessary to add additional circuitry to determine the output common-mode voltage and to control it to be equal to some specified voltage, usually about halfway between the power-supply voltages. This circuitry, referred to as the common-mode feedback (CMFB) circuitry, takes an important role in the feedback loop of the opamp.

To avoid the signal swing limit, a switched-capacitor common-mode feedback (SC-CMFB) circuit is applied into the folded-cascode opamp. A switched-capacitor common-mode feedback (SC-CMFB) circuit offer very wide input dynamic range, high linearity, and inherent stability with no power consumption. [26]

ø2

Figure 4.19 Dual-phase switched-capacitor CMFB circuit

The main advantages of SC-CMFB are that they impose no limits on the maximum allowable differential input signals, have no additional parasitic poles in the CM loop, and are highly linear. However, SC-CMFB injects nonlinear clock-feedthrough noise into the op-amp output nodes and increases the load capacitance that needs to be driven by the op-amp. Hence, SC-CMFB is typically only used in switched-capacitor applications such as sample-and-hold amplifier and SC-filter. The dual-phase switched-capacitor common-mode feedback (SC-CMFB) circuit is shown in Figure 4.19.

In Figure 4.19 it duplicates the sampling capacitors Cs, and interchanges its driving switch clocks. This scheme continuously refreshes capacitor Cc during both clock phases, and assures the same loading and same CM feedback factor. Capacitors Cc generate the average of the output voltages, which is used to create control voltages for the opamp current sources. The dc voltage across Cc is determined by capacitors Cs, which are switched between bias voltages and between being in parallel with Cc. The bias voltages are designed to be equal to the difference between the desired common-mode voltage and the desired control voltage used for the opamp current sources.

Figure 4.20 Simulated AC results of the op-amp

Figure 4.20 shows the AC simulation results including the gain and phase margin of five process corners (TT, FF, FS, SF, SS), which are summarized in Table 4.1. The simulated performance of the fully-differential folded cascode op-amp is summarized in Table 4.2.

TT SS SF FS FF

Gain（dB） 82.38 83.24 79.65 83.33 78.87

Phase（deg） 65.25 67.75 65.13 66.57 64.32 Unity GB(MHz) 721.5 678.7 698.5 742.5 785.4

Table 4.1 Simultated performance of opamp in five process corners

Folded-Cascode Op-amp(TT process corner)

DC Gain 82.38dB

Phase Margin 65.25°

Unity Gain Bandwidth 721.5MHz

Load Capacitor 2pF

Common Mode Input Range 0.3V~1.4V

Output Swing 0.35V~1.45V

Rise 302V/µs Slew Rate

Fall 311V/µs

Settling Time 4.12ns

Power Dissipation 8.43mW

Process TSMC 0.18µm 1P6M Process Table 4.2 Summary of the simulation results of the op-amp