The Package and Pin Configuration

Figure 5.10 shows the die photomicrograph of the experimental double-sampling pipelined ADC. Figure 5.11 presents the pin configuration and lists the pin assignments of the experimental pipelined ADC.

Figure 5.10 Die photomicrograph of the pipelined ADC

Figure 5.11 (a) Pin configuration diagram and (b) Pin assignment 6 CLOCK In System clock input 7 NC - No connection 8 DGND In Digital ground 9 DVDD In Digital power supply 10 AGND In Analog ground 11 NC - No connection 12 AVDD In Analog power supply 13 REFP In Reference voltage＞Vcm 29 AGND In Analog ground 30 Vba4 In Bias voltage 31 Vba1 In Bias voltage 32 Vcm In Common mode voltage 33 Vinn In Input signal (180°) 34 Vinp In Input signal (0°) 35 AVDD In Analog power supply 36 NC - No connection

5.4 Experiment Results of Pipelined ADC

The pipelined ADC has fabricated in 0.18µm CMOS process. The chip was powered by the 1.8 V analog and digital circuits supply. A 1 MHz sine wave is applied to the ADC and operates at the 100 Msample/s and 150 Msample/s conversion rate, respectively. The output 10-bit streams of the DUT collected by the logic analyzer and the plot chart are shown in Figure 5.12 and 5.13.

(a) (b)

Figure 5.12 Measured results for 100 Msample/s conversion rate (a)Output bit streams (b) Plot chart

Figure 5.13 Measured results for 150 Msample/s conversion rate (a)Output bit streams (b) Plot chart

From the measured results shown in Figure 5.12 and 5.13, the signal to noise ratio is calculated by collecting 65536 samples of the input signal and performing a 65536 point fast Fourier transform shown in Figure 5.14. This result shows that SNDR are about 32.14 dB and 30.78 dB for 100 and 150 Msample/s conversion rate respectively.

(a) (b)

Figure 5.14 65536 points FFT at 1MHz input frequency for (a) 100 MHz sampling frequency (b) 150 MHz

These harmonic distortions are caused by the nonlinear of the op-amp and mismatch of the two sampling paths. The worst reason is that the DC gain of the op-amp at the highest output swing is no longer large enough to meet the required specification. Furthermore, the charge injection and common mode drift issues both are the possible reasons. In addition, when the sampling rate is large than 150 Msample/s, the plot chart of the ADC doesn’t show the similar sine-wave. Probably the input signal and the sampling rate are coupled each other, thus the input signal is influenced and clipped. Figure 5.15 shows the SNDR for different sampling rate.

Table 5.1 summaries the measured results of the pipelined ADC.

Figure 5.15 The SNDR against the sampling rate

Parameters Measured Results

Process TSMC 0.18µm CMOS

Mixed-Signal

Supply Voltage 1.8 V

Input Range ±0.6V Fully differential Operation Frequency 150 MHz

SNDR for a 1 MHz input 30.78 dB

ENOB 4.82bits

DNL/INL 5.43/18.62 LSB

Power Dissipation 103 mW

Chip Size 1.380mm×1.134mm

Table 5.1 Summary of measured results of the pipelined ADC

Chapter 6

Conclusions

6.1 Conclusion

In thesis, a double-sampling pipelined ADC has been designed, laid-out, fabricated, and tested. With the technique of double-sampling, the specifications of the operational amplifier can be relaxed and the conversion rate of the pipelined ADC is duplicated compared with the single-sampling ADC.

Although the technique of double-sampling can increase the conversion rate, some non-idealities also comes along in the double-sampling pipelined ADC. Besides the non-idealities in the single-sampling pipelined ADC, such as the charge injection error, offset error, and gain error, the mismatches between the two paths have to be considered. We have discussed these problems in chapter 3.

The chip was fabricated by TSMC 0.18um 1P6M CMOS process. The measured results are 32.14dB in the 100MHz conversion rate. The maximum conversion rate in the measurement is worse than the simulation, because the design of the opamp is not good enough and settling error increases. Therefore, the output residue of each stage can not be settled properly when increasing the sampling frequency. On the other hand, there are many extra parasitic capacitors that the post-layout extraction didn’t extract out, and the measuring skills are not good enough, and any other reasons like the instrument issue and the high frequency effects that need to discover and study.

6.2 Future Work

As the mismatches between the paths result in severe distortions in the spectrum, the performance of the measurement is not satisfied. Therefore, it is an important issue to reduce the gain mismatch, offset mismatch, and timming mismatch. If we continue to research on the same topic, we will try to add some calibration methods to correct the nonidealities in the double-sampling pipelined ADC. As time goes by, a wide variety of calibration techniques has been proposed. Digital or analog calibration methods may be applied to the design for the double-sampling pipelined ADC. Based on the architecture of double-sampling pipelined ADC, the time-interleaved ADC can be established by combining more channels of double-sampling pipelined ADC. As a result, the sampling rate can be increased much greatly.

On the other hand, low voltage low-power design is the other topic to study for the future work. With the reduced supply voltage, we have to do efforts to improve the performance of the opamp to reach the accuracy of the ADC. And in order to reduce the power consumption, scaling down the sampling capacitors stage by stage will be necessary.

Bibliography

[01] “Data Converters”, Analog and Mixed Signal Center, TAMU

[02] Joao Goes, Joao C. Vital, and Jose Franca, “SYSTEMATIC DESIGN FOR OPTIMISATION OF PIPELINED ADCs”, Kluwer Academic Publishers, Boston, 2001.

[03] “INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs)”, Maxim Integrated Products.

[04] D.A. Johns and K. Martin, “Analog Integrated Circuit Design”, John Wiley &

Sons, Inc., 1997.

[05] “Defining and Testing Dynamic Parameters in High-Speed ADCs＂, Maxim Integrated Products.

[06] P.E. Allen and D.R. Holberg, “CMOS Analog Circuit Design”, 2nd edition, Published by Oxford University Press, Inc., 2002.

[07] S.H. Lewis and P.R. Gray, “A Pipelined 5-Msamples/s 9-bit Analog-to-Digital Converter”, IEEE Journal of Solid State Circuits, Vol. SC-22, pp. 954-961, Dec.

1987.

[08] D.Y. Wang and H.P. Chou, “A Two-Stage Pipelined Cyclic ADC for X/Gamma Spectroscopy”, IEEE Nuclear Science Symposium Conference Record, Vol. 2, pp. 1238-1241, Oct. 2003.

[09] S.H. Lewis, H.C. Fetterman, G.F. Gross, Jr., R. Ramachandran, and T.R.

Viswanathan, “A 10-b 20-Msample/s Analog-to-Digital Converter”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 3, March 1992.

[10] Lewis, S.H.; Fetterman, H.S.; Gross, G.F., Jr.; Ramachandran, R.; Viswanathan, T.R.;“A PIPELINED 9-STAGE VIDEO-RATE ANALOG-TO-DIGITAL CONVERTER” Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991, , pp. 26.4/1 - 26.4/4, 12-15 May 1991.

[11] Jason Hsieh, “High Speed and High Resolution A/D Converter Design”, Chip Implementation Center.

[12] George Chien, “High-Speed, Low-Power, Low Voltage Pipelined Analog -to- Digital Converter”, B.S. (University of California, Los Angeles) 1993.

[13] Andrew Masami Abo, “Design for Reliability of Low-voltage, Switched - capacitor Circuits”, B.S. (California Institute of Technology) 1992.

[14] B.-S. Song, M. F. Tompsertt, K. R. Lakshmikumar, “A 12-b 1-Msamples/s Capacitor Error Averaging Pipelined A/D Converter,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1324–1333, Dec. 1988.

[15]Yu, P.C.; Hae-Seung Lee, “A 2.5-V, 12-b, 5-MSample/s Pipelined CMOS ADC”, IEEE J. Vol. 31, Issue 12, pp. 1854 – 1861, Dec. 1996.

[16] Tat Choi; Brodersen, R., “Considerations for high-frequency switched-capacitor ladder filters”, Circuits and Systems, IEEE Transactions, Vol. 27, Issue 6, pp.

545 - 552, Jun 1980.

[17] Bazarjani, S. Snelgrove, M., “A 40MHz IF Fourth-Order Double- Sampled SC Bandpass Σ∆ Modulator”, Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, Vol. 1, pp. 73-76, 9-12 Jun 1997.

[18] Mikko E. Waltari & Kari A.I. Halonen, ‘‘CIRCUIT TECHNIQUES FOR LOW -VOLTAGE AND HIIGH-SPEED A/D CONVERTERS’’, 2002 Kluwer Academic Publishers, Boston.

[19] Bazarjani, S.; Snelgrove, W.M., “A 160-MHz Fourth-Order Double -Sampled SC Bandpass Sigma-Delta Modulator”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions, Vol. 45, Issue 5, pp. 547 – 555, May 1998.

[20] Lauri Sumanen, ‘‘Pipeline Analog-to-Digital Converters for Wide-Band Wireless Communications’’, Helsinki University of Technology Electronic Circuit Design Laboratory Report 35, Espoo 2002.

[21] Shi Chunlei., Ismail Mohammed. “DATA CONVERTERS FOR WIRELESS STANDARDS”, Boston Kluwer Academic Publishers, 2002.

[22] 鄭光偉,＂一伏十位元 CMOS 導管式類比數位轉換器＂,國立台灣大學/電機 工程學研究所/90/碩士/90NTU00442109.

[23] Klaas Bult and Govert J.G.M. Deelen, “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain ” IEEE Journal of Solid State Circuits, Vol. 25, No.6, pp. 1379 – 1384,December 1990.

[24] Nakamura, K.; Carley, L.R.^; “An Enhanced Fully Differential Folded-Cascode Op Amp”IEEE Journal of Solid-State Circuits, Vol. 27, Issue 4, pp. 563 – 568, April 1992.

[25] Behzad Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw-Hill Companies, Inc., International Edition, 2001.

[26] Noman, A.; Dessouky, M.; Sharaf, K., ‘‘A Dual Phase SC CMFB Circuit for Double Sampling Modulators’’, Circuits and Systems, 2003. MWSCAS '03.

Proceedings of the 46th IEEE International Midwest Symposium, Vol. 1, pp.

287 – 290, 27-30 Dec. 2003.

[27] Waltari, M.; Halonen, K., “Bootstrapped switch without bulk effect in standard CMOS technology”, Electronics Letters, Vol. 38, Issue 12, , pp. 555 – 557 ,6 June 2002.

[28] Lee, T.-S.; Lu, C.-C.; “Design techniques for low-voltage high-speed Pseudo -differential CMOS track-and-hold circuit with low hold pedestal”, Electronics

Letters, Vol. 40, Issue 9, pp. 519 – 520, 29 April 2004.

[29] Li Yu; Snelgrove, M., “Mismatch cancellation for double-sampling sigma-delta modulators”, Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium, Vol. 1, pp. 356 – 359, 31 May-3 June 1998.

[30] Waltari, M.; Halonen, K., “Timing skew insensitive switching for double-sampled circuit”,Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium, Vol 2, pp. 61 – 64, 30 May-2 June 1999.

[31] L. Sumanen, M. Waltari, V. Hakkarainen, and K. Halonen, “CMOS dynamic comparators for pipeline A/D converters”, IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 157-160, May 2002.

[32] L. Sumanen, M. Waltari, and K. Halonen, “A MISMATCH INSENSITIVE CMOS DYNAMIC COMPARATOR FOR PIPELINE A/D CONVERTERS”, IEEE International Conference on Electronics, Circuits and Systems, Vol. 1, pp.

32-35, Dec. 2000.

[33] L. Sumanen, M. Waltari, V. Hakkarainen, and K. Halonen, “CMOS dynamic comparators for pipeline A/D converters”, IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 157-160, May 2002.

[34] Samiran Halder, Arindrajit Ghosh, Ravi sankar Prasad,Aniban hatterjeee ,Swapna Banerjee,, “A 160MPS 8-bit Pipeline Based ADC”,VLSI Design, 2005. 18th International Conference, pp.313 - 318, 3-7 Jan. 2005.

[35] Waltari, M.; Halonen, K.; “A 10-bit 220-MSample/s CMOS sample-and-hold circuit”Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE

International Symposium, Vol. 1, pp. 253 – 256, 31 May-3 June 1998.

[36] Sumanen, L.; Waltari, M.; Halonen, K.A.I.; “A 10-bit 200-MS/s CMOS Parallel Pipeline A/D Converter”, IEEE Journal ofSolid-State Circuits, Vol. 36, Issue 7, pp.1048 – 1055, July 2001.

[37] Manganaro, G.;, “An improved phase clock generator for interleaved and double-sampled switched-capacitor circuits”, Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference, Vol. 3, pp.1553 – 1556, 2-5 Sept. 2001.

[38] “LM317 1.2V TO 37V VOLTAGE REGULATOR” Data Sheet,勝特力電子.

[39]黃善君 “10 位元 10MHz 導管式類比數位轉換器數位較正方法之研製” 國立