Chapter 4 Design of Double-Sampling Pipelined Analog-to-Digital
4.4 The implementation of 10-Bit Double-Sampling Pipelined ADC
4.4.4 Sub-ADC
4.4.4.1 Comparators
In many ADC designs, dynamic comparators using low-powered, cross-coupled inverter latches have a drawback of intolerable offset voltages and mismatches due to process variations, but in the 1.5 bits-per-stage pipline, a ±Vref/4 of comparator offset can be corrected using the digital correction logics. Thus a dynamic latch may be used in the system of pipelined ADC.
In order to make a dynamic comparator against mismatch and process variations all transistors should be in saturation straight after the latching signal. The comparator, based on two cross coupled differential pairs and switchable current sources, has a small power and area dissipation and it is shown to be very insensitive to transistor mismatch. A fully-differential CMOS dynamic comparator for pipelined ADC with a low stage resolution is implemented in Figure 4.27. [31] [32] [33]
Figure 4.27 Schematic diagram of comparator circuit
The comparator consists of two cross coupled differential pairs M1~M4, the current source transistors M5 and M6, and latches M7~M12. The operation of the comparator is as follows:
When Vlatch=0V, transistors M5 and M6 are inactive and no current path between the supply voltages exists. Simultaneously the switch transistors M9 and M12 reset the outputs by shorting them to Vdd. The transistors M7 and M8 of the latch conduct and force the drains of all the input transistors M1~M4 to Vdd.
When the Vlatch=Vdd, the outputs are disconnected from the positive supply and the switching current sources M5 and M6 enter saturation and begin to conduct. The two cross-coupled differential pairs M1~M4 start to compare the threshold with the input voltage. When the transistors M7 and M8 are active and amplify the difference of the source voltage in the cross-coupled differential pair. The transistors M5 and M6 determine the bias currents of the two differential pairs M1 - M2 and M3 - M4, respectively. Therefore, the threshold voltage of the comparator is determined by the current division in the differential pairs and between the cross coupled branches.
The output of the comparator has only two conditions. One condition is M7 and M11 is active but M8 and M10 is inactive. The other is M8 and M10 is active but M7 and M11 is inactive. Thus the comparator is free of static power consumption. The determination of the switching point of the comparator can be modeled with the simplification of Figure 4.28 for the two cross coupled differential pairs. Using the symbols indicated in the figure and having W1=W2, W3=W4 the transistors M1-M4 follow the large signal current equations:
5 2
6 2
4 3 3
1
2 D
D D ref ref
I I βV I V
− = β − (4.28)
where βi =
( ) (
1/ 2 K W L' i/) ( )
= 1/ 2 µ0Cox(
W Li/)
, Vin=Vin+-Vin- and Vref=Vref+-Vref-. The comparator changes its stage when the currents Io1 and Io2 of the both output branches are equal. Assuming the relation of the source coupled pair bias currents to be ID5=d ID6 and by making the threshold point with parameter e so that Vin=e Vref, this results in a condition from (4.27) and (4.28):2 1 ' 4 2 1 2 3 ' 2 3 2
6 6
2 D W ref(W ) 2 D W ref(W )
de I K e V I K V
L − L = L − L (4.29)
From Eq(4.29) the threshold and transistor sizes of the comparators can be decided.
The right-side of the Figure 4.27 is a SR-latch, which is used to stretch the output of the comparator to the full period because of only half-period lasting result in the output of the comparator. Figure 4.29 shows the simulation result of the output signal when applying the sine-wave input into the comparator.
Figure 4.28 Simplified model of the differential pair comparator
(a) (b)
Figure 4.29 Simulated result of the comparator for a threshold of (a) Vref/4 (b) –Vref/4
4.4.4.2 1.5-Bit Sub-ADC (Flash Quantizer)
Figure 4.30 Schematic of the 1.5-bit Sub-ADC
The 1.5-bit Sub-ADC consists of two differential comparators and some simple logic as shown in Figure4.30. The threshold voltages of the comparator are in Vref/4 and –Vref/4. A comparator offset voltage up to ±Vref/4 can be tolerated through digital error correction technology. The sub-ADC compares the differential input signal with two decision levels and generates one of three different digital outputs 00,01 or 10. The MSB and LSB are the digital output codes of the 1.5-bit sub-ADC.
Because the double sampling technique is applied in the pipelined ADC, not only
opamp is shared in two paths of each stage, but the sub-ADC is also shared. Therefore, the Xa, Ya, Za and Xb, Yb, Zb, corresponding to clka and clkb respectively, are the controlled signals which will be applied to the MDAC, which is also implemented with double-sampling technique.
Table 4.3 summaries the digital output codes of MSB and LSB and the controlled signals of X, Y, and Z for different values of the differential input voltage. Figure 4.31 shows the simulated result of the 1.5-bit sub-ADC, where the ±Vref are set equal to
±600mV.
Table 4.3 Digital output codes and controlled signals of 1.5-bit sub-ADC
Figure 4.31 Simulated result of MSB, LSB, Xa, Ya, Za, Xb, Yb, Zb for an input signal of sine wave
4.4.5 1.5-Bit MDAC
The performance of pipelined ADC critically depends on the 1.5-bit multiplying-digital-to-analog converter (MDAC). Figure 4.32 shows the schematic of the double-sampling 1.5-bit MDAC configuration. As the configuration of the SHA, the MDAC is designed for two parallel sets of sampling capacitors and feedback capacitors to increase the throughput rate in each stage. The two parallel paths are controlled by opposite non-overlapping phase clocks øa andøa. The phase øa_d and øb_d
are delayed version of phase øa andøb. [34] [35] [36]
Figure 4.32 Schematic of the double-sampling 1.5-bit MDAC
During the first phase øa, one set of capacitors Cs1p, Cf1p, Cs1n and Cf1n sample the differential input voltage Vinp and Vinn .Concurrently the other set of capacitors Cf2p
and Cf2n are connected in feedback, and capacitors Cs2p and Cs2n are connected to a proper reference voltage, Vrefp or Vrefn, which is controlled by the controlled signals Xa, Ya, and Za generated from the sub-ADC. The amplifier performs the analog reconstruction of the digital code resulting from the sub-ADC, subtracts it from the analog sampled voltage, Vin, and multiplies the resulting residue by 2.
During the second phase øb, the roles of the capacitors are exchanged. Capacitors Cs2p, Cf2p, Cs2n and Cf2n are employed as sampling capacitors. And capacitors Cf2p
and Cf2n form the feedback loop of the opamp while the capacitors Cs2p and Cs2n are connected to the positive reference voltage (Vrefp), or to the negative reference voltage (Vrefn) depending on the state of controlled signals Xb, Yb, and Zb.
Assuming Cs=Cf=C and the a non-ideal op-amp with finite DC gain, the value of the amplified residue to be processed by the next stage of the pipeline is given approximately by
yielding for very large A
out 2 in ref ref
V ≅ ⋅V − ⋅X V + ⋅Y V (4.31)
where X, Y, and Z are the encoded digital outputs provided by the 1.5-bit sub-ADC.
Figure 4.33 shows the simulation output waveform of the MDAC circuits in the first stage .
Figure 4.33 Simulated result of the 1.5-bit MDAC
4.4.6 The 2-Bit Flash ADC
Figure 4.34 Schematic of the 2-bit Flash ADC
The final stage of 2-bit flash ADC is shown Figure 4.34. The simulated results are illustrated in Figure 4.35. The output digital codes are 00, 01, 10, 11 depending on the threshold voltages, Vrefp and Vrefn.
Figure 4.35 Simulated result of the 2-bit Flash ADC
4.4.7 Clock Generator
Figure 4.36 Two-phase clock generator for double-sampling pipelined ADC
The two-phase clock generator for the double-sampling pipelined ADC is
illustrated in Figure 4.36. The input clock ,clkin, is inserted off-chip in the frequency of 200MHz. Two non-overlapping phases, shown in Figure 4.37, are delivered for proper operation of switched capacitor circuits in the frequency of 100MHz respectively. The characteristic of this scheme is the adoption of the short pulse Cs of the width ∆ and frequency 200MHz, which changes from 0 to 1 on the rising edge of clkin, illustrated in Figure 4.38. The short pulse Cs cause a high-to-low transition at the output of the inv1, which has its output at logic level one. Therefore, the falling edges of the clka and clkb can be controlled uniformly by the short pulse Cs. [37]
Figure 4.37 Simulated results of the non-overlapping clocks
Figure 4.38 Timing diagram of the clock generator
As a result, uniform sampling clocks can be reached to minimize time-skew
problems in the double-sampling pipelined ADC. A possible disadvantage of this circuit will be that a short time makes the pmos of inv1 and M1, or, the pmos of inv2 and M2 simultaneously on. It will increase the power dissipation a little, but it can be negligible in the overall power consumption.
4.4.8 Registers and Digital Error Correction Logics
The registers are used to make the output codes from 9 stages synchronous and the final 10-bit codes are stored in registers after processing by digital error correction logics. Positive edge-triggered true single-phase clocked D-flips are adopted in the design of the registers, as shown in Figure 4.39. Only one clock phase is needed in the register and the complexity of the register arrays can be reduced.
Figure 4.39 Positive edge-triggered true single-phase clocked D-flip
The digital output codes in each stage must be calibrated by the digital correction logics. It recombined the nine 1.5-bit codes by overlapping adding operation.
Combining the register array and digital correction logics implement the backend design of the ADC shown in Figure 4.40.
Figure 4.40 Shift register arrays and digital error correction logics
4.4.9 Simulated Results of Pipelined ADC
The 10-bit, 200MS/s double-sampling pipelined A/D converter with the 1.8V supply voltage is implemented. With the ideal DAC, the 10-bit output digital codes are converter to analog signal. Figure 4.41 shows the simulated result of the pipelined ADC when applying the 1 MHz sine-wave to the inputs. The spectrum of the reconstructed 0.98 MHz sine wave is shown in Figure 4.42 and the SNDR is about 56.14 dB.
Figure 4.41 Simulated result of the pipelined ADC with the sine-wave input signal
Figure 4.42 The spectrum of the 0.98 MHz sine wave
Figure 4.43 shows the simulated results through the ideal DAC when applying the ramp signal to input.
Figure 4.43 Simulated result of the pipelined ADC with the ramp input signal
Then the results are analyzed for characterizing the linearity of the ADC. However, the linearity of the ADC could be realized by analyzing the parameters of the DNL and INL. The simulated results of the DNL and INL of the pipelined ADC are shown in Figure 4.44. The maximum DNL and INL are ±0.75 LSB and ±0.95 LSB.
Figure 4.44 Simulated results of DNL and INL
Table 4.4 summaries the simulated results of the pipelined ADC. Layout and floor plan of the experimental prototype chip are shown in Figure 4.45. This pipelined ADC was laid out on a 1.380×1.134 mm2 die that including digital circuits and the pad frame. In the layout, we use the mirror symmetry to enhance the rejection of common mode noises in the fully differential circuits. In this research, the analog circuit is
separated from the digital circuit and is powered from a separated power supply.
Parameters Simulated Results
Process TSMC 0.18µm CMOS
Mixed-Signal
Supply Voltage 1.8 V
Input Range ±0.6V Fully differential
Resolution 10 bits
Operation Frequency 200 MHz INL/DNL ±0.95 LSB /±0.75 LSB
ENOB(Fin=0.98MHz) 9.03 bits
SNDR (Fin=0.98MHz) 56.14 dB Power Dissipation 103.28 mW
Chip Size 1.380mm×1.134mm
Table 4.4 Summary of simulated results of the double-sampling pipelined ADC
(a) Layout
(b) Floor plan
Figure 4.45 (a) Layout and (b) floor plan of the pipelined ADC
Chapter 5
Test Setup and Experimental Results
5.1 Introduction
The double-sampling pipelined ADC has been implemented by TSMC 0.18um 1P6M CMOS Mixed-Signal process. In this chapter, the testing environment, the printed circuit board (PCB) circuits and required instrument for testing are introduction. Finally, the experimental results are summarized.
5.2 Test Setup
Figure 5.1 Testing setup
A schematic of the measurement setup used to evaluate the double-sampling pipelined ADC performance is presented in Figure 5.1. Figure 5.2 shows a photograph of the PC board used in the experimental evaluations. In Figure 5.1 it consists of the
analog power regulator, the digital power regulator, the function generator, the clock generator, the reference and bias voltage generator, and the logic analyzer.
Figure 5.2 The photograph of the experimental pipelined ADC DUT board
5.2.1 Power Supply Regulators
The power supply is divided into two main parts to support the analog voltage VDDA and digital VDDD to avoid noise coupling between analog and digital circuit.
Therefore, these two powers have their own regulator and the output voltage, and the analog ground and digital ground are isolated to each other.
The analog and digital power supplies are generated by the application of the LM317 adjustable regulators shown in Figure 5.3. The input voltage of the regulator circuit is connected to a 9V battery, and the output voltage is specified in 1.8V. The regulator circuit requires two resistors to define the output voltage. [38] The output
voltage of the Figure 5.3can be expressed as
1.25 1 2 2
1
out ADJ
V R I R
R
⎛ ⎞
= ⋅ +⎜⎝ ⎟⎠⋅ ⋅ , (5.1)
where IADJ is the DC current that flows out of the adjustment terminal ADJ of the regulator.
LM 317
Vin Vout
ADJ
Vin Vout
R1
R2 C1
C2
Figure 5.3 Power supply regulator
The outputs of the regulators are bypassed on the PCB with the filter tank. The bypassed filter network is combined by 10uF, 1uF, 0.1uF, and 0.01uF capacitors as shown in Figure 5.4. The capacitor arrangement in Figure 5.4 provides decoupling of both low frequency noise with large amplitude and high frequency noise with small amplitude.
Figure 5.4 Bypass filter at the output of the regulator
5.2.2 Input Termination Circuit
The applied input signal to the DUT is buffered and converted to balanced differential forms by the circuit shown in Figure 5.5. By using the configuration of an inverting opamp and a non-inverting opamp, the differential signals are generated and delivered to the AC coupled circuit. [22] [39] [40] [41]
Figure 5.5 Single to differential circuit
Figure 5.6 AC coupled circuit
The AC couple circuit is illustrated in Figure 5.6. The outputs of the AC coupled circuits are terminated on the DUT with one pole low pass filters as shown in Figure 5.6. With the AC coupled circuit, we can prevent the aliasing of high frequency noise components into the baseband and attenuate charge kickback from the sampling switches in the DUT into the input source.
5.2.3 Measured Instruments
The input signal to the DUT is provided by the signal generator, Agilent E4438C, shown in Figure 5.7. The clock signal is generated by a pulse/pattern generator Agilient 81130A, shown in Figure 5.8. The output bit streams of the DUT are fed to the logic analyzer, HP 16702B, shown in Figure 5.9. The 10-bit output data was primarily captured and stored in the logic analyzer. By transferring the digital data from the logic analyzer, the converter outputs were processed and analyzed using MATLAB in the personal computer.
Figure 5.7 Signal Generator Agilent E4438C
Figure 5.8 Pulse/pattern generator Agilient 81130A
Figure 5.9 Logic analyzer HP 16702B
5.3 The Package and Pin Configuration
Figure 5.10 shows the die photomicrograph of the experimental double-sampling pipelined ADC. Figure 5.11 presents the pin configuration and lists the pin assignments of the experimental pipelined ADC.
Figure 5.10 Die photomicrograph of the pipelined ADC
Figure 5.11 (a) Pin configuration diagram and (b) Pin assignment 6 CLOCK In System clock input 7 NC - No connection 8 DGND In Digital ground 9 DVDD In Digital power supply 10 AGND In Analog ground 11 NC - No connection 12 AVDD In Analog power supply 13 REFP In Reference voltage＞Vcm 29 AGND In Analog ground 30 Vba4 In Bias voltage 31 Vba1 In Bias voltage 32 Vcm In Common mode voltage 33 Vinn In Input signal (180°) 34 Vinp In Input signal (0°) 35 AVDD In Analog power supply 36 NC - No connection
5.4 Experiment Results of Pipelined ADC
The pipelined ADC has fabricated in 0.18µm CMOS process. The chip was powered by the 1.8 V analog and digital circuits supply. A 1 MHz sine wave is applied to the ADC and operates at the 100 Msample/s and 150 Msample/s conversion rate, respectively. The output 10-bit streams of the DUT collected by the logic analyzer and the plot chart are shown in Figure 5.12 and 5.13.
(a) (b)
Figure 5.12 Measured results for 100 Msample/s conversion rate (a)Output bit streams (b) Plot chart
Figure 5.13 Measured results for 150 Msample/s conversion rate (a)Output bit streams (b) Plot chart
From the measured results shown in Figure 5.12 and 5.13, the signal to noise ratio is calculated by collecting 65536 samples of the input signal and performing a 65536 point fast Fourier transform shown in Figure 5.14. This result shows that SNDR are about 32.14 dB and 30.78 dB for 100 and 150 Msample/s conversion rate respectively.
(a) (b)
Figure 5.14 65536 points FFT at 1MHz input frequency for (a) 100 MHz sampling frequency (b) 150 MHz
These harmonic distortions are caused by the nonlinear of the op-amp and mismatch of the two sampling paths. The worst reason is that the DC gain of the op-amp at the highest output swing is no longer large enough to meet the required specification. Furthermore, the charge injection and common mode drift issues both are the possible reasons. In addition, when the sampling rate is large than 150 Msample/s, the plot chart of the ADC doesn’t show the similar sine-wave. Probably the input signal and the sampling rate are coupled each other, thus the input signal is influenced and clipped. Figure 5.15 shows the SNDR for different sampling rate.
Table 5.1 summaries the measured results of the pipelined ADC.
Figure 5.15 The SNDR against the sampling rate
Parameters Measured Results
Process TSMC 0.18µm CMOS
Mixed-Signal
Supply Voltage 1.8 V
Input Range ±0.6V Fully differential Operation Frequency 150 MHz
SNDR for a 1 MHz input 30.78 dB
ENOB 4.82bits
DNL/INL 5.43/18.62 LSB
Power Dissipation 103 mW
Chip Size 1.380mm×1.134mm
Table 5.1 Summary of measured results of the pipelined ADC
Chapter 6
Conclusions
6.1 Conclusion
In thesis, a double-sampling pipelined ADC has been designed, laid-out, fabricated, and tested. With the technique of double-sampling, the specifications of the operational amplifier can be relaxed and the conversion rate of the pipelined ADC is duplicated compared with the single-sampling ADC.
Although the technique of double-sampling can increase the conversion rate, some non-idealities also comes along in the double-sampling pipelined ADC. Besides the non-idealities in the single-sampling pipelined ADC, such as the charge injection error, offset error, and gain error, the mismatches between the two paths have to be considered. We have discussed these problems in chapter 3.
The chip was fabricated by TSMC 0.18um 1P6M CMOS process. The measured results are 32.14dB in the 100MHz conversion rate. The maximum conversion rate in the measurement is worse than the simulation, because the design of the opamp is not good enough and settling error increases. Therefore, the output residue of each stage can not be settled properly when increasing the sampling frequency. On the other hand, there are many extra parasitic capacitors that the post-layout extraction didn’t extract out, and the measuring skills are not good enough, and any other reasons like the instrument issue and the high frequency effects that need to discover and study.
6.2 Future Work
As the mismatches between the paths result in severe distortions in the spectrum, the performance of the measurement is not satisfied. Therefore, it is an important issue to reduce the gain mismatch, offset mismatch, and timming mismatch. If we continue to research on the same topic, we will try to add some calibration methods to correct the nonidealities in the double-sampling pipelined ADC. As time goes by, a wide variety of calibration techniques has been proposed. Digital or analog calibration
As the mismatches between the paths result in severe distortions in the spectrum, the performance of the measurement is not satisfied. Therefore, it is an important issue to reduce the gain mismatch, offset mismatch, and timming mismatch. If we continue to research on the same topic, we will try to add some calibration methods to correct the nonidealities in the double-sampling pipelined ADC. As time goes by, a wide variety of calibration techniques has been proposed. Digital or analog calibration