應用雙倍取樣技術之10位元200百萬赫茲互補式金氧半導管式類比數位轉換器

國 立 交 通 大 學

電信工程學系

碩 士 論 文

應用雙倍取樣技術之 10 位元 200 百萬赫茲

互補式金氧半導管式類比數位轉換器

10-Bit 200MHz Double-Sampling Pipelined

Analog-to-Digital Converter

研究生：何俊達

指導教授：洪 崇 智 教授

應用雙倍取樣技術之 10 位元 200 百萬赫茲互補式金氧半導

管式類比數位轉換器

10-Bit 200MHz Double-Sampling Pipelined

Analog-to-Digital Converter

研 究 生：何俊達 Student：Chun-Ta Ho

指導教授：洪崇智 教授 Advisor：Prof. Chung-Chih Hung

國 立 交 通 大 學

電 信 工 程 學 系 碩 士 班

碩 士 論 文

A Thesis

Submitted to Department of Communication Engineering College of Electrical and Computer Engineering

National Chiao Tung University in Partial Fulfillment of the Requirements

for the Degree of Master in Communication Engineering October 2006 Hsinchu, Taiwan.

中華民國九十五年十月

應用雙倍取樣技術之 10 位元 200 百萬赫茲互補式金氧半導

管式類比數位轉換器

研究生：何俊達 指導教授：洪崇智 教授

國立交通大學

電信工程學系碩士班

摘要

導管式類比數位轉換器固有高轉換速度的特性，並且普遍使用在寬頻通訊系 統以及影像系統。然而隨著解析度與轉出率的提高，相對的功率消耗以及需要的 晶片面積也變得越大。因此，雙倍取樣的技術能夠提供加倍取樣率卻不至於使功 率消耗及需要面積倍增的一種方法。 藉由 TSMC 0.18um 1P6M CMOS 製程，我們已經完成一應用雙倍取樣技術之 10 位元 200 百萬赫茲互補式金氧半導管式類比數位轉換器的模擬。此一類比數 位轉換器包括前端的取樣保持電路、8 級串接的轉換器（每級 1.5 位元）以及最 後ㄧ級的 2 位元的快閃式轉換器。所有的類比電路皆以全差動輸入設計，輸入為 2 倍峰對峰的輸入訊號，並且電源供應電壓為 1.8 伏特。在每ㄧ級的運算放大器 是由兩個操作的路徑共用，並且放大器交互地處理這兩個路徑所獲得的取樣訊 號。不但每ㄧ級的運算放大器可以在兩個路徑上共用，子類比數位轉換器也能夠 在兩個路徑上共同使用。如此一來，可使得取樣更加的有效率並且增加導管式類 比數位轉換器的轉換速率。 應用雙倍取樣技術之 10 位元 200 百萬赫茲互補式金氧半導管式類比數位轉換 器已經由晶片中心(CIC)提供的 TSMC 0.18um 1P6M CMOS 製程下線。此一導管 式類比數位轉換器在時脈為 100 百萬赫茲,取樣頻率為 200 百萬赫茲/取樣數並供 以 1.8 伏特的電源電壓，共消耗了 103 毫瓦功率。晶片面積為 1.134*1.380 mm2

。 模擬的差動非線性誤差(DNL)以及積分非線性誤差(INL)分別為±0.75 LSB 和

±0.95 LSB。並且當輸入訊號為 1 百萬赫茲弦波時，訊號對雜訊及失真比(SNDR) 約為 56dB。

10-Bit 200MHz Double-Sampling Pipelined

Analog-to-Digital Converter

Student：Chun-Ta Ho Advisor：Prof. Chung-Chih Hung

Department of Communication Engineering National Chiao Tung University

Hsinchu, Taiwan

Abstract

Pipelined analog-to-digital converters (ADCs) have intrinsic high-speed characteristics and are commonly used in wideband communication and video systems. However, with the higher resolution and throughput rate the power consumption and the required area are getting larger. Therefore, the double-sampling technique provides a method applied to the pipelined ADC to duplicate the sampling rate without consuming two times of power and area.

The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was simulated by TSMC 0.18um 1P6M CMOS process. It consists of one front-end SHA, eight cascaded 1.5-bit stages, and a final 2-bit flash converter in the last stage. All analog circuits are fully differential with a 2Vpp input signal and 1.8V power supply. The operation amplifier in each stage is shared between the two paths and active for one of both paths alternately. Not only the operation amplifier in each stage is shared, but sub-ADC is common to both paths. As a result, it makes sampling more efficient and increases the throughput rate of the pipelined ADC.

The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was finally implemented by TSMC 0.18um 1P6M CMOS process. The pipelined ADC

dissipates 103mW at a 100MHz clock rate and a 200MS/s sampling rate with 1.8V supply voltage. The chip area is 1.134*1.380 mm2. The simulated differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.75 LSB and ±0.95 LSB, respectively. And the peak SNDR about 56dB for an input signal of 1MHz sine wave.

誌謝

本論文得以順利完成，首先，要感謝我的指導教授洪崇智老師在我兩年的研 究生活中，對我的指導與照顧，並且在研究主題上給予我寬廣的發展空間。同時 我也要感謝碩士班兩年內曾經敎過我的每位老師，由於他們熱心的教學，使我在 短短的碩士班兩年內，學習如何設計、製作類比積體電路。此外要感謝劉萬榮教 授、闕河鳴教授、黃淑娟教授撥空擔任我的口試委員並提供寶貴意見，使得本論 文更為完整。還有，感謝國家晶片系統設計中心提供先進的半導體製程，讓我有 機會將所設計的電路得以實現並完成驗證。 其次，我要感謝博士班羅天佑學長以及已畢業的碩士班學長張家瑋、李三 益、邱俊宏、莊誌倫和楊峻岳在研究上的指導與幫助，尤其是家瑋學長，由於他 不吝惜的賜教，使得我的研究得以完成。另外我要感謝學弟邱建豪和廖德文的幫 忙，使我的量測過程能夠順利。接著還要感謝林政翰、蔡宗諺、黃琳家、楊家泰、 黃柏勳和陳家敏等諸位同窗，與我在實驗室一同奮鬥。此外感謝學弟們的支持, 使我的碩士生活增色不少。 特別要感謝我的父母和家人，感謝他們提供了一個穩定且健全的環境，使我 無後顧之憂地完成我的學業。最後要感謝我的女朋友，感謝她一直默默的支持 我、鼓勵我，並在這段成長的路上與我相伴。 總之，我要感謝所有關心我、愛護我和曾經幫助過我的人，願我在未來能有 一絲的榮耀歸予最愛我的家人、老師以及朋友，謝謝你們。

何俊達

2006.10.17

Table of contents

Abstract(Chinese) I Abstract(English) III Acknowledgment V Table of Content VI List of Figures IV List of Tables XIII

Chapter 1 Introduction 1

1.1 Motivation ……….……….……… 1

1.2 Thesis Organization .……….……… 3

Chapter 2 Fundamentals of Analog-to-Digital Converters 5

2.1 Introduction ……….... 5

2.2 The Concept and Performance of A/D Converters ………. 5

2.2.1 Static Specific ……….. 7

2.2.1.1 Offset Error ……… 8

2.2.1.2 Gain Error ……….. 8

2.2.1.3 Differential Non-Linearity Error (DNL) ……….…… 9

2.2.1.4 Integral Non-Linearity Error (INL) ……….. 10

2.2.2 Dynamic Specifications ……… 11

2.2.2.1 Signal-to-Noise Ratio (SNR) ……….… 11

2.2.2.2 Signal-to-Noise and Distortion Ratio (SNDR) ……… 12

2.2.2.3 Spurious Free Dynamic Range (SFDR) …..…………...….… 12

2.2.2.4 Effective Number of Bits (ENOB) ……… 13

2.2.2.5 Dynamic Range (DR) ………. 13

2.2.2.6 Sampling-Time Uncertainty (Aperture jitter)……… 14

2.3 ADC Architectures Overview ………..………. 16

2.3.1 Flash ADC ………. 17

2.3.2 Two Step ADC (or Subranging ADC) ………... 18

2.3.3 Pipelined ADC ………... 20

2.3.4 Cyclic ADC ………...… 21

Chapter 3 The System of Pipelined Analog-to-Digital Converters and

the Double -Sampling Technique 23

3.1 Introduction ……….... 23

3.2 Conventional Pipelined ADC ………. 24

3.3 Nonidealities and Error Sources in Pipeline ADCs ……….. 26

3.3.1 Nonidealities in the Sub-ADC ………. 27

3.3.2 Residue Amplification Gain Error in the MDACs ……….. 28

3.3.3 Nonlinearity in the MDACs ……….…. 29

3.4 Digital Error Correction Technique and Redundancy ……… 30

3.5 1.5 Bit/Stage Architecture ……….. 34

3.6 Calibration Techniques for Pipelined A/D Converter ……… 37

3.6.1 Capacitor Error Averaging ……….……… 37

3.6.2 Commutated Feedback-Capacitor Switching Technique (CFCS) ….… 40 3.7 Double-Sampling Technique ……….…. 43

3.7.1 A Double Sampled Switched Capacitor Delay Cell ……….. 44

3.7.2 Nonidealities in the Double Sampling Circuits ……….… 47

3.7.2.1 Memory Effect ……….……. 47

3.7.2.2 Offset ……….…… 48

3.7.2.3 Gain Mismatch ……….…… 49

3.7.2.4 Timming Mismatch ……….….. 51

Chapter 4 Design of Double-Sampling Pipelined Analog-to-Digital

Converter 53

4.1 Introduction ……….... 53

4.2 Pipelined Stage Accuracy Requirements ……… 54

4.2.1 Opamp Requirements ……… 54

4.2.2 Capacitor Requirements ……… 57

4.3 Behavior Model of the Double-Sampling Pipelined ADC ……….… 58

4.3.1 SHA Circuit ………... 59

4.3.2 Sub_ADC ……….. 61

4.3.3 MDAC ………... 62

4.3.4 2-Bit Flash ………. 63

4.3.5 10-Bit Double-Sampling Pipelined ADC ……….. 64

4.3.6 Ideal DAC Reconstructed Waveform ……… 65

4.3.7 Mismatch Considerations ……….. 67

4.4 The implementation of 10-Bit Double-Sampling Pipelined ADC …………. 68

4.4.1 Operational Amplifier ………. 69

4.4.3 Double-Sampled Sample and Hold Amplifier ………. 77

4.4.4 Sub-ADC ………... 80

4.4.4.1 Comparators ……….. 80

4.4.4.2 1.5-Bit Sub-ADC (Flash Quantizer) ……….…. 83

4.4.5 The 1.5-Bit MDAC ……… 85

4.4.6 The 2-Bit Flash ADC ………. 87

4.4.7 Clock Generator ……… 89

4.4.8 Register and Digital Error Correction Logics ………... 90

4.4.9 Simulated Results of Pipelined ADC ……… 91

Chapter 5 Test Setup and Experimental Results 96

5.1 Introduction ……….... 96

5.2 Test Setup ………... 96

5.2.1 Poewe Supply Regulator ………... 97

5.2.2 Input Termination Circuit ……….. 99

5.2.3 Measured Instruments ……… 100

5.3 The Package and Pin Configuration ……….…... 101

5.4 Experimental Results of Pipelined ADC ……….… 103

Chapter 6 Conclusions 106

6.1 Conclusion ………..… 106

6.2 Future Works ……….. 107

List of Figures

Chapter 1

Chapter 2

Figure 2.1 block diagram of an ADC ……….6

Figure 2.2 Ideal conversion characteristic of a 4-bit ADC ……….7

Figure 2.3 illustrates Offset Error. ………..8

Figure 2.4 Illustrates Gain Error ……….9

Figure 2.5 DNL and INL errors in a 3-bit ADC ………...10

Figure 2.6 the power spectrum with the fundamental and noise ………..13

Figure 2.7 the aperture jitter for full-scale sinusoidal input ……….14

Figure 2.8 N-bit Flash ADC ……….18

Figure 2.9 Two-step ADC ……….19

Figure 2.10 m-bit/stage pipelined ADC ………...20

Figure 2.11 Cyclic ADC ………...22

Figure 2.12 Four-channel time-interleaved ADC and its clock signals …………...22

Chapter 3

Figure 3.1 Block diagram of N-stage pipelined ADC ………..24

Figure 3.2 Timing diagram of the pipelined ADC ………...25

Figure 3.3 (a) Block diagram for 2-bit/stage (b) ideal residue plot ………..26

Figure 3.4 ideal 2-bit stage (a) residue plot (b) conversion characteristic ………...27

Figure 3.5 2-bit stage with comparator offset (a) residue plot (b) conversion characteristic ………...28

Figure 3.6 Residue plot and conversion characteristic of 2-bit stage considering a gain error (a) (b) larger and (c) (d) smaller than 4 ……….29

Figure 3.7 2-bit stage with nonlinearity in MDAC (a) residue plot (b) conversion characteristic ………...30

Figure 3.8 the residue plot with inter stage gain of 2 (a) without offsets (b) with offsets ……….32

Figure 3.9 (a) Block diagram of one stage with offset in ADC and DAC (b) ideal residue versus held input with 1/2 LSB offset ………...32

Figure 3.10 (a) Block diagram of 1.5 bit output per stage(b) ideal residue versus held input without top comparator ………...33

Figure 3.11 RSD correction in digital domain ……….34

Figure 3.13 Switched-capacitor implemention of each pipeline stage ……….36

Figure 3.14 Capacitor error averaging technique: Ø1: sampling phase Ø2 : amplification phase Ø3 : averaging phase ……….37

Figure 3.15 The conventional MDAC operation (a) sampling phase (b) amplifying phase ……….40

Figure 3.16 Residue plot of the conventional stage (a) for C1>C2 (b) for C1<C2 ..41

Figure 3.17 Transfer curve of the conventional stage (a) for C1>C2 (b) for C1<C2 .41 Figure 3.18 The CFCS’s MDAC operation (a)sampling phase (b)amplifying phase..42

Figure 3.19 Residue plot with CFCS technique (a) for C1>C2 (b) for C1<C2 …...43

Figure 3.20 Transfer curve with CFCS technique (a) for C1>C2 (b) for C1<C2 …...43

Figure 3.21 A double-sampled SC delay circuit ………...44

Figure 3.22 A single-ended equivalent circuit of Figure 3.21 during (a)φ1(b)φ2…..46

Figure 3.23 Channel offset in the double sampling model ………...48

Figure 3.24 the spectrum of the double-sampled SC circuit with channel offsets ...49

Figure 3.25 gain mismatch in the double sampling model ………...49

Figure 3.26 Spectrum of the input signal vin (solid line) and the attenuated odd samples of the input signal (dotted line) ………..50

Figure 3.27 timming mismatch in the double sampling model ………52

Chapter 4

Figure 4.1 Operation of pipeline stages implemented with identical stages ………54

Figure 4.2 Double-sampled sample-and-hold circuit behavior mode ………..59

Figure 4.3 The transfer curve for the input signal of (a) 1M sine wave (b) ramp 60 Figure 4.4 Sub-ADC behavior model ..………61

Figure 4.5 The input signal of (a) 1M sine wave (b) ramp versus digital output codes of MSB and LSB ………61

Figure 4.6 MDAC behavior model ………..62

Figure 4.7 The output residue and ital output codes of MSB and LSB for the input signal of (a) 1M sine wave (b) ramp ………..63

Figure 4.8 2-bit flash behavior model ………..63

Figure 4.9 Transfer curve of the MSB and LSB versus the input voltage ………...64

Figure 4.10 10 bit double-sampling pipelined ADC behavior model ………..64

Figure 4.11 The reconstructed behavior model by a ideal DAC ………..65

Figure 4.12 The reconstructed waveform of (a) sine wave (b) ramp ………...66

Figure 4.13 The output spectrum of the sine wave ………..66

Figure 4.14 DNL and INL versus code ………67

Figure 4.15 Gain mismatch (1%) (a) FFT spectrum (b) DNL & INL ..………67

Figure 4.17 Timming mismatch (1%) (a) FFT spectrum (b) DNL & INL ………...68

Figure 4.18 Fully-differential folded cascode op-amp with gain boosting ………..70

Figure 4.19 Dual-phase switched-capacitor CMFB circuit ………..72

Figure 4.20 Simulated AC results of the op-amp ……….73

Figure 4.21 Basic circuit of the bootstrapped switch ………...75

Figure 4.22 Transistor-level implementation of the bootstrapped switch …………76

Figure 4.23 The simulated result of the bootstrapped switch ………...76

Figure 4.24 Timming skew-insensitive double-sampled S/H circuit ………...77

Figure 4.25 Timming diagram of the S/H circuit ……….78

Figure 4.26 Simulated result of the S/H sampling the input sine-wave …………...79

Figure 4.27 Schematic diagram of comparator circuit ……….80

Figure 4.28 Simplified model of the differential pair comparator ………...82

Figure 4.29 Simulated result of the comparator for a threshold of (a) Vref/4 (b) –Vref/4 ………83

Figure 4.30 Schematic of the 1.5-bit Sub-ADC ………...83

Figure 4.31 Simulated result of MSB, LSB, Xa, Ya, Za, Xb, Yb, Zb for an input signal of sine wave ………..84

Figure 4.32 Schematic of the double-sampling 1.5-bit MDAC ………...85

Figure 4.33 Simulated result of the 1.5-bit MDAC ………..87

Figure 4.34 Schematic of the 2-bit Flash ADC ………87

Figure 4.35 Simulated result of the 2-bit Flash ADC ………...88

Figure 4.36 Two-phase clock generator for double-sampling pipelined ADC …….88

Figure 4.37 Simulated results of the non-overlapping clocks ………..89

Figure 4.38 Timing diagram of the clock generator ……….89

Figure 4.39 Positive edge-triggered true single-phase clocked D-flip ……….90

Figure 4.40 Shift register arrays and digital error correction logics ………91

Figure 4.41 Simulated result of the pipelined ADC with the sine-wave input signal .92 Figure 4.42 The spectrum of the 0.98 MHz sine wave ………92

Figure 4.43 Simulated result of the pipelined ADC with the ramp input signal …..93

Figure 4.44 Simulated results of DNL and INL ………...93

Figure 4.45 (a) Layout and (b) floor plan of the pipelined ADC ……….95

Chapter 5

Figure 5.1 Testing setup ………...96

Figure 5.2 The photograph of the experimental pipelined ADC DUT board ……..97

Figure 5.3 Power supply regulator ………...98

Figure 5.4 Bypass filter at the output of the regulator ………..98

Figure 5.6 AC coupled circuit ………..99

Figure 5.7 Signal Generator Agilent E4438C ………100

Figure 5.8 Pulse/pattern generator Agilient 81130A ………..100

Figure 5.9 Logic analyzer HP 16702B ………...101

Figure 5.10 Die photomicrograph of the pipelined ADC ………...101

Figure 5.11 (a) Pin configuration diagram and (b) Pin assignment ………...102

Figure 5.12 Measured results for 100 Msample/s conversion rate (a)Output bit streams (b) Plot chart ……….103

Figure 5.13 Measured results for 150 Msample/s conversion rate (a)Output bit streams (b) Plot chart ……….103

Figure 5.14 65536 points FFT at 1MHz input frequency for (a) 100 MHz sampling frequency (b) 150 MHz ………104

List of Tables

Table 2.1 Different A/D converter architectures ………..16 Table 4.1 Simultated performance of opamp in five process corners ………..74 Table 4.2 Summary of the simulation results of the op-amp ………74 Table 4.3 Digital output codes and controlled signals of 1.5-bit sub-ADC …………84 Table 4.4 Summary of simulated results of the double-sampling pipelined ADC ...94 Table 5.1 Summary of measured results of the pipelined ADC ……….105

Chapter 1

Introduction

1.1 Motivation for the Thesis

Data converters are dominant in modern data and communication systems where increasingly complex processing of analog signals is performed digitally. To achieve the more effective performance, signal processing trends to digital domain. As the result of low power consumption and cost reduction, digital signal processing (DSP) is becoming more and more important. However, in many applications the input and output signals of the system are inherently analog, but the signal processing in the system is digital. Therefore, analog to digital converters (ADC) and digital to analog converters (DAC) are the necessary interfaces in the system. These interfaces achieve the digitization of the received waveform subject to a sampling rate requirement of the system and transform to analog signal in the output after signal processing. However perfect the digital or analog circuits in the system design, they actually need better data converters to perform much well.

There are many applications for the data converters, such as High-Definition Television (HDTV), Multimedia, Software Radio Receivers, Wireless communications, Radar Systems, and Cable Modems. In order to make the system more accurate, reliable, storable, higher yields, the interface using ADCs has become a key component and plays an important role in the system.

employing wider bandwidths and a higher signal-to-noise ratio. High data rates imply wide bandwidths, while a continuous growing complexity of the modulation schemes and the desire for more flexible receivers push the boundary between analog and digital signal processing closer to the antenna. Because of these trends, there is an urgent need for data converters with increasing conversion rates and resolution. At the same time, the increasing integration level leads to systems with a smaller number of chips, the ultimate goal being a single chip solution, the system on a chip (SoC). Data converters are inherently mixed signal circuits and face the challenges on a small scale.

The main challenges in data converter design are decreasing supply voltage, short channel effects in MOS devices, mixed signal issues, the development of design and simulation tools, and testability. In analog to digital converters, they need to be met at the same time as the requirements for the sampling linearity, conversion rate, resolution, and power consumption are being tougher.

In mixed signal-model ADC interfaces, there is some architecture for several kinds of application. For high speed application, flash and folding ADC architectures are useful. For higher resolution sigma-delta architectures is suitable but it is useful in lower sampling rate, whereas pipeline architecture has been widely employed as it properly manages the trade-off between high conversion rate and resolution.

In this research an attempt has been made to design a 10-bit 200MS/s pipelined ADC with reduced power dissipation by using double sampling technique. The pipelined ADC has been implemented with a standard TSMC 0.18µm CMOS 1P6M process. Here the double sampling technique is used in the front-end of

sample-and-hold amplifier (SHA) and the subsequent stages. Two sets of capacitors are used to sample and hold the signal alternately in two non-overlap phases. Two parallel paths provided by the sets of capacitors introduce parallelism and increases the speed of conversion.

1.2 Thesis Organization

This thesis is organized into six chapters.

Chapter 1 briefly introduces the motivation of the thesis.

Chapter 2 describes the concepts of analog-to-digital conversion and performance parameters used to characterize ADCs. Then, several ADC architectures are introduced and the evolution of the pipelined ADC is presented.

Chapter 3 concentrates on the characteristics of the pipelined ADC. The nonlinearity of components is also need to take into account. Finally, the technique of double sampling is introduced, and it will apply to our design in order to speed the throughput rate of the pipelined ADC.

Chapter 4 illustrates the design and implementation of the double-sampling pipelined ADC. Circuit designs and the behavior model of the key blocks will be introduced in detail. Among them are the operational amplifier, the common mode feedback, the comparator, the bootstrapped switch, the sample-and-hold amplifier (SHA), the 1.5-bit architecture, and the 2-bit flash converter. Then, the transistor level simulated results of each circuit are presented. Finally, the simulation of the whole

pipelined ADC and its layout and floor plan are presented.

Chapter 5 presents the testing environment, including the component circuits on the DUT (device under test) board and the instruments. Then, the double-sampling pipelined ADC described in Chapter 4 is fabricated in a standard TSMC 0.18µm CMOS Mixed-Signal process and the measured results of this chip are summarized.

Finally, Chapter 6 is the conclusions of this work. Some suggestions and improved recommendations are proposed for the future work.

Chapter 2

Fundamentals of Analog-to-Digital

Converter

2.1 Introduction

An analog-to-digital converter quantizes an analog signal into digital code at discrete time points. The performance of A/D converters depends on static specifications and dynamic specifications. This chapter first introduces the concept of the analog-to-digital converters and presents the static and dynamic performance parameters for A/D converters. Second, some of the prominent ADC architectures are introduced and the characteristics of these ADCs are described. Third, the technique of double sampling is discussed and the behavior model of the pipelined A/D converter with the double sampling technique is established by simulink.

2.2 The Concept and Performance of A/D Converters

An analog to digital converter (ADC) is a device converting analog signals into digital codes to link the real world and the digital systems. Figure 2.1 shows a block diagram of a traditional A/D converter at Nyquist rate. A low pass filter called an anti-aliasing filter is necessary to avoid the aliasing of higher frequency signals back into the baseband of ADC. The low pass filter is followed by a sample-and-hold amplifier (SHA) that maintains the signal in discrete time. The conversion is accomplished by a quantizer that segments the reference into subranges. Typically,

there are 2N subranges, where N is the number of digital output codes. Finally, the digital encoder is allowed to encode the corresponding digital bits according to the reference of subranges.

Figure 2.1 block diagram of an ADC

The frequency response of the ADC is also illustrated in Figure 2.1. At first we define the bandwidth of the signal, fb, and the sampling frequency, fs. The spectrum of the input signal is aliased at the sampling frequency. If the bandwidth of the signal, fb, is above 1/2fs, the spectrum of the signal will overlap with that of its image. It will result in the unrecoverable area around the frequency 1/2fs. This concept is formalized in the Nyquist rate, which states that the sampling frequency must be at least twice the bandwidth of the signal in order for the signal to be recovered from the samples. The types of ADCs operate in the concept of the Nyquist rate are called Nyquist analog-to-digital converters. [01]

Figure 2.2 illustrates the ideal conversion characteristic of a 4-bit ADC. The transition voltage can be written as

, 2 ref tn N V V = ⋅ n n∈

{

0,1, 2,..., 2N −1 ,

}

(2.1)

where N and Vref represent the bit numbers and the applied reference voltage

respectively. The quantization step (VLSB) is the difference of two transition voltages

and it can be written as

2 ref LSB N V V = (2.2) 0000 0001 0010 0011 Vt1 Vt2 Vt3 Vt4 Digital Output Analog Input Voltage VLSB 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Vt5 Vt6 Vt7 Vt8Vt9Vt10Vt11Vt12Vt13Vt14Vt15Vref

Figure 2.2 Ideal conversion characteristic of a 4-bit ADC

2.2.1

Static Specifications

The static error of an A/D converter is based on the input-output characteristics shown below. Static parameters are directly related with a comparison between the ideal and the expected conversion characteristics. These static characteristics that define the static performance of A/D converters are offset error, gain error, integral nonlinearity (INL), and differential nonlinearity (DNL). These errors will cause inaccuracy output digital codes converted by the ADC. As in most applications these errors really impact the performance of ADC, some of calibration techniques have

been proposed. We will discuss some calibration methods applying in the A/D converter later.

2.2.1.1 Offset Error

The offset error is the deviation between the ideal transition voltage and the actual transition voltage relatively to the quantization step, VLSB. For an ADC with offset

error, the ideal characteristic line is shifted horizontally. Offset error is illustrated in Figure 2.3. 000 001 010 011 100 101 110 111 Vt1 Vt2 Vt3 Vt4 Vt5 Vt6 Vt7 Digital Output Analog Input Voltage

Offset error Actual case_{Ideal case}

Figure 2.3 illustrates Offset Error.

2.2.1.2 Gain Error

The gain error can be defined as the ratio between the slopes of the actual and other the ideal straight lines defined using the two endpoints of both conversion characteristics. Gain error can be measured as the horizontal difference in LSBs between actual and ideal finite resolution characteristics at highest digital code. Gain

error is illustrated in Figure 2.4. [02]

Figure 2.4 Illustrates Gain Error

2.2.1.3 Differential Non-Linearity Error (DNL)

Differential non-linearity error is defined as the difference between two adjacent analog signal values compared to the step size of converter generated by transitions between adjacent pairs of digital code numbers over the whole range of the converter. In other words, DNL is the value compared the actual step size with the ideal step size

voltage (1

2

ref N

V

LSB= ). To achieve a maximum DNL error of ± 0.5 LSB defined at the

resolution level of the ADC (N-bit) , the transition voltages should be within 0.5 to 1.5 LSB at N-bit level.

If the maximum DNL error is larger than -1 LSB at N-bit level, it is guaranteed that the ADC is monotonic, which means that the digital output always increases or is kept constant as the input increases. If DNL error is larger or equal to 1 LSB, it guarantees a non-monotonic transfer function with more missing codes.

DNL error is defined as follows:

( )

( 1 ,) ( ), 1 1 t n actual t n actual V V LSB DNL n LSB + − − = . (2.3)

2.2.1.4 Integral Non-Linearity Error (INL)

INL error is defined as the deviation of the output code of a converter from the straight line drawn through zero and full-scale excluding a possible zero offset. The integral non-linearity error (INL) should not deviate more than ±1/2 LSB of the straight line drawn. INL is also specified after the static gain error has been removed. It is defined as follows:

( )

( ), ( ), 1 t n actual t n ideal V V INL n LSB − = . (2.4)

Figure 2.5 displays examples of DNL and INL errors in 3-bit ADC . [02] [03]

2.2.2 Dynamic Specifications

Dynamic performance parameters depend on the resolution, the sampling frequency and the input signal frequency of an A/D converter and include information about dynamic linearity, distortion, sampling time uncertainty, noise and settling time errors. The most commonly analysis are related to the spectrum of the output signal. With the input of full-scale sine wave, the resulting spectral analysis is rich in information about the dynamic behavior of the ADC.

2.2.2.1 Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the signal power, corresponding to the maximum amplitude of the signal component, and the noise power present at the output of ADC. The SNR includes the quantization noise and other circuits noise excluding any harmonic component of the input signal.

Assuming that the quantization error of an ADC is evenly distributed, the rms value of the generated noise signal, VQ(rms) ,is given by

( ) 12 LSB Q rms V V = (2.5)

where VLSB is the quantization step, and N is the resolution of the ADC. Assuming Vin

is a sinusoidal waveform between 0 and Vref , and considering only the ac power of

( ) ( )

/ 2 2 ₃

20log 20log 20log 2

2 / 12 =6.02 1.76 dB in rms ref N Q rms LSB V V SNR V V N ⎛ ⎞ ⎛ ⎞ ⎛ ⎞ = ⎜_⎜ ⎟_⎟= ⎜_⎜ ⎟_⎟= ⎜_⎜ ⎟_⎟ ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ + (2.6)

2.2.2.2 Signal-to-Noise and Distortion Ratio (SNDR)

Signal-to-Noise and Distortion Ratio is defined as the ratio of the signal power to the total noise power including all spurs and harmonics of the ADC. SNDR is measured for a sinusoidal input and is normally represented as a function of the frequency of the input signal. [04]

2.2.2.3 Spurious Free Dynamic Range (SFDR)

The spurious free dynamic range is defined as the ratio between the maximum rms amplitude of the signal and the rms value of the largest distortion component in a specified frequency range. SFDR indicates the usable dynamic range of an ADC, beyond which a spectral analysis poses special detection and thresholding problems.

To get much more understanding between SNR, SNDR, and SFDR, we can realize the difference between these parameters by the power spectrum illustrated in Figure. 2.6, where S is the fundamental of the input tones, D is the harmonic distortion component, and N is the noise floor. The Spurious Free Dynamic Range (SFDR) is depicted in Figure 2.6. SNR and SNDR are defined as

S S SNR SNDR N N D = = + (2.7)

SFDR D S Power Spectrum fi 2fi 3fi f N

Figure 2.6 the power spectrum with the fundamental and noise[05]

2.2.2.4 Effective Number of Bits (ENOB)

For actual ADCs, a specification often used in place of the SNR or SNDR is ENOB, which is a global indication of ADC accuracy at a specific input frequency and sampling rate. ENOB can be defined as follows:

1.76 6.02

SNDR

ENOB= − bits. (2.8)

2.2.2.5 Dynamic Range (DR)

Dynamic range (DR) is the input power range for which the signal-to-noise ratio of the ADC is greater than 0 dB. The dynamic range of a converter is usually specified as the ratio of the rms value of the maximum amplitude input sinusoidal signal to the rms SNR measured when the same sinusoid is present at the output. The dynamic range can be obtained by measuring the SNR as a function of the input power.

2.2.2.6 Sampling-Time Uncertainty (Aperture jitter)

The aperture jitter comes from the fact that there is a random variation between the clock signal and the effective holding time. For a sinusoidal waveform, the sampling time uncertainty is less of a problem near the peak values. However, the sampling time uncertainty will cause severe errors at the zero crossing where the maximum rate of change occurs.

A ADC with a full-scale sinusoidal input is illustrated in Figure 2.7.

∆V ∆t

X(t) X(k)

Figure 2.7 the aperture jitter for full-scale sinusoidal input

For the continuous-time input X(t), the discrete-time output is generated through the ADC which is controlled by the clock fclk. Taking account of the aperture jitter ∆t,

we can get 1 ( ) ( _s ) _s CLK X k X kT t T f = + ∆ = (2.9)

For a full-scale sinusoidal input with the frequency fin, we can find that

1 ( ) sin(2 ) 2 2 N FS in FS X t = A πf t A = LSB (2.10)

At the zero corssing, we find that the aperture error voltage ∆V must be less than 1 LSB 1 FS in dX V t A f t LSB dt π ∆ ≈ × ∆ < × × ∆ < (2.11)

In consequence, we get the limit of the aperture jitter ∆t for the N bit ADC as follows, 1 2N in t f π ∆ < (2.12)

In the other way, the signal-to-noise ratio (SNR) is limited by the aperture jitter. Let ( ) 1 sin(2 )

2 FS in

X t = A π f t and ∆t be a random variable, then

1 ( ) ( ) ( ) sin(2 ) | 2 1 sin(2 ) cos(2 ) 2 s FS in s t kTs FS in s FS in in s dX t X k X kT t A f kT t dt A f kT A f f kT t π π π π = = + ∆ ≈ + ×∆ ≈ + × ∆ (2.13)

The total signal power and noise power can be calculated to be 2_{( )} 1 2 1 2 2 2 2

8 FS 2 FS in s n

X k = A + A π f × ∆ =t P + (2.14) P

By the equation (2.14), the signal-to-noise ratio of X(k) is 20log(2 ) s in rms n P SNR f t dB P π = = − ∆ (2.15)

From the equation (2.15), it can be seen that SNR is independent of signal amplitude and that it decrease as the signal frequency fin and the rms value jitter ∆trms increases.

2.3

ADC Architectures Overview

Architectures for realizing analog-to-digital converters can be divided into three categories shown in Table 2.1 --- low-to-medium speed, medium speed, and high speed. These different types of A/D converts are designed for several kinds of applications, such as video systems, communication systems, and audio system, etc. In this section, we will discuss some of the prominent A/D converters. In many applications, it is necessary to have a smaller conversion time. Therefore, it has led to the development of high-speed ADCs that use parallel techniques to achieve short conversion times or increase the speed of the individual components in ADCs. However, the high speed ADCs usually cannot be design for very high resolution, like 14-bit resolution or even more. The speed and resolution of A/D converter is a trade off and it is difficult to design ADCs satisfying both demands at the same time. Generally, the oversampling architecture of the ADC is adopted for high resolution design. Low-to-Medium Speed, High Resolution Medium Speed, Medium Resolution High Speed, Low-to-Medium Resolution Integrating Oversampling Successive approximation Algorithmic Flash Two-step Interpolating Folding Pipelined Time-interleaved Table 2.1 Different A/D converter architectures [04]

2.3.1 Flash ADC

Flash ADCs are the very-high-speed converters. The input signal in a flash is fed to 2N-1 comparators in parallel, as shown in Figure 2.8. For a N-bit flash converter, It performs 2N-1 level quantization by dividing the full-scale reference voltage into 2N segments. The reference voltages of the comparators are generated by using a resistor ladder which is connected between the positive and the negative reference voltage: +Vref and –Vref respectively. Each comparator is also connected to a different node of a resistor string. Any comparator connected to a resistor string node where the reference of each comparator is larger than the input signal will have a 1 output, while those connected to nodes with less reference voltages than the input voltage will have 0 outputs. The set of 2N-1 comparator outputs is often referred to as thermometer code and is converted to N-bit binary word with a logic circuit. The input signal of the flash ADC is directly connected to the inputs of the comparators, and all comparators compare the input signal with the reference voltages in the resistor string simultaneously. Thus the speed of the flash ADC is very fast and the speed is only limited by the speed of the comparators. Therefore the flash ADC is capable of high speed.

The flash ADCs are fast but they require a large number of comparators, which typically take up a large area and consume much power. Both area and power become isseues in the parallel ADC as the resolution increases. Therefore the flash ADC is not suitable for high resolution application; typical resolutions are seven bits or below.

Besides, the bubble error is a serious problem. The outputs of the comparators should be a thermometer code with a single transition. However, sometimes a lone 1

will occur within the strings of 0s due to comparator metastability, noise, cross talk, limited bandwidth, etc. To combat the bubble noise, one can widen the input of the 1-of-2N detector. For example, use three-input OR gate to detect the 011 transition in the thermometer input. [04]

+Vref -Vref Vin 2N_{-1 comparators} N-bit digital output 1 of 2N Thermometer

Figure 2.8 N-bit Flash ADC

2.3.2 Two-Step ADC (or Subranging ADC)

In high speed applications, it is difficult to realize high-resolution flash ADCs which have the exponential growth of size and power. In order to overcome these drawbacks, two-step ADC has been proposed. The two-step ADC is demonstrated by separating coarse and fine converters into two paths, as shown in Figure 2.9.

The two-step ADC consists of an S/H circuit, a coarse flash ADC, a DAC, and a fine ADC. The conversion takes two steps. First, the S/H circuit samples the input signal and the M-bit MSB are generated through the coarse flash ADC. These M-bits will correspond to output voltage of the DAC. Second, the output voltage is subtracted from the former analog input voltage. The residue voltage is determined by the fine flash ADC to get the N-bit LSB. Therefore, the M+N bits resolution is reached by combining M-bit MSB and N-bit LSB.

coarse flash ADC fine flash ADC DAC MSBs (M-bits) LSBs (N-bits) S/H Vin Latch M+N bits digital output

Figure 2.9 Two-step ADC

Compared with the flash ADC, the number of the comparators for the architecture of the two-step ADC is reduced from 2M+N-1 to 2M-1+2N-1. For example, to achieve 10-bit resolution, we can reduce the number of comparators from 1023 (in flash architecture) to 62 (in two-step architecture). The area and power consumption is also reduced greatly.

converter but it can allow for higher resolutions than the flash converter because of reducing the number of comparators.

2.3.3 Pipelined ADC

In a pipeline A/D converter, the quantization is distributed along a pipelined signal chain resulting in an effective architecture for high-resolution high-speed ADCs. By the idea of the two-step architecture, it is spread to a multi-stage architecture to construct the pipelined ADC. It has features that improve the throughput rate and tolerance to comparator offsets. The block diagram of the pipelined ADC is shown in Figure 2.10. It consists of M low-resolution stages and each stage generates k bit output codes. Finally, the last pipelined stage is followed by a flash ADC providing p bits. [07]

Figure 2.10 m-bit/stage pipelined ADC

The input signal is first sampled by the front-end S/H circuit and then the output is delivered to Stage 1. For each stage, the input signal is the output of the previous

stage except for the last stage. Each stage comprises a low-resolution sub-analog-to digital converter (sub-ADC) and an arithmetic unit called the multiplying digital-to-analog converter (MDAC) that performs a sample-and-hold (S/H) operation, coarse D/A conversion, subtraction, and amplification. In operation, each stage performs an A/D conversion of k bits, converts the digital output back to analog and subtracts it from the sampled and held analog input. The resulting residue voltage is amplified by 2k.

The architecture of pipelined ADC is the good compromise between area and speed. However, the major limitation on the accuracy in pipelined ADC is the gain amplifier, especially in the first few stages, where accuracy requirements are most stringent. The bandwidth of the gain amplifiers will decide the total throughput rate of the pipelined ADC. And the gain of gain amplifiers influences the total resolution greatly. Therefore, the gain amplifier plays the most important role in the pipelined ADC.

2.3.4 Cyclic ADC

A cyclic ADC is based on a pipelined ADC, as shown in Figure 2.11. It has only one stage but uses the stage repeatedly in a cycle. A cyclic ADC consisted of a single pipeline stage with the output fed back to the input. The delay from the input sample to complete digital output is the same as the pipelined ADC. The cyclic ADC completes N bits by reusing the stage multiple times thus it uses very little chip area and dissipates very low power. However, the throughput rate of the cyclic ADC is much less than the pipelined ADC. For N bit resolution, the cyclic ADC samples the single input signal every (N*clock cycle), and thus the throughput rate of the cyclic

ADC is only 1/N times compared with the pipelined ADC. [08]

Figure 2.11 Cyclic ADC

2.3.5 Time-Interleaved ADC

Figure 2.12 shows the block diagram of an architecture in which four ADCs are used on parallel to achieve four times the sampling rate of a single converter. This method is often known as time-interleaved architecture . The sample-and-hold circuits consecutively sample and apply the input analog signal to their respective ADCs. The digital outputs of the channels are combined with a multiplexer to a single bit-stream. [02] [06]

Chapter 3

The System of Pipelined

Analog-to-Digital Converters and the

Double-Sampling Technique

3.1 Introduction

In this chapter we will concentrate on the pipelined ADC. We will discuss the pipelined architecture in more detail. As we know, the pipelined ADC has large tolerance to the offset of comparators due to the use of the redundancy and digital correction algorithm.

However, the nonlinearity of components is also need to take into account. With the rapid growth in applications, such as communication systems and video systems, the demands for the resolution and throughput rate of the ADC are getting higher. As a result, the accuracy for high-resolution pipelined ADCs is actually a tough challenge. Thus some calibration algorithms are developed to improve the accuracy. We will discuss in later section. Finally, the technique of double sampling is introduced, and it will be applied to our design in order to speed the throughput rate of the pipelined ADC.

3.2 Conventional Pipelined ADC

A conventional pipelined ADC consists of N cascaded stages, each resolving k bits as shown in Figure 3.1. Each stage consists of an S/H circuit, a sub-ADC, a DAC and a gain amplifier, as mentioned before. Digital correction logic is often employed in order to relax the specifications of each stage.

Figure 3.1 Block diagram of N-stage pipelined ADC

The pipelined ADC needs two phase clock phases per conversion. One clock phase is used for sampling the input signal, and the other is employed for holding and delivering the residue voltage. Consecutive stages operate in opposite clock phase and as a result one sample traverses two stages in one clock cycle. Thus the latency in clock cycles is half the number of stages plus one. The complete cycle for processing a given input sample ends when the last stage of the pipeline quantizes the amplified residue provided by the previous stage. Meanwhile, from the beginning of processing a given sample, N/2 new samples are already sampled and being processed inside the

chain. The timming analysis is illustrated in Figure 3.2. For example, the lantency time for the 10-bit pipelined ADC is 5 clock cycles, and the corresponding digitized codes are available at the output after 5 clock cycles of operation. [02]

Figure 3.2 Timing diagram of the pipelined ADC

An example for the ideal 2-bit per stage is shown in Figure 3.3(a). The resolution for this stage is 2 bit, and the full scale input range is divided into four subranges, each one corresponding to a given input digital code among the possible combinations. After subtracting the DAC value from the input signal, the residue is yielded by the gain amplifier, whose gain is 4. So the analog residue is

(

)

4

out in DAC

V = V −V (3.1)

As shown in Figure 3.3(b), the residue plot is the shape of sawtooth with the full scale range between Vref and –Vref. [09]

(a)

(b)

Figure 3.3 (a) Block diagram for 2-bit/stage (b) ideal residue plot

3.3 Nonidealities and Error Sources in Pipeline ADCs

In the pipelined ADC, designs of each stage and components are not ideal, and some error sources need to be considered while designing the circuit. The primary error sources presented in a pipelined ADC are offset errors in the S/H circuits and amplifiers, gain errors in the S/H circuits and amplifiers, sub-ADC nonlinearity, DAC nonlinearity, and opamp settling-time errors.

For an example of ideal 2-bit pipelined stage, the residue plot and conversion characteristic are shown in Figure 3.4. Ideally, the 2-bit stage transistion voltages are 0, -1/2 Vref, 1/2 Vref, where Vref is the reference voltage. The residue amplification characteristic has four segments according to the input voltage. And the conversion characteristic for 2-bit stage is linear. [10]

(a) (b)

Figure 3.4 Ideal 2-bit stage (a) residue plot (b) conversion characteristic

3.3.1 Nonidealities in the Sub-ADC

For the comparators in the sub-ADC, limited accuracy and offset in the decision levels of the comparators produce wrong 2-bit output codes and, consequently, originate deviations in the transition voltages between subranges of the residue characteristic. If the deviations in the residue characteristic exceed the full range scale, the residue propagated to the next stage exceeds the conversion range of the next stage, resulting in saturation which cannot be corrected. So some codes will be missing, as shown in Figure 3.5. The offset error can be resolved by the digital error correction technique, discussed later.

00 01 10 11 Vin Vout Vref -Vref 0 0

-Vref -1/2Vref 1/2Vref Vref

ideal actual

(a) (b)

Figure 3.5 2-bit stage with comparator offset (a) residue plot (b) conversion characteristic

3.3.2 Residue Amplification Gain Error in the MDACs

For a given pipelined stage, a gain error in the residue amplification can cause the residue range to be smaller or larger than the conversion range of the following stage. As a result, missing codes is also apparent to see. Figure 3.6 illustrates these errors where the residue amplification characteristic of the MDAC exhibits different segment-slopes from the ideal ones. Gain errors result from two aspects. On one hand, the residue amplification gain error is basically due to mismatches between the sampling capacitors and the feedback capacitors. On the other hand, the limited DC gain of the operational amplifier contributes to the gain error of the residue. [11] To overcome gain errors, analog or digital self-calibration techniques are employed and they also improve the DNL of the conversion characteristic.

00 01 10 11 Vin Vout Vref -Vref 0 0

-Vref -1/2Vref 1/2Vref Vref

ideal actual (a) (b) 00 01 10 11 Vin Vout Vref -Vref 0 0

-Vref -1/2Vref 1/2Vref Vref

ideal actual

(b) (d)

Figure 3.6 Residue plot and conversion characteristic of 2-bit stage considering a gain error (a) (b) larger and (c) (d) smaller than 4

3.3.3 Nonlinearity in the MDACs

Mismatch errors in the capacitor-array of the MDAC and nonlinearity in the operational amplifier produce differences in the transition magnitudes of the residue. Figure 3.7 illustrates nonlinearity in MDACs and it results in different width for each digital code corresponding to the input voltage. The nonlinearity errors in the MDACs can produce a large number of missing code in the overall conversion characteristic.

00 01 10 11 Vin Vout Vref -Vref 0 0

-Vref -1/2Vref 1/2Vref Vref

ideal actual

(a) (b)

Figure 3.7 2-bit stage with nonlinearity in MDAC (a) residue plot (b) conversion characteristic

3.4 Digital Error Correction Technique and Redundancy

Digital error correction and redundancy are used to eliminate the nonlinearity of sub-ADC and inter stage offset on the overall linearity. With the digital error correction, the pipelined ADC has a large tolerance of the comparator offset. Without the digital error correction, the comparator offset must be no more than one LSB of the pipelined ADC. This technique is attractive because it allows the use of simplified comparators for each stage. Thus, it can reduce the total area and power consumption.

As we mention in 3.3, the comparator offset and gain error may lead the residue to

the next stage to exceed the conversion range and make codes missing. In the pipelined ADC, it needs the same input and output signal range for each stage due to the cascade implementation. The output signal for each stage is produced by the gain amplifier which has gain of 2N, N is the resolution for each stage. The amplified

residue must still within the conversion range for the next stage. However, it is difficult to avoid code missing with the inter stage gain as much as 2N. In order to overcome this problem, the inter stage gain is reduced to 2N-1 so that the amplified residue can remain within the conversion range of the next stage.

In many previous implementations, digital error correction technique has used both addition and subtraction to correct errors. When the offset error occurs in the first stage, the next stage can calibrate the digital codes of the first stage by the digital error correction. The correction logic has three options at each stage (to add, subtract, or do nothing) according to the residue of the previous stage.

To illustrate digital error correction technique in more detail, we take a 2-bit/stage pipelined ADC for example. When the inter stage gain is reduced to 2, the residue range is compressed between 1/2 Vref and -1/2 Vref, illustrated in Fig 3.8 (a). Even if the comparator offset occurs, the residue is still within Vref and –Verf. And then the following stage will correct the output codes by adding or subtracting correction, as shown in Figure 3.8 (b). When one of the decision level of the sub-ADC has an offset, the output of the first stage will exceeds 1/2 Vref. The second stage, sensing the overhanging, will add the output by 1 LSB. In the same way, when the output of the first stage drops below -1/2 Vref, the second stage will subtract 1 LSB. It allows the comparator offset to be as large as 1/4 Vref and the output is still in the input range of the following stage. Digital error correction simply utilizes the extra bit to correct the overhanging section from the previous stage.

00 01 10 11 Vin Vout Vref -Vref 0 0

-Vref -1/2Vref 1/2Vref Vref

ideal actual 00 01 10 11 Vin Vout Vref -Vref 0 0

-Vref -1/2Vref 1/2Vref Vref

ideal actual 1/2Vref -1/2Vref Addition correction Subtraction correction (a) (b)

Figure 3.8 the residue plot with inter stage gain of 2 (a) without offsets (b) with offsets

Since subtraction is equivalent to addition with offset, the required correction logic can be simplified by eliminating the need for the correction logic to do subtraction. So subtraction can be eliminated by intentionally adding a 1/2 LSB offset to both sub-ADC and DAC, as shown in Figure 3.9. After shifting 1/2 LSB offset in

00 01 10 11 Vin Vout Vref -Vref 0 1/4Vref

-Vref -1/4Vref 3/4Vref Vref ideal Shift ½

LSB

(a) (b)

Figure 3.9 (a) Block diagram of one stage with offset in ADC and DAC (b) ideal residue versus held input with 1/2 LSB offset

the decision level, the subranges are separated in different width. The section of “00” is enlarged and that of “11” is reduced. Because the interstage gain is 2, the amplified residue remains within the conversion range of the next stage when the offset of comparators are between 1/2 LSB. Under these conditions, errors caused by the sub-ADC nonlinearity can be corrected, and the correction requires no change and addition.

Since the top-most decision level is 1/2 LSB below the maximum stage input, we can assume that the decision level of the top comparator has an offset of 1/2 LSB adding and it is shifted to the upper bound of the conversion range, as shown in Figure 3.10(b). So the digital output code 11 is eliminated. However, the output code 11 can be recovered by the digital error correction of the next stage and the output residue is still within the conversion range. According to this assumption, removal of the top-most comparator does not change the correction range because the decision can still move by up to ±1/2 LSB before saturating the next stage. [09] [12]

00 01 10 Vin Vout Vref -Vref 0 1/4Vref

-Vref -1/4Vref Vref

ideal 1.5 bit

(a) (b)

Figure 3.10 (a) Block diagram of 1.5 bit output per stage(b) ideal residue versus held input without top comparator

The final block diagram is shown in Figure 3.10(a). The comparator thresholds are at 1/4 Vref and -1/4Vref and the DAC level are at -1/2Vref, 0, 1/2Vref. In each stage, only 2 comparators are needed, which means that the resolution per stage here is 1.5 bits. Reconstruction of the redundant sign digit coded digital stage outputs is performed by adding up the properly delayed stage outputs with one-bit overlap, as indicated in Figure 3.11. [07] [09]

……… ………

Figure 3.11 RSD correction in digital domain

3.5

1.5 Bit / Stage Architecture

As we know, the 1.5 bit/stage pipeline architecture is characteristic of only 3 digital output codes, 00, 01, and 10. If we would like to realize a pipelined ADC with 10 bits resolution, 1.5 bit/stage architecture can be adopted with 9 stages and each stage resolves two bits with a sub-ADC, as shown in Figure 3.12. The 1.5 bit/stage pipeline architecture is employed in the first 8 stage, and the last stage is composed of 2 bit flash qunatizer. According to the input range of signal, from –Vref to -1/4Vref, -1/4Vref to 1/4Vref, and 1/4Vref to Vref, the output residue transfer function can be derived as follows :

( )

( )

( )

2 2 2 2 , 00 4 2 , 01 4 4 2 , 10 4 ref in ref ref in ref ref out in in ref in ref in ref V V V if V V D V V V V if V D V V V if V V D − ⎧ + − < < ⇔ = ⎪ ⎪ − + ⎪ =_⎨ < < ⇔ = ⎪ + ⎪ − < < + ⇔ = ⎪ ⎩ (3.2)

D is the output code for each stage. The transfer function of 1.5-bit/stage is shown in Figure 3.10(b). Because of using the digital error correction technology, the 1.5-bit/stage has lower (2 instead of 4) inter-stage gain than the 2-bit/stage, but it requires more stages (9 stages instead of 5 stages for 10bits ADC) than the 2-bit/stage. By reducing the inter-stage gain, the accuracy requirements on the sub-ADCs are greatly reduced. In this research, a maximum offset voltage of Vref/4 can be tolerated before the bit errors occur.

Figure 3.12 Pipelined ADC with 1.5-bit/stage architecture

how the 1.5 bit/stage architecture works. For simplicity, a single-ended configuration is used. A common, switched-capacitor implementation is chosen which operates on a two-phase clock. During the first phase, the input signal Vi is applied to the input of

the sub-ADC, which has thresholds at Vref/4 and –Vref/4. The input signal ranges from –Vref to Vref. Concurrently, Vi is applied to sampling capacitors Cs and Cf. At

the end of the first clock phase, Vi is sampled across Cs and Cf, and the output of the

sub-ADC is latched. During the second phase, Cf closes a negative feedback loop

around the opamp, while the top plate of Cs is switched to the DAC output. The stage

residue Vo is generated by this configuration. The output of the sub-ADC is used to

select the DAC output voltage, Vdac, through an analog multiplexor. Vdac is

capacitively subtracted from the residue such that :

(1 ) if 4 (1 ) if < 4 4 (1 ) if 4 ref s s i ref i f f ref ref s o i i f ref s s i ref i f f V C C V V V C C V V C V V V C V C C V V V C C ⎧ + − > ⎪ ⎪ ⎪⎪ =_⎨ + − < ⎪ ⎪ ⎪ + + < − ⎪⎩ (3.3)

In the 1.5 bit/stage architecture Cs=Cf is chosen to give a gain of two in the transfer function. In the 1.5 bit/stage architecture Cs=Cf is chosen to give a gain of two in the transfer function. The opamp gain msut be large (>60dB for 10 bit pipelined ADC) enough to reach the specifications of the resolution. Moreover, the opamp must settle to better than 0.1% accuracy in one clock phase (one half cycle). The settling time limits the overall pipelined throughtput. [13]

3.6

Calibration Techniques for Pipelined A/D Converter

A number of calibration Techniques have been developed to make high resolution analog to digital conversion possible in spite of the sources of error mentioned earlier in the chapter. Some of the techniques are based on adding circuit enhancements to reduce the error to a tolerable level. Other techniques do not attempt to fix the error but instead are based on design changes that make the error more tolerable. The basic idea in the calibration methods is to minimize or correct the steps causing nonidealities in the stage transfer functions. These calibration techniques have resulted in an improvement of the resolution capability of pipelined ADCs. This improvement has made it possible to design pipelined ADCs with high resolutions that are limited by thermal noise rather than matching constrains. Because the mismatch and error attached to each step can either be average out, or their magnitude can be measured and corrected.

3.6.1 Capacitor Error Averaging

Capacitor error averaging is the technique for achieving a precise gain of two in the residue amplifier for each stage of the pipelined ADC. The basic idea in the

capacitor error averaging is, rather than fix the sampling and feedback capacitors in the MDAC, to swap their roles. The residue is amplified twice and each time a different feedback capacitor is be used. But an extra clock phase and one additional amplifier are needed in each stage. By adding an extra clock phase, the gain error resulting from the mismatch between the two different feedback loops is compensated during different feedback capacitors interchanging.

1

φ

2

φ

3

φ

Figure 3.14 Capacitor error averaging technique: 1φ : sampling phase 2

φ :amplification phase 3φ :averaging phase

Figure 3.14 shows how the capacitor error averaging technique works during each phase. During 1φ the input signal Vin is sampled onto capacitors C1 and C2. These

two capacitors have mismatch capacitances. As a result, interstage gain is different while using either capacitor as the feedback capacitor. To average gain error, it needs

two amplification phases, one where C1 is used for feedback and the other where C2 is

used for feedback. During the amplification phase 2φ , C1 is used for feedback, and the positive output of the first amplifier Va is sampled onto capacitor C3 while the

negative output of the first amplifier –Va is sampled onto capacitor C4. During the

averaging phase 3φ , C2 is used for feedback, and the negative output -Vb is

connected to C4

In order to analyze the output voltage as a function of the input voltage, we have to assume these capacitors are not match perfectly. So let’s assume that

C1=Ca , C2=(1+α)Ca , C3=2Cb , C4=(1+β)Cb

where |α| <<1, |β|<<1

During the sampling phase 1φ and the amplification phase 2φ , the following expression is obtained. 2 1 ( ) (2 ) ( ) a in in r j in r j in r j C V V V V D V V D V V D C α = + − × = − × + − × (3.4)

During the averaging phase 3φ , we can get as follows, 1 2 ( ) (2 ) ( ) b r j a r j in r j in r j C V V D V V D V V D V V D C α = × + − × ≈ − × − − × (3.5)

Finally, the output function with gain error averaging is derived by combining equations (3.4) and (3.5). 4 3 1 ( ) ( ) 2 (2 ) ( ) o a a b a a b in r j in r j C V V V V V V V C V V D V V D β αβ + = + − + = + − + ≈ − × − − × (3.6)

From the equation (3.6), the oupt voltage can be divided into two parts, which are the ideal residue and the mismatch error. With the capacitor error averaging technique

applying, the mismatch error is actually reduced greatly. [14]

3.6.2 Commutated Feedback-Capacitor Switching Technique

(CFCS)

The commuted feedback-capacitor switching technique (CFCS) is motivated by the fact that in many imaging applications, high resolution but medium accuracy are reauired. Therefore, the commutated feedback-capacitor switching technique (CFCS) relaxes the capacitor matching requirement to the point that it is easy to satisfy in most modern process technologies. [15] As a result, the technique allows the capacitors to be scaled down to the kT/C noise limit. With a reduced capacitive load, opamp power consumption is also reduced.

+ -Vref GND d=1 d=0 Vres C1 C2 (a) (b)

Figure 3.15 The conventional MDAC operation (a) sampling phase (b) amplifying phase

To compare the CFCS technique with the conventional architecture, we examine the effect of the capacitor mismatch in these two styles. For simplicity, we consider the case of a single-ended 1-b/stage pipelined ADC, which has a capacitor mismatch. For the fixed feedback capacitor stage is illustrate in Figure 3.15. During the sampling phase, the input is sampled on both C1 and C2. During the amplifying phase, C1 is

fixed as the feedback capacitor. The residue of the conventional architecture is derived as follows, depending on the input voltage large than Vref/2 (d=1) or less than Vref/2 (d=0) 1 2 1 1 2 2 1 1 ( ) 0 ( ) ( ) , 1 in RES in ref C C V d C V C C C V V d C C + ⎧ ₌ ⎪⎪ = ⎨ ₊ ⎪ _{− =} ⎪⎩ (3.7) (a) (b)

Figure 3.16 Residue plot of the conventional stage (a) for C1>C2 (b) for C1<C2

(a) (b)

Figure 3.17 Transfer curve of the conventional stage (a) for C1>C2 (b) for C1<C2

The residue plot of the conventional stage and the transfer curve of the conventional stage are illustrated in Figure 3.16 and Figure 3.17 individually. If C1<C2,