Thesis Organization

1.1 Motivation

Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in the advance of CMOS processes.

However, electrostatic discharge (ESD) was not scaled down with CMOS technology.

Among the three chip-level ESD test standards, which are human body model (HBM), machine model (MM), and charged device model (CDM), CDM becomes more and more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the application of system on chip (SoC). The electrostatic charges could be stored within the body of IC products due to induction or tribocharging.

Once a certain pin of the IC is suddenly grounded, the electrostatic charges originally stored within the IC will be discharged through the grounded pin, which is called as the CDM ESD event.

1.2 Thesis Organization

To improve the performance of CDM ESD protection devices, two designs against the CDM event are proposed and discussed in this thesis. This thesis contains five chapters. The chapter 2 introduces the background of ESD event and the chip-level CDM event and board-level CDM event. Then, the mechanism that results in CDM discharge phenomenon of internal transistors is illustrated. In the chapter 3, Observe of a CDM event on an IO pin to break down a core transistor gate through

verified in a 65-nm CMOS process. The measurement setup and experimental results including the dc characteristics, field induce CDM test and ESD robustness are stated in detail in the chapter 3. In the chapter 4, by compared the CDM performance of the protection device to protect the internal transistor with different metal line length, resistance, deep N-well (DNW) and pick-up splits, the test is fabricated and verified in a 65-nm CMOS process. The design concept of test device structure is illustrated and then the measurement results including field induce CDM test, and ESD robustness are stated in detail. In the end of this thesis, the conclusion and the future work are given in the chapter 5.

Chapter 2

CDM ESD Events and Test Methods

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2.1 CDM ESD Events in CMOS IC

2.1.1 Introduction of Chip-Level CDM ESD Events

During the assemblage of the IC chips, charges could be stored in the substrate of IC chips due to tribocharging or induction. It is suddenly grounded of the IC chip for once a certain pin, they originally stored in the IC chips will be discharged through the grounded certain pin from the static charges, which is called as the CDM ESD events and shown in Fig.2.1. It delivers a larger of the current in a very short time form the CDM ESD event. The pin of the IC chips is grounded that have many situations. For example, the pin may touch grounded by different metallic site. There are different die sizes of the different IC chips, so they are totally different of their equivalent substrate parasitic capacitances (Cs) form one another. Thus, there are different discharge currents and different CDM ESD performances from the different IC chips. When a device under test (DUT) with a equivalent capacitance of 4pf is under 1-kV CDM ESD test, it rises to more than 15A within several nanoseconds of the CDM ESD discharge current [1]. The discharging current in the CDM ESD events is not only larger, but also faster as compared by HBM and MM ESD events. They may be damaged during CDM ESD events before the ESD protection circuit is turned on of the internal circuits, since the duration of CDM ESD event is much shorter than HBM and MM ESD events. The parasitic capacitor becomes a low impedance device

oxide is most likely to be damaged during CDM ESD events. In the nanoscale CMOS processes, it becomes very thin of the gate oxide, which increases the equivalent capacitance per unit area. Therefore, the gate oxides of MOSFET transistors are more vulnerable to CDM ESD stresses in nanoscale CMOS processes [2-6]. Moreover, many functions are integrated into one IC chip in system on chip applications, which increases the die capacitance through it increased the die size. The larger capacitance stores more static chares under the same charged voltage, so it is larger with larger capacitance of DUT from the CDM ESD current. The larger equivalent capacitance since the larger die size, for ICs with larger die sizes the CDM ESD current is larger.

The thinner gate oxide was used by MOSFET transistors with the larger die size, they are very vulnerable to CDM ESD events in the nanoscale CMOS ICs.

Some of the different steps had been reported to cause chip-level CDM events, ESD levels could be more than 1000 V. Such it may damage the IC products from a high CDM ESD voltage [7].

The chips are induced to store charges when the machines are carried by the carrier in the plastic-leaded-chip-carrier packages. When anyone pin of the charged chip is connected to ground, when CDM ESD events may occur, to solve this problem, it can be utilized of the balanced ionizer in the environment of manufacturing to neutralize it stored of the charges in the chips and the machines.

Fig.2.1 Chip-level CDM ESD events: the stored static charges in the IC product will be quickly discharged, when a certain pin is grounded.

2.1.2. Case Study on Chip-Level CDM ESD Damage

An input buffer fabricated in a 0.8-µm CMOS process is shown in Fig. 2.3(a).

Although the chip is equipped with ESD protection circuit at the input pad, it is still damaged after 1000-V CDM ESD test. As shown in Fig. 2.3(b), the failure point after CDM ESD test is located at the gate oxide of the NMOS in the input buffer. Duo to consideration of noise isolation between I/O cells and internal circuits, the VSS of I/O cells (VSS_I/O) and the VSS of internal circuits (VSS_Internal) are separated in the chip layout. As a result, the ESD clamp device at the input pad can not efficiently protect the gate oxide during CDM ESD stresses, because there is no connection between VSS_I/O and VSS_Internal. The CDM ESD current which damages the gate

(a)

(b)

Fig. 2.2 (a) Discharge current path of the CDM event in an input buffer. (b) The failure point is located at the gate oxide of the input NMOS [13].

Fig. 2.3(a) is shown an output buffer fabricated in a 0.5-µm CMOS process. After 100V CDM ESD test, this chip is damaged. As shown in Fig.2.3(c), the failure picture inspected by scanning electron microscopy (SEM). The picture of SEM has proved that the damage caused by CDM ESD event is located at gate oxide of the NMOS that is connect to the output pad in the internal circuit. It damaged the gate oxide of NMOS () from the CDM ESD current is shown by dash line in an output buffer circuit and the cross-section view in Fig. 2.3(a) and (b), respectively [8].

(a)

(b)

(c)

Fig.2.3 (a) CDM ESD current path in an output buffer. (b) The diagram of cross-section view in an output buffer. (c) After chip-level CDM ESD test, the failure point is located at the gate oxide of an output buffer [13].

2.2 Chip-Level CDM ESD Test Methods [9], [10]

Fig. 2.4(a) and Fig. 2.4(b) show the CDM ESD test methods of socketed and non-socketed CDM (Field-Induce CDM), respectively. In the socketed CDM ESD test, the test chip in the socket on the test fixture board, the CDM voltage is added into the pin which is connected to the VSS and stored in the substrate. Once a test pin of the chip is grounded, the CDM charge stored within the chip will be discharged through the test pin during the CDM test. The test charge is stored in the distributive network of the parasitic capacitances and the inductance elements starting from the CDM voltage supply, the CDM voltage relays, the VSS in the chip, the test pins, and the discharge relay. The discharge currents through the pin under test represent the charge stored in the VSS of the chip and socketed CDM test simulators distributive network [9], [10].

In the non-socketed CDM ESD test, two different methods can be used to raise the component potential for the CDM discharge. Two methods are direct-charging method and filed-induced method. Since the field-induced method is more realistic than direct-charging method, so the CDM related experiments are tested by field-induced method in this experiments. With the field-induced CDM ESD test, the test chips were putted on the charging plate. The charge in the chip was induced by the CDM voltage.

Discharge through all test pins, Including power pins and ground pins, without the same time [4].

(a)

(b)

Fig. 2.4 Two type CDM ESD tester: (a) socketed CDM and (b) non-socketed CDM.

2.2.1 Socketed CDM (SDM) ESD Test on Test Pins

Since electrical charges in natural environment can be either positive or negative, CDM ESD tests have positive and negative modes, too. Moreover, since the CDM ESD events can occur on input/output (I/O) pins, VDD pins, or between different I/O pins of an IC chip, ESD test methods have pin combinations as follows. For everyone pin of an IC chip under the charge-device model ESD tests, there are two test modes as illustrated through Fig. 2-5(a) to 2-5 (b):

(1). Positive-Mode

The positive CDM ESD voltage is added into the pin which is connected to the VSS and stored the voltage in the substrate.

Positive ESD voltage applied to the tested I/O pin with VSS pins relatively grounded.

VDD pins and all other pins are kept floating during the test, as shown in Fig. 2-5(a).

(2). Negative-Mode

The negative CDM ESD voltage is added into the pin which is connected to the VSS and stored the voltage in the substrate.

Negative ESD voltage applied to the tested I/O pin with VSS pins relatively grounded. VDD pins and all other pins are kept floating during the test, as shown in Fig.

2-5(b).

(a)

(b)

Fig.2.5 Pin combination in socketed CDM ESD test (a) positive-mode and (b) negative-mode.

2.2.2 Non-Socketed CDM (FICDM) ESD Test on Test Pins

Since electrical charges in natural environment can be either positive or negative, CDM ESD tests have positive and negative modes, too. Moreover, since the CDM ESD events can occur on input/output (I/O) pins, VDD pins, or between different I/O pins of an IC chip, ESD test methods have pin combinations as follows. For everyone pin of an IC chip under the charge-device model ESD tests, there are two test modes as illustrated through Fig. 2-6(a) to 2-6 (b):

(1). Positive-Mode

The positive CDM ESD voltage is added into the pin which is induced to the substrate and stored the voltage in the substrate.

Positive ESD voltage applied to the tested I/O pin with VSS pins relatively grounded.

VDD pins and all other pins are kept floating during the test, as shown in Fig. 2-6(a).

(2). Negative-Mode

The negative CDM ESD voltage is added into the pin which is induced to the substrate and stored the voltage in the substrate.

Negative ESD voltage applied to the tested I/O pin with VSS pins relatively grounded. VDD pins and all other pins are kept floating during the test, as shown in Fig.

2-6(b).

(a)

(b)

Fig. 2.6 Pin combination in non-socketed CDM ESD test: (a) positive-mode and (b) negative-mode.

2.2.3. Measurement Tester of CDM Test Chip

A CDM ESD test system, Oyrx CDM Orion, was used for field-induced chip-level CDM ESD test. The equipment picture is as Fig. 2.7 shown. The experimental setup of chip-level CDM ESD tests is shown in Fig. 2.8. In the chip-level CDM ESD test, the IC chip device under test (DUT) is put on the charging plate of the field-induced CDM ESD tester. Then set the test pins and discharge to anyone test pins.

Fig. 2.7 The non-socket CDM tester.

Fig. 2.8 The non-socketed CDM (FICDM) tester (Oyrx CDM Orion).

Chapter 3

CDM ESD Robustness of Core Circuits with Coupling Effects

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3.1 Background

The integrated circuit (IC) occur CDM ESD event, when occur at the I/O pin, induce to break down the core transistor gate with inductive coupling event. The inductive coupling is the phenomenon that causes the very fast and high-voltage pulse. The pulse has a pulsewidth of ~100ps.

When the I/O traces occur CDM ESD event that are coupled to core traces, that causes lead to fail on the thin gate oxide transistors in the core, the induced coupling voltage on the core traces then the transistor gate oxide to be break down, causing the transistor function failure, as shown in Fig.3.1.

Fig.3.1 Propagation of an ESD-CDM event on an I/O pin to break down a core

3.2 ESD Protection Design against Coupling Events

3.2.1. Protection Strategy with Ground Shield [13]

In internal circuit, if a ground shield is near the IO trace, the inductively induced voltage on the core traces can be reduced. During a CDM ESD event, a fast and huge transient current flows in the aggressor IO trace. This current set up the magnetic field, the magnetic field induces a voltage on the core traces. When the ground shield insert, a return current is induced with the ground shield. This direction of the induced current is such that tends to oppose of the induced magnetic field. The result is that less the field of magnetic is available to couple the IO trace to the core traces, the result is reduced induced voltage.

Two different of the ground shields may be implemented with multiple metal layers in the typical technology. If there is available space between the I/O trace and the core traces of one ground shield may be implemented. This is called bottom shielding of this technique. Next one, if there is no available space between the I/O traces and the core traces of the ground shield may be implemented, but it is available on the side of the I/O traces. This is called side shielding of this technique.

(a)

(b)

3.2.2. Test Circuit Design against Coupling Events

The test circuit is as Fig. 3.4 shown, the input buffer is connected to the input pad with the I/O trace, and the different core circuit is connected with the core trace, the spacing (S) is between the I/O trace and the core trace, and the length of the I/O trace and core trace is L1, Another part the spacing (S) is between the I/O trace and the core trace, and insert the shield between the I/O trace and core trace, the length of the shield is L2. The lengths of both the I/O trace and the core trace are fixed at 20 µm, 50 µm and 100µm, and the length L2 of the ground shield varies from 0 µm (where it is nonexistent) to 20 µm, 50 µm and 100 µm (when it shields the entire length of the core circuit).

Fig. 3.3 Diagram of the test circuit with couple events.

3.3 Experimental Results and Failure Analysis

The reference test circuit of couple effect in test circuits with distributed ESD protection schemes had been fabricated in a 65-nm CMOS process. The chip micrograph of these fabricated test circuits is shown in Fig. 3.5. In the following sub-sections, the CDM performances, including positive CDM robustness and negative CDM robustness of these fabricated test circuits will be measured and compared. The ESD robustness of these ten test circuits will also be characterized and compared with failure analysis.

Fig.3.4 Layout top view of the test circuit with coupled events.

3.3.1. CDM ESD Robustness

To compare the ESD robustness, the distributed test circuits five ESD-protected distributed test circuits were tested according to the criterion of 30% I-V curve shift at

ground shield of ESD protection only sustains a very low ESD level, which is far below the ESD specifications for commercial ICs.

The ESD robustness of the test circuit is not obviously improved after inserting the ground shield of ESD protection design. The test circuits 1-1 with no insert the ground shield and spacing is 0.78µm between the I/O trace and core trace of test circuit 1-1-1 has the positive CDM ESD level of 400V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 20µm of ground shield and Spacing is 0.3µm between I/O trace and ground shield ESD protection scheme of test circuit 1-1-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of <-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of positive CDM level.

The test circuits 1-2-1 with no insert the ground shield and spacing is 1.98µm between the I/O trace and core trace of test circuit 1-2-1 has the positive CDM ESD level of 400V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 20µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 1-2-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of <-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of positive CDM level.

The test circuits 2-1-1 with no insert the ground shield and spacing is 0.78µm between the I/O trace and core trace of test circuit 2-1-1 has the positive CDM ESD level of 400V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 50µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 2-1-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of <-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of

positive CDM level.

The distributed test circuits 2-2-1 with no insert the ground shield and spacing is 1.98µm between the I/O trace and core trace of test circuit 2-2-1 has the positive CDM ESD level of 400V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 50µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 2-2-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of

<-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of positive CDM level.

The test circuits 3-1-1 with no insert the ground shield and spacing is 0.78µm between the I/O trace and core trace of test circuit 3-1-1 has the positive CDM ESD level of more than 600V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 100µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 3-1-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of

<-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of positive CDM level.

The distributed test circuits 3-2-1 with no insert the ground shield and spacing is 1.98µm between the I/O trace and core trace of test circuit 3-2-1 has the positive CDM ESD level of more than 600V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 100µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 3-2-2 has the positive CDM ESD level of 100V and the negative CDM ESD

grounded, the ground shield and I/O trace synthesis parasitic capacitance, the charge fixed in the substrate where is coupled to I/O trace through the parasitic capacitance.

The charge is caused the current in the ground shield, and the current is inductive coupled to the core circuit. The CDM ESD robustness is very low through the couple

The charge is caused the current in the ground shield, and the current is inductive coupled to the core circuit. The CDM ESD robustness is very low through the couple