Background

3.1 Background

The integrated circuit (IC) occur CDM ESD event, when occur at the I/O pin, induce to break down the core transistor gate with inductive coupling event. The inductive coupling is the phenomenon that causes the very fast and high-voltage pulse. The pulse has a pulsewidth of ~100ps.

When the I/O traces occur CDM ESD event that are coupled to core traces, that causes lead to fail on the thin gate oxide transistors in the core, the induced coupling voltage on the core traces then the transistor gate oxide to be break down, causing the transistor function failure, as shown in Fig.3.1.

Fig.3.1 Propagation of an ESD-CDM event on an I/O pin to break down a core

3.2 ESD Protection Design against Coupling Events

3.2.1. Protection Strategy with Ground Shield [13]

In internal circuit, if a ground shield is near the IO trace, the inductively induced voltage on the core traces can be reduced. During a CDM ESD event, a fast and huge transient current flows in the aggressor IO trace. This current set up the magnetic field, the magnetic field induces a voltage on the core traces. When the ground shield insert, a return current is induced with the ground shield. This direction of the induced current is such that tends to oppose of the induced magnetic field. The result is that less the field of magnetic is available to couple the IO trace to the core traces, the result is reduced induced voltage.

Two different of the ground shields may be implemented with multiple metal layers in the typical technology. If there is available space between the I/O trace and the core traces of one ground shield may be implemented. This is called bottom shielding of this technique. Next one, if there is no available space between the I/O traces and the core traces of the ground shield may be implemented, but it is available on the side of the I/O traces. This is called side shielding of this technique.

(a)

(b)

3.2.2. Test Circuit Design against Coupling Events

The test circuit is as Fig. 3.4 shown, the input buffer is connected to the input pad with the I/O trace, and the different core circuit is connected with the core trace, the spacing (S) is between the I/O trace and the core trace, and the length of the I/O trace and core trace is L1, Another part the spacing (S) is between the I/O trace and the core trace, and insert the shield between the I/O trace and core trace, the length of the shield is L2. The lengths of both the I/O trace and the core trace are fixed at 20 µm, 50 µm and 100µm, and the length L2 of the ground shield varies from 0 µm (where it is nonexistent) to 20 µm, 50 µm and 100 µm (when it shields the entire length of the core circuit).

Fig. 3.3 Diagram of the test circuit with couple events.

3.3 Experimental Results and Failure Analysis

The reference test circuit of couple effect in test circuits with distributed ESD protection schemes had been fabricated in a 65-nm CMOS process. The chip micrograph of these fabricated test circuits is shown in Fig. 3.5. In the following sub-sections, the CDM performances, including positive CDM robustness and negative CDM robustness of these fabricated test circuits will be measured and compared. The ESD robustness of these ten test circuits will also be characterized and compared with failure analysis.

Fig.3.4 Layout top view of the test circuit with coupled events.

3.3.1. CDM ESD Robustness

To compare the ESD robustness, the distributed test circuits five ESD-protected distributed test circuits were tested according to the criterion of 30% I-V curve shift at

ground shield of ESD protection only sustains a very low ESD level, which is far below the ESD specifications for commercial ICs.

The ESD robustness of the test circuit is not obviously improved after inserting the ground shield of ESD protection design. The test circuits 1-1 with no insert the ground shield and spacing is 0.78µm between the I/O trace and core trace of test circuit 1-1-1 has the positive CDM ESD level of 400V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 20µm of ground shield and Spacing is 0.3µm between I/O trace and ground shield ESD protection scheme of test circuit 1-1-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of <-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of positive CDM level.

The test circuits 1-2-1 with no insert the ground shield and spacing is 1.98µm between the I/O trace and core trace of test circuit 1-2-1 has the positive CDM ESD level of 400V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 20µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 1-2-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of <-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of positive CDM level.

The test circuits 2-1-1 with no insert the ground shield and spacing is 0.78µm between the I/O trace and core trace of test circuit 2-1-1 has the positive CDM ESD level of 400V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 50µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 2-1-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of <-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of

positive CDM level.

The distributed test circuits 2-2-1 with no insert the ground shield and spacing is 1.98µm between the I/O trace and core trace of test circuit 2-2-1 has the positive CDM ESD level of 400V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 50µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 2-2-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of

<-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of positive CDM level.

The test circuits 3-1-1 with no insert the ground shield and spacing is 0.78µm between the I/O trace and core trace of test circuit 3-1-1 has the positive CDM ESD level of more than 600V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 100µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 3-1-2 has the positive CDM ESD level of 100V and the negative CDM ESD level of

<-600V, test data is shown in Table 3.2. The test circuit insert ground shield is not improved of positive CDM level.

The distributed test circuits 3-2-1 with no insert the ground shield and spacing is 1.98µm between the I/O trace and core trace of test circuit 3-2-1 has the positive CDM ESD level of more than 600V and the negative CDM ESD level of more than -600V, test data is shown in Table 3.1, next one the Length is 100µm of ground shield and Spacing is 0.9µm between I/O trace and ground shield ESD protection scheme of test circuit 3-2-2 has the positive CDM ESD level of 100V and the negative CDM ESD

grounded, the ground shield and I/O trace synthesis parasitic capacitance, the charge fixed in the substrate where is coupled to I/O trace through the parasitic capacitance.

The charge is caused the current in the ground shield, and the current is inductive coupled to the core circuit. The CDM ESD robustness is very low through the couple current. So the distributed circuit with the not inserted the ground shield of protection scheme exhibits higher CDM ESD robustness than the test circuit with the insert the ground shield protection scheme.

This measured result has verified that the proposed ground shield protection scheme can not provide more efficient ESD protection for the test circuits than the not protection scheme.

(a) (b)

Fig. 3.5 Comparison of I-V curves between (a) normal circuit and (b) failed circuit.

Table 3.1 CDM ESD robustness of test circuit without inserting shielding.

Table 3.2 CDM ESD robustness of test circuit with inserting shielding.

(a)

(b)

Fig. 3.6 Comparison among (a) positive CDM level and (b) negative CDM level of the core circuit.

3.3.2. Failure Analysis

After the test circuit was damaged by ESD, failure analysis is performed to investigate the failure mechanism. Fig.3.7 shows the SEM analysis of I/O buffer inverter circuit in 65-nm CMOS process after field induce CDM testing. The I/O buffer was damaged at the gate oxide, because the CDM current is very fast and very large, when I/O pad grounded the CDM current penetrated the gate oxide cause the gate oxide damage.

Fig. 3.8 show the SEM analysis of test circuit 3-1-2A with insert ground shield structure and test circuit two with insert ground shield structure after +200V CDM ESD testing. In the not insert ground shield structure, the position at gate oxide are all complete, and failure happened because of the couple current by the CDM current on I/O trace. But in the insert ground shield structure, the gate oxides are all complete, and failure happened because of the coupled current by the CDM current on ground shield.

Fig. 3.9 show the SEM analysis of test circuit 3-1-2B with insert ground shield structure and test circuit two with insert ground shield structure after +200V CDM ESD testing. In the not insert ground shield structure, the position at gate oxide are all complete, and failure happened because of the couple current by the CDM current on I/O trace. But in the insert ground shield structure, the gate oxides are all complete, and failure happened because of the couple current by the CDM current on ground shield.

When the positive CDM charge is fixed in substrate, and the ground shield is connected in substrate, when I/O pad is grounded, the CDM charge in substrate is coupled to ground by I/O trace and ground shield, through the back-to-back diode and

was damaged. Therefore, the CDM performance is deteriorated, shown in Fig. 3.10.

When the negative CDM charge is fixed in substrate, and the ground shield is connected in substrate, when I/O pad is grounded, the CDM charge in substrate is coupled to ground by I/O trace and ground shield, through the back-to-back diode and the GGNMOS to discharge of the charge in substrate, and there is normal discharging path for the charge in N-well of core circuit 2, the charge in N-well of core circuit 2 must discharges by gate oxide; thus the gate oxide of PMOS in core circuit 2 was damaged. Therefore, the CDM performance is deteriorated, shown in Fig. 3.10.

Fig. 3.7 SEM photo of I/O buffer in 65-nm CMOS process after +200V CDM ESD testing.

Fig. 3.8 SEM photo of test circuit 3-1-2A with ground shield structure in 65-nm

Fig.3.9 SEM photo of test circuit 3-1-2B with ground shield structure in 65-nm CMOS process after +200 CDM ESD testing.

(a)

(b)

3.4. Summary

In this chapter, two kinds circuit of couple effect ESD protection schemes used to protect the distributed circuit have been reported but not successfully verified in a 65-nm CMOS process. From the experimental results, the circuit of not insert ground shield, the circuit has coupled effect but CDM level is high, the ESD robustness is

>600V in positive CDM and <-600V in negative CDM, but in the circuit of insert ground shield can't remove the coupled effect instead the CDM performance is very low, the ESD robustness is 100V in positive CDM and <-600V in negative CDM.

With the insert ground shield protection scheme can not applied to the distributed circuit, the ESD robustness is too bad. Therefore, we should be think the other method to remove the couple effect when CDM occurrence.

The CDM model reported in the paper from Stanford University (T-ED, 2009) should be re-examined again.

Chapter 4

Investigation on CDM ESD Robustness of Internal MOS Transistors with CDM clamp

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4.1 Background

When integrated circuit (IC) occur CDM ESD event caused the internal circuit are damaged. The CDM event often damages the circuits with special layout or design, and the failure modes for an IC after CDM event include the gate oxide damage, junction damage and source to drain punch-through. In which the gate oxide damage is particularly important, because most of the CDM failure sites of the internal circuit is gate oxide damage. So the internal MOS transistor protection is more important during the CDM event and shown in Fig.4.1.

In this chapter, in order to investigate what kind structures are sensitive to the CDM stress, several various structure are designed. And how to improve CDM ESD robustness form the layout.

4.2 CDM Clamp Devices

4.2.1 Gate-VDD P-Channel MOSFET (GDPMOS) of CDM Clamp Device

Fig.4.2. (a) and (b) shows the device without deep N-Well (DNW) and device with deep N-Well (DNW) for gate-vdd p-channel MOSFET (GDPMOS) of CDM clamp device. Fig.4.3. (a) and (b) shows the positive CDM performance and negative CDM performance of the GDPMOS without deep N-well (DNW) and the GDPMOS with deep N-well (DNW).

The positive CDM performance of the GDPMOS with size 180µm /0.09µm and without deep N-well (DNW) can be achieved 900V, the negative CDM performance of the GDPMOS with size 180µm /0.09µm and without deep N-well (DNW) can be achieved -800V. The positive CDM performance of the GDPMOS with size 360µm /0.09µm and without deep N-well (DNW) can be achieved 1000V, the negative CDM performance of the GDPMOS with size 360µm /0.09µm and without deep N-well (DNW) can be achieved -800V. The positive CDM performance of the GDPMOS with size 540µm /0.09µm and without deep N-well (DNW) can be achieved 1200V, the negative CDM performance of the GDPMOS with size 540µm /0.09µm and without deep N-well (DNW) can be achieved -1000V, the test data is shown in Table 4.1.

The positive CDM performance of the GDPMOS with size 180µm /0.09µm and with deep N-well (DNW) can be achieved 1000V, the negative CDM performance of the GDPMOS with size 180µm/0.09µm and with deep N-well (DNW) can be achieved -900V. The positive CDM performance of the GDPMOS with size 360µm /0.09µm and with deep N-well (DNW) can be achieved 1300V, the negative CDM performance of the GDPMOS with size 360µm /0.09µm and with deep N-well (DNW) can be achieved -1200V. The positive CDM performance of the GDPMOS with size 540µm

/0.09µm and with deep N-well (DNW) can be achieved 1400V, the negative CDM performance of the GDPMOS with size 540µm /0.09µm and with deep N-well (DNW) can be achieved -1200V, the test data is shown in Table 4.1.

Table 4.1 The device size and CDM level of the GDPMOS without deep N-well (DNW) and the GDPMOS with deep N-well (DNW).

(a) (b)

Fig. 4.2 (a) GDPMOS without deep N-well (DNW). (b) GDPMOS with deep N-well (DNW).

(a)

(b)

Fig. 4.3 (a) Positive CDM robustness of GDPMOS with and without deep N-well. (b) Negative CDM robustness of GDPMOS with and without deep N-well.

150 200 250 300 350 400 450 500 550 -1200 150 200 250 300 350 400 450 500 550 700

4.2.2 Gate-Ground N-Channel MOSFET (GGNMOS) of CDM Clamp Device

Fig.4.4. (a) and (b) shows the device without deep N-well (DNW) and device with deep N-well (DNW) for gate-ground n-channel MOSFET (GGNMOS) of CDM clamp device. Fig.4.5. (a) and (b) shows the positive CDM performance and negative CDM performance of the GGNMOS without deep N-well (DNW) and the GGNMOS with deep N-well (DNW).

The positive CDM performance of the GGNMOS with size 180µm /0.09µm and without deep N-well (DNW) can be achieved 900V, the negative CDM performance of the GGNMOS with size 180µm /0.09µm and without deep N-well (DNW) can be achieved -800V. The positive CDM performance of the GGNMOS with size 360µm /0.09µm and without deep N-well (DNW) can be achieved 1000V, the negative CDM performance of the GGNMOS with size 360µm /0.09µm and without deep N-well (DNW) can be achieved -800V. The positive CDM performance of the GGNMOS with size 540µm /0.09µm and without deep N-well (DNW) can be achieved 1200V, the negative CDM performance of the GGNMOS with size 540µm /0.09µm and without deep N-well (DNW) can be achieved -1000V, the test data is shown in Table 4.2.

The positive CDM performance of the GGNMOS with size 180µm /0.09µm and with deep N-well (DNW) can be achieved 1000V, the negative CDM performance of the GGNMOS with size 180µm /0.09µm and with deep N-well (DNW) can be achieved -900V. The positive CDM performance of the GGNMOS with size 360µm /0.09µm and with deep N-well (DNW) can be achieved 1300V, the negative CDM

CDM performance of the GGNMOS with size 540µm /0.09µm and with deep N-well (DNW) can be achieved -1200V, the test data is shown in Table 4.2.

Table 4.2 The device size and CDM level of the GGNMOS without deep N-well (DNW) and the GGNMOS with deep N-well (DNW).

(a) (b)

Fig.4.4 (a) GGNMOS without deep N-Well (DNW). (b) GGNMOS with deep N-Well (DNW).

(a)

(b)

150 200 250 300 350 400 450 500 550 -1300 150 200 250 300 350 400 450 500 550 800

4.3 CDM Clamp with Assistance of R

4.3.1 GDPMOS with Assistance of R

In this experiment of CDM test, the ESD protection devices are the GDPMOS and the p-type protected devices fabricated in a 65-nm CMOS process. The p-type protected devices used to simulate the internal PMOS transistor with the channel width is 20um, and GDPMOS of CDM clamp are applied with protection the p-type protected device with silicide blocking (SAB) and channel width is 180um.

The gate terminal of the p-type protected device is connected to the drain with metal line or a poly resistance of the GDPMOS to emulate the connection of input PMOS transistor in internal circuit. The source, drain and body terminals of the p-type protected device and the source and body terminal of the GDPMOS are connected to bottom pad. The capacitance between the bottom pad and N-Well of the p-type protected devices in the 48-pin DIP package is very small. The structures with different deep N-Well (DNW) location and metal interconnect length and the poly resistance size to test the CDM clamp device’s protection capability.

The GDPMOS is connected a p-type protected device with metal line or a poly resistance, and N+ guard-ring of the p-type protected device, as shown in Fig.4.6 (a), the GDPMOS is connected a p-type protected device in deep N-well (DNW) with metal line or a poly resistance, and N+ guard-ring of the p-type protected device, as shown in Fig.4.6 (b), the GDPMOS in deep N-well (DNW) is connected a p-type protected device with metal line or a poly resistance, and N+ guard-ring of the protected device, as shown in Fig.4.6 (c). There are two different kinds of N+ pick-up layouts to assess its effect on the CDM performance of the protected device. The N+

pick-up splits include only four pick-ups at the corner and one guard-ring to rotate the device, as shown in Fig.4.7 (a)-(c).

(a)

(b)

(c)

Fig. 4.6 (a) GDPMOS and protected device without deep N-well. (b) GDPMOS in deep N-Well. (C) Protected device in deep N-well.

(a)

(b)

Fig. 4.7 N-type protected device with body terminal realized with (a) four pick-ups at the corner and (b) one guard-ring.

4.3.2 GGNMOS with Assistance of R

[15]

In this experiment of CDM test, the ESD protection devices are the GGNMOS and the n-type protected devices fabricated in a 65-nm CMOS process. The n-type protected device used to simulate the internal NMOS transistor with channel width is 20um, and GGNMOS are applied with protection the n-type protected device with silicide blocking (SAB) and channel width is 180um.

The gate terminal of the n-type protected device is connected to the drain with metal line or a poly resistance of the GGNMOS to emulate the connection of input NMOS transistor in internal circuit. The source, drain and body terminals of the n-type protected device and the source and body terminal of the GGNMOS are connected to top pad. The equivalent capacitance between the top pad and P-substrate of the n-type protected device in the 48-pin DIP package is small. The structures with different deep N-well (DNW) location and metal interconnect length and the poly resistance size to test the CDM clamp device’s protection capability.

The GGNMOS is connected a n-type protected device with metal line or the poly resistance, and P+ guard-ring of the n-type protected device, as shown in Fig.4.8 (a), the GGNMOS is connected a n-type protected device in deep N-well (DNW) with

The GGNMOS is connected a n-type protected device with metal line or the poly resistance, and P+ guard-ring of the n-type protected device, as shown in Fig.4.8 (a), the GGNMOS is connected a n-type protected device in deep N-well (DNW) with