Summary

In this chapter, two kinds circuit of couple effect ESD protection schemes used to protect the distributed circuit have been reported but not successfully verified in a 65-nm CMOS process. From the experimental results, the circuit of not insert ground shield, the circuit has coupled effect but CDM level is high, the ESD robustness is

>600V in positive CDM and <-600V in negative CDM, but in the circuit of insert ground shield can't remove the coupled effect instead the CDM performance is very low, the ESD robustness is 100V in positive CDM and <-600V in negative CDM.

With the insert ground shield protection scheme can not applied to the distributed circuit, the ESD robustness is too bad. Therefore, we should be think the other method to remove the couple effect when CDM occurrence.

The CDM model reported in the paper from Stanford University (T-ED, 2009) should be re-examined again.

Chapter 4

Investigation on CDM ESD Robustness of Internal MOS Transistors with CDM clamp

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4.1 Background

When integrated circuit (IC) occur CDM ESD event caused the internal circuit are damaged. The CDM event often damages the circuits with special layout or design, and the failure modes for an IC after CDM event include the gate oxide damage, junction damage and source to drain punch-through. In which the gate oxide damage is particularly important, because most of the CDM failure sites of the internal circuit is gate oxide damage. So the internal MOS transistor protection is more important during the CDM event and shown in Fig.4.1.

In this chapter, in order to investigate what kind structures are sensitive to the CDM stress, several various structure are designed. And how to improve CDM ESD robustness form the layout.

4.2 CDM Clamp Devices

4.2.1 Gate-VDD P-Channel MOSFET (GDPMOS) of CDM Clamp Device

Fig.4.2. (a) and (b) shows the device without deep N-Well (DNW) and device with deep N-Well (DNW) for gate-vdd p-channel MOSFET (GDPMOS) of CDM clamp device. Fig.4.3. (a) and (b) shows the positive CDM performance and negative CDM performance of the GDPMOS without deep N-well (DNW) and the GDPMOS with deep N-well (DNW).

The positive CDM performance of the GDPMOS with size 180µm /0.09µm and without deep N-well (DNW) can be achieved 900V, the negative CDM performance of the GDPMOS with size 180µm /0.09µm and without deep N-well (DNW) can be achieved -800V. The positive CDM performance of the GDPMOS with size 360µm /0.09µm and without deep N-well (DNW) can be achieved 1000V, the negative CDM performance of the GDPMOS with size 360µm /0.09µm and without deep N-well (DNW) can be achieved -800V. The positive CDM performance of the GDPMOS with size 540µm /0.09µm and without deep N-well (DNW) can be achieved 1200V, the negative CDM performance of the GDPMOS with size 540µm /0.09µm and without deep N-well (DNW) can be achieved -1000V, the test data is shown in Table 4.1.

The positive CDM performance of the GDPMOS with size 180µm /0.09µm and with deep N-well (DNW) can be achieved 1000V, the negative CDM performance of the GDPMOS with size 180µm/0.09µm and with deep N-well (DNW) can be achieved -900V. The positive CDM performance of the GDPMOS with size 360µm /0.09µm and with deep N-well (DNW) can be achieved 1300V, the negative CDM performance of the GDPMOS with size 360µm /0.09µm and with deep N-well (DNW) can be achieved -1200V. The positive CDM performance of the GDPMOS with size 540µm

/0.09µm and with deep N-well (DNW) can be achieved 1400V, the negative CDM performance of the GDPMOS with size 540µm /0.09µm and with deep N-well (DNW) can be achieved -1200V, the test data is shown in Table 4.1.

Table 4.1 The device size and CDM level of the GDPMOS without deep N-well (DNW) and the GDPMOS with deep N-well (DNW).

(a) (b)

Fig. 4.2 (a) GDPMOS without deep N-well (DNW). (b) GDPMOS with deep N-well (DNW).

(a)

(b)

Fig. 4.3 (a) Positive CDM robustness of GDPMOS with and without deep N-well. (b) Negative CDM robustness of GDPMOS with and without deep N-well.

150 200 250 300 350 400 450 500 550 -1200 150 200 250 300 350 400 450 500 550 700

4.2.2 Gate-Ground N-Channel MOSFET (GGNMOS) of CDM Clamp Device

Fig.4.4. (a) and (b) shows the device without deep N-well (DNW) and device with deep N-well (DNW) for gate-ground n-channel MOSFET (GGNMOS) of CDM clamp device. Fig.4.5. (a) and (b) shows the positive CDM performance and negative CDM performance of the GGNMOS without deep N-well (DNW) and the GGNMOS with deep N-well (DNW).

The positive CDM performance of the GGNMOS with size 180µm /0.09µm and without deep N-well (DNW) can be achieved 900V, the negative CDM performance of the GGNMOS with size 180µm /0.09µm and without deep N-well (DNW) can be achieved -800V. The positive CDM performance of the GGNMOS with size 360µm /0.09µm and without deep N-well (DNW) can be achieved 1000V, the negative CDM performance of the GGNMOS with size 360µm /0.09µm and without deep N-well (DNW) can be achieved -800V. The positive CDM performance of the GGNMOS with size 540µm /0.09µm and without deep N-well (DNW) can be achieved 1200V, the negative CDM performance of the GGNMOS with size 540µm /0.09µm and without deep N-well (DNW) can be achieved -1000V, the test data is shown in Table 4.2.

The positive CDM performance of the GGNMOS with size 180µm /0.09µm and with deep N-well (DNW) can be achieved 1000V, the negative CDM performance of the GGNMOS with size 180µm /0.09µm and with deep N-well (DNW) can be achieved -900V. The positive CDM performance of the GGNMOS with size 360µm /0.09µm and with deep N-well (DNW) can be achieved 1300V, the negative CDM

CDM performance of the GGNMOS with size 540µm /0.09µm and with deep N-well (DNW) can be achieved -1200V, the test data is shown in Table 4.2.

Table 4.2 The device size and CDM level of the GGNMOS without deep N-well (DNW) and the GGNMOS with deep N-well (DNW).

(a) (b)

Fig.4.4 (a) GGNMOS without deep N-Well (DNW). (b) GGNMOS with deep N-Well (DNW).

(a)

(b)

150 200 250 300 350 400 450 500 550 -1300 150 200 250 300 350 400 450 500 550 800

4.3 CDM Clamp with Assistance of R

4.3.1 GDPMOS with Assistance of R

In this experiment of CDM test, the ESD protection devices are the GDPMOS and the p-type protected devices fabricated in a 65-nm CMOS process. The p-type protected devices used to simulate the internal PMOS transistor with the channel width is 20um, and GDPMOS of CDM clamp are applied with protection the p-type protected device with silicide blocking (SAB) and channel width is 180um.

The gate terminal of the p-type protected device is connected to the drain with metal line or a poly resistance of the GDPMOS to emulate the connection of input PMOS transistor in internal circuit. The source, drain and body terminals of the p-type protected device and the source and body terminal of the GDPMOS are connected to bottom pad. The capacitance between the bottom pad and N-Well of the p-type protected devices in the 48-pin DIP package is very small. The structures with different deep N-Well (DNW) location and metal interconnect length and the poly resistance size to test the CDM clamp device’s protection capability.

The GDPMOS is connected a p-type protected device with metal line or a poly resistance, and N+ guard-ring of the p-type protected device, as shown in Fig.4.6 (a), the GDPMOS is connected a p-type protected device in deep N-well (DNW) with metal line or a poly resistance, and N+ guard-ring of the p-type protected device, as shown in Fig.4.6 (b), the GDPMOS in deep N-well (DNW) is connected a p-type protected device with metal line or a poly resistance, and N+ guard-ring of the protected device, as shown in Fig.4.6 (c). There are two different kinds of N+ pick-up layouts to assess its effect on the CDM performance of the protected device. The N+

pick-up splits include only four pick-ups at the corner and one guard-ring to rotate the device, as shown in Fig.4.7 (a)-(c).

(a)

(b)

(c)

Fig. 4.6 (a) GDPMOS and protected device without deep N-well. (b) GDPMOS in deep N-Well. (C) Protected device in deep N-well.

(a)

(b)

Fig. 4.7 N-type protected device with body terminal realized with (a) four pick-ups at the corner and (b) one guard-ring.

4.3.2 GGNMOS with Assistance of R

[15]

In this experiment of CDM test, the ESD protection devices are the GGNMOS and the n-type protected devices fabricated in a 65-nm CMOS process. The n-type protected device used to simulate the internal NMOS transistor with channel width is 20um, and GGNMOS are applied with protection the n-type protected device with silicide blocking (SAB) and channel width is 180um.

The gate terminal of the n-type protected device is connected to the drain with metal line or a poly resistance of the GGNMOS to emulate the connection of input NMOS transistor in internal circuit. The source, drain and body terminals of the n-type protected device and the source and body terminal of the GGNMOS are connected to top pad. The equivalent capacitance between the top pad and P-substrate of the n-type protected device in the 48-pin DIP package is small. The structures with different deep N-well (DNW) location and metal interconnect length and the poly resistance size to test the CDM clamp device’s protection capability.

The GGNMOS is connected a n-type protected device with metal line or the poly resistance, and P+ guard-ring of the n-type protected device, as shown in Fig.4.8 (a), the GGNMOS is connected a n-type protected device in deep N-well (DNW) with metal line or the poly resistance, and P+ guard-ring of the protected device, as shown in Fig.4.8 (b), the GGNMOS in deep N-well (DNW) is connected a protected device with metal line or the poly resistance, and P+ guard-ring of the protected device, as shown in Fig4.8 (c).

There are two different kinds of P+ pick-up layouts to assess its effect on the CDM performance of the protected device. The P+ pick-up splits include only four pick-ups

(a)

(b)

(c)

Fig. 4.8 (a) GGNMOS and protected device without deep N-well. (b) Protected device with deep N-well. (C) GGNMOS with deep N-well.

(a)

(b)

Fig. 4.9 N-type protected device with body terminal realized with (a) four pick-ups at the corner and (b) one guard-ring.

4.4. Experimental Results

The reference distributed test circuit in ten distributed circuits with distributed ESD protection schemes had been fabricated in a 65-nm CMOS process. The chip micrograph of these fabricated distributed circuits is shown in Fig.4.10. In the following sub-sections, the CDM performances, including positive CDM robustness and negative CDM robustness of these fabricated test circuits will be measured and compared. The ESD robustness of these test circuit will also be characterized and compared with failure analysis.

Fig.4.10 Layout top view of the test circuits.

4.4.1. CDM ESD Robustness of Deep N-Well

In this work, the CDM clamping by test circuit are GDPMOS and GGNMOS with different variable or different dimensions. The GDPMOS is realized with a p-type protection device and a PMOS device (W/L) of 180μm/0.09μm, whose gate and body is connected to Vdd. The GGNMOS is realized with a n-type protection device and a NMOS device (W/L) of 180μm/0.09μm, whose gate and body is connected to

Vss. The CDM ESD levels of devices were measured by ZapMaster and the tested devices were stressed by three continuous ESD zaps at every CDM ESD test level under non-socketed CDM (field-induce CDM) mode. The failure criterion is 30%

leakage current shift under 1-V VDD bias.

The positive and negative CDM level of the GDPMOS is connected a p-type protected device with length is 1.5µm of metal line and N+ guard-ring of the p-type protected device can be achieved 200V and -300V. The positive and negative CDM level of the GDPMOS is connected a p-type protected device with length is 300µm of metal line and N+ guard-ring of the n-type protected device can be achieved 400V and -500V. The positive and negative CDM level of the GDPMOS in deep N-well (DNW) is connected a n-type protected device with length is 1.5µm of metal line and N+

guard-ring of the p-type protected device can be achieved 100V and -300V. The positive and negative CDM level of the GDPMOS in deep N-well (DNW) is connected a p-type protected device with length is 300µm of metal line and N+ guard-ring of the p-type protected device can be achieved 200V and -500V. The positive and negative CDM level of the GDPMOS is connected a n-type protected device in deep N-well (DNW) with length is 1.5µm of metal line and N+ guard-ring of the p-type protected device can be achieved 100V and -200V. The positive and negative CDM level of the GDPMOS is connected a p-type protected device in deep N-well (DNW) with length is 300µm of metal line and P+ guard-ring of the p-type protected device can be achieved 200V and -400V.

The positive and negative CDM level of the GDPMOS is connected p-type protected device with resistance is 0.1kΩ of poly resistor and N+ guard-ring of the

400V and -500V. The positive and negative CDM level of the GDPMOS is connected p-type protected device with resistance is 10kΩ of poly resistor and N+ guard-ring of the n-type protected device can be achieved 800V and -700V.

The positive and negative CDM level of the GDPMOS is connected p-type protected device in deep N-well (DNW) with resistance is 0.1kΩ of poly resistor and N+ guard-ring of the p-type protected device can be achieved 200V and -400V. The protected device can be achieved 800V and -700V.

The positive and negative CDM level of the GDPMOS is connected p-type protected device with resistance is 0.1kΩ of poly resistor and N+ guard-ring of the p-type protected device can be achieved 200V and -300V. The positive and negative CDM level of the GDPMOS is connected p-type protected device with resistance is 1kΩ of poly resistor and N+ guard-ring of the p-type protected device can be achieved 300V and -500V. The positive and negative CDM level of the GDPMOS is connected n-type protected device with resistance is 10kΩ of poly resistor and N+ guard-ring of the p-type protected device can be achieved 800V and -700V.

Fig. 4.11 (a) compares the positive CDM level on the different p-type device with metal line and DNW, as the length of metal line increased, the positive CDM robustness increased. The different p-type device put in DNW can not remove the CDM discharge current, it will be even worse of the p-type device put in DNW.

Fig. 4.11 (b) compares the negative CDM level on the different p-type device with metal line and DNW, as the length of metal line increased, the negative CDM

robustness increased. The different p-type device put in DNW can not remove the CDM discharge current, it will be even worse of the p-type device put in DNW.

Fig. 4.12 (a) compares the positive CDM level on the different p-type device with a poly resistor and DNW, as the length of metal line increased, the positive CDM robustness increased. The different p-type device put in DNW can not remove the CDM discharge current, it will be even worse of the p-type device put in DNW.

Fig. 4.12 (b) compares the negative CDM level on the different p-type device with a poly resistor and DNW, as the length of metal line increased, the negative CDM robustness increased. The different p-type device put in DNW can not remove the CDM discharge current, it will be even worse of the p-type device put in DNW.

Table 4.3 Show the positive CDM level and negative CDM level on the different p-type device with poly resistor, metal line and DNW.

The positive and negative CDM level of the GGNMOS is connected a n-type protected device with length is 1.5µm of metal line and P+ guard-ring of the n-type protected device can be achieved 400V and -200V. The positive and negative CDM level of the GGNMOS is connected a n-type protected device with length is 300µm of metal line and P+ guard-ring of the n-type protected device can be achieved 600V and -500V. The positive and negative CDM level of the GGNMOS in deep N-well (DNW) is connected a n-type protected device with length is 1.5µm of metal line and P+

guard-ring of the n-type protected device can be achieved 200V and -100V. The positive and negative CDM level of the GGNMOS in deep N-well (DNW) is connected a n-type protected device with length is 300µm of metal line and P+

guard-ring of the n-type protected device can be achieved 500V and -400V. The

negative CDM level of the GGNMOS is connected a n-type protected device in deep N-well (DNW) with length is 300µm of metal line and P+ guard-ring of the n-type protected device can be achieved 700V and -600V.

The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 0.1kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved 400V and -300V. The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 1kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved 600V and -400V. The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 10kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved more than 800V and -800V.

The positive and negative CDM level of the GGNMOS is connected n-type protected device in deep N-well (DNW) with resistance is 0.1kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved 200V and -100V. The protected device can be achieved 800V and -700V.

The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 0.1kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved 500V and -400V. The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 1kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved 700V and -600V. The positive and negative CDM level of the GGNMOS is connected

n-type protected device with resistance is 10kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved more than 800V and -800V.

Fig. 4.13 (a) compares the positive CDM level on the different n-type device with metal line and DNW, as the length of metal line increased, the positive CDM robustness increased. The different n-type device put in DNW can not remove the CDM discharge current, it will be even worse of the n-type device put in DNW.

Fig. 4.13 (b) compares the negative CDM level on the different n-type device with metal line and DNW, as the length of metal line increased, the negative CDM robustness increased. The different n-type device put in DNW can not remove the CDM discharge current, it will be even worse of the n-type device put in DNW.

Fig. 4.14 (a) compares the positive CDM level on the different n-type device with a poly resistor and DNW, as the length of metal line increased, the positive CDM robustness increased. The different n-type device put in DNW can not remove the CDM discharge current, it will be even worse of the n-type device put in DNW.

Fig. 4.14 (b) compares the negative CDM level on the different n-type device with a poly resistor and DNW, as the length of metal line increased, the negative CDM robustness increased. The different n-type device put in DNW can not remove the CDM discharge current, it will be even worse of the n-type device put in DNW.

Table 4.4 Show the positive CDM level and negative CDM level on the different n-type device with poly resistor, metal line and DNW.

(a)

(b)

Fig.4.11 Comparison among (a) positive CDM level and (b) negative CDM level of the different p-type device with metal line and DNW.

0 50 100 150 200 250 300

(a)

(b)

Fig.4.12 Comparison among (a) positive CDM level and (b) negative CDM level of

0 2 4 6 8 10

(a)

(b)

Fig.4.13 Comparison among (a) positive CDM level and (b) negative CDM level of the different n-type device with metal line and DNW.

0 50 100 150 200 250 300

(a)

(b)

Fig. 4.14 Comparison among (a) positive CDM level and (b) negative CDM level of the different n-type device with poly resistor and DNW.

0 2 4 6 8 10

Table 4.3 The positive CDM level and negative CDM level of the different p-type device with poly resistor, metal line, and DNW.

Table 4.4 The positive CDM level and negative CDM level of the different n-type device with poly resistor, metal line, and DNW.

4.4.2. Protected Device with Pick-Up / Guard-Ring

In this work, the CDM clamping by test circuit are GDPMOS and GGNMOS with different variable or different dimensions. The GDPMOS is realized with a p-type protection device and a PMOS device (W/L) of 180μm/0.09μm, whose gate and body is connected to Vdd. The GGNMOS is realized with a n-type protection device and a NMOS device (W/L) of 180μm/0.09μm, whose gate and body is connected to Vss. The CDM ESD levels of devices were measured by ZapMaster and the tested

In this work, the CDM clamping by test circuit are GDPMOS and GGNMOS with different variable or different dimensions. The GDPMOS is realized with a p-type protection device and a PMOS device (W/L) of 180μm/0.09μm, whose gate and body is connected to Vdd. The GGNMOS is realized with a n-type protection device and a NMOS device (W/L) of 180μm/0.09μm, whose gate and body is connected to Vss. The CDM ESD levels of devices were measured by ZapMaster and the tested