Protected Device with Pick-Up / Guard-Ring

In this work, the CDM clamping by test circuit are GDPMOS and GGNMOS with different variable or different dimensions. The GDPMOS is realized with a p-type protection device and a PMOS device (W/L) of 180μm/0.09μm, whose gate and body is connected to Vdd. The GGNMOS is realized with a n-type protection device and a NMOS device (W/L) of 180μm/0.09μm, whose gate and body is connected to Vss. The CDM ESD levels of devices were measured by ZapMaster and the tested level of the GDPMOS is connected a p-type protected device with length is 300µm of metal line and N+ pick-up of the n-type protected device can be achieved 300V and -400V. The positive and negative CDM level of the GDPMOS is connected a p-type protected device with length is 1.5µm of metal line and N+ guard-ring of the p-type protected device can be achieved 200V and -300V. The positive and negative CDM level of the GDPMOS is connected a p-type protected device with length is 300µm of metal line and N+ guard-ring of the n-type protected device can be achieved 400V and -500V.

The positive and negative CDM level of the GDPMOS is connected p-type protected device with resistance is 0.1kΩ of poly resistor and N+ pick-up of the p-type

-400V. The positive and negative CDM level of the GDPMOS is connected p-type protected device with resistance is 10kΩ of poly resistor and N+ pick-up of the n-type protected device can be achieved 700V and -600V. The positive and negative CDM level of the GDPMOS is connected p-type protected device with resistance is 0.1kΩ of poly resistor and N+ guard-ring of the p-type protected device can be achieved 200V and -400V. The positive and negative CDM level of the GDPMOS is connected p-type protected device with resistance is 1kΩ of poly resistor and N+ guard-ring of the p-type protected device can be achieved 400V and -500V. The positive and negative CDM level of the GDPMOS is connected p-type protected device with resistance is 10kΩ of poly resistor and N+ guard-ring of the n-type protected device can be achieved 800V and -700V.

Fig. 4.15 (a) and (b) compares the positive CDM level and negative CDM level on the different p-type device with metal line and N+ pick-up, as the length of metal line increased, the positive and the negative CDM robustness increased. The CDM performance of the protected device with N+ guard-ring is better than the protected device with N+ pick-up.

Fig. 4.16 (a) and (b) compares the positive CDM level and negative CDM level on the different p-type device with a poly resistor and N+ pick-up, the series resistance significantly increases the positive and the negative CDM robustness. The CDM performance of the protected device with N+ guard-ring is better than the protected device with N+ pick-up. Table 4.5 Show the positive CDM level and negative CDM level on the different p-type device with poly resistor, metal line and N+ pick-up.

The positive and negative CDM level of the GGNMOS is connected a n-type protected device with length is 1.5µm of metal line and P+ pick-up of the n-type protected device can be achieved 100V and -200V. The positive and negative CDM level of the GGNMOS is connected a n-type protected device with length is 300µm of

metal line and P+ pick-up of the n-type protected device can be achieved 300V and -400V. The positive and negative CDM level of the GGNMOS is connected a n-type protected device with length is 1.5µm of metal line and P+ guard-ring of the n-type protected device can be achieved 400V and -200V. The positive and negative CDM level of the GGNMOS is connected a n-type protected device with length is 300µm of metal line and P+ guard-ring of the n-type protected device can be achieved 600V and -500V.

The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 0.1kΩ of poly resistor and N+ pick-up of the n-type protected device can be achieved 100V and -200V. The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 1kΩ of poly resistor and P+ pick-up of the n-type protected device can be achieved 300V and -400V. The positive and negative CDM level of the GDPMOS is connected n-type protected device with resistance is 10kΩ of poly resistor and P+ pick-up of the n-type protected device can be achieved 700V and -600V. The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 0.1kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved 400V and -300V. The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 1kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved 600V and -400V. The positive and negative CDM level of the GGNMOS is connected n-type protected device with resistance is 10kΩ of poly resistor and P+ guard-ring of the n-type protected device can be achieved more than 800V and -800V.

performance of the protected device with P+ guard-ring is better than the protected device with P+ pick-up. Fig. 4.18 (a) and (b) compares the positive CDM level and negative CDM level on the different n-type device with a poly resistor and DNW, the series resistance significantly increases the positive and the negative CDM robustness.

The CDM performance of the protected device with P+ guard-ring is better than the protected device with P+ pick-up. Table 4.6 Show the positive CDM level and negative CDM level on the different n-type device with poly resistor, metal line and P+

pick-up.

(a)

(b)

Fig. 4.15 Comparison among (a) positive CDM level and (b) negative CDM level of

0 50 100 150 200 250 300

(a)

(b)

Fig.4.16 Comparison among (a) positive CDM level and (b) negative CDM level of the different p-type device with poly resistor and N+ pick-up.

0 2 4 6 8 10

(a)

(a)

(b)

Fig.4.18 Comparison among (a) positive CDM level and (b) negative CDM level of the different n-type device with poly resistor and P+ pick-up.

0 2 4 6 8 10

Table 4.5 The positive CDM level and negative CDM level of the different p-type device with poly resistor, metal line, and pick-up.

Table 4.6 The positive CDM level and negative CDM level of the different n-type device with poly resistor, metal line, and pick-up.

4.4.3. Failure Analysis

After the test circuit was damaged by ESD, failure analysis is performed to investigate the failure mechanism. Fig. 4.19 shows the SEM analysis of the protected device with GGNMOS in DNW in 65-nm CMOS process after positive CDM +600V of the field induce CDM (FICDM) testing. Fig. 4.20 shows the SEM analysis of the protected device with GGNMOS in DNW in 65-nm CMOS process after positive CDM -500V of the field induce CDM (FICDM) testing.

Fig. 4.21 shows the SEM analysis of the protected device with GDPMOS in 65-nm CMOS process after positive CDM +600V of the field induce CDM (FICDM) testing.

Fig. 4.22 shows the SEM analysis of the protected device with GDPMOS in 65-nm CMOS process after positive CDM -500V of the field induce CDM (FICDM) testing.

The device of protection with protected device was damaged at the gate oxide of protected device, because the CDM current is very fast and very large, when I/O pad grounded the CDM current penetrated the gate oxide cause the gate oxide damage.

During the positive cycle, the n-type CDM clamp uses parasitic diode to discharge the CDM current. During the negative cycle, the n-type CDM clamp uses parasitic bipolar to discharge the CDM current. So, the n-type test devices all are with better positive CDM performance.

During the positive cycle, the p-type CDM clamp uses parasitic bipolar to discharge the CDM current. During the negative cycle, the p-type CDM clamp uses parasitic diode to discharge the CDM current. So, the p-type test devices all are with better negative CDM performance.

As the n-type device with deep N-well (DNW), there are some other parasitic components (diodes and junction capacitors) in the discharge path. Which result in the smaller capacitance in the discharge path than that of the device without deep N-well

(DNW). As the capacitance decreases, the CDM stress current will be decreased. So, the n-type protected device CDM performance can be improved significantly as it is put in the deep N-well (DNW).

As increasing interconnect metal length and resistance of ploy resistor to the p-type and n-type protected device corresponds to increase the interconnect resistance, the CDM stress current level of the protected device will be decreased and more CDM stress currents will flow through the CDM clamp device. Therefore, better CDM performance can be achieved. If the n-type protected device with deep N-well (DNW) can reduce the current from all bus-line capacitors to flow into the n-type protected device. Because the CDM clamp devices are surrounded by a P+ guard-ring, it will induce the non-uniform CDM current stress to the n-type protected device. The CDM clamp devices with deep N-well (DNW), it has not discharge path by CDM clamp.

Thus, putting the protected device in the deep N-well (DNW) can get better CDM performance, but putting the CDM clamp devices in the deep N-well (DNW) are opposite.

Fig.4.19 The SEM photo of protected device with GGNMOS in DNW after +600V CDM ESD testing.

Fig.4.20 The SEM photo of protected device with GGNMOS in DNW after -500V CDM ESD testing.

Fig.4.21 The SEM photo of protected device with GDPMOS after +500V CDM ESD testing.

4.4. Summary

In this chapter, the CDM ESD protection design for internal transistor in a 65-nm CMOS process is presented. The CDM performance of n-type protected device can be improved as putting it into the DNW, but the p-type protected device is opposite. The CDM performance of the protected device with guard-ring is better than the protected device with pick-up.

The CDM performances of the n-type protected devices can be improved as

realizing them with the DNW, but those of n-type CDM clamps can not be improved.

Chapter 5

Conclusion and Future Work

━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━

5.1 Conclusion

The new proposed structures for CDM ESD protection in 65-nm CMOS processes in which positive CDM performance and negative CDM performance measured by the field induce CDM tester and the dc curve tracer can be adjusted to the specific requirements has been presented. The CDM performance of the inserted shielding structure can not be increased by the shielding length. With the insert ground shield protection scheme can not applied to the distributed circuit, the ESD robustness is too bad. So we should be think the other method to remove the couple effect when CDM occurrence.

The CDM ESD protection design for internal transistor in a 65-nm CMOS process is presented. The CDM performance of n-type protected device can be improved as protected devices about nine times. The layout dimension of CDM clamps is too large

Besides chip-level CDM ESD events, board-level CDM ESD events becomes more important recently, because it often causes the ICs to be damaged after the IC is installed to the circuit board of electronic system. Since the board-level CDM ESD damages are easily mistaken for EOS damages and no effective design against board-level CDM ESD events was reported so far, the formal board-level CDM ESD test standard and method should be considered and developed. Moreover, due to the threat of the board-level CDM ESD events in real-world failures, the test standard of board-level CDM ESD should be established in the near future for IC industry to verify their products.

References

[1] Electrostatic Discharge (ESD) Sensitivity Testing - Charged Device Model (CDM), EIA/JEDEC Standard Test Method 5.3.1. 1999.

[2] Y. Fong and C. Hu, “Internal ESD transients in input protection circuits,” in Proc. International Reliability Physics Symp., 1989, pp. 77-81.

[3] K. Cheung, “Plasma-charging damage and ESD, help each other,” in Proc.

EOS/ESD Symp., 1999, pp. 38-42.

[4] C. Duvvury and A. Amerasekera, “Advanced CMOS protection device trigger mechanisms during CDM,” in Proc. EOS/ESD Symp., 1995, pp.162-174

[5] K. Verhaege, C. Russ, J-M. Luchies, G. Groeseneken, and F. Kuper,

“Grounded-gate nMOS transistor behaviour under CDM ESD stress conditions,” IEEE Trans. Electron Devices, vol. 44, no.11, pp. 1972-1980, Nov.

1997.

[6] C. Russ, K. Verhaege, K. Bock, P.J. Roussel, G. Groeseneken, and H.E. Maes,

“A compact model for the grounded-gate nMOS behavior under CDM ESD stress,” in Proc. EOS/ESD Symp., 1996, pp. 302-315.

[7] S. Malobabic', D. Ellis, J. Salcedo, Y. Zhou, J. Hajjar, and J. Liou“Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress,”

in Proc. IEEE International Caribbean Conference on Devices, Circuits and Systems, 2008, pp. 1-8.

[8] M. Tanaka and K. Okada, “CDM ESD test considered phenomena of division and reduction of high voltage discharge in the environment,” in Proc. EOS/ESD Symp., 1996, pp.54-61.

[9] For Electrostatic Discharge Sensitivity Testing—Charged Device Model

[10] JEDEC, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components, JESD22-C101C, 2004.

[11] J. Vinson and J. Liou, “Electrostatic discharge in semiconductor devices: An overview,” in Proc. IEEE, vol. 86, no. 2, pp.399-418, Feb. 1998.

[12] M.-D. Ker and Y.-W. Hisao, “Investigation on board-level CDM ESD issue in products,” IEEE Trans. on Device and Materials Reliability, vol. 8, 2008, pp.

694-704.

[13] T. Chen, C. Ito, W. Loh, W. Wang, K. Doddapaneni, S. Mitra, and R. Dutton,

“Design methodology and protection strategy for ESD-CDM robust digital system design in 90-nm and 130-nm technologies,”IEEE Trans. Electron Devices, vol. 56, 2009, pp. 275-283.

[14] C. Ito and W. Loh, “A new mechanism for core device failure during CDM ESD events,”in Proc. EOS/ESD Symp., 2007, pp.78-85.

[15] J. Lee, J. Shih, M. Shiue, C. Tsai, A. Liang, D. Su, and K. Wu, “The study of sensitive circuit and layout for CDM improvement,” in Proc. IEEE International Symposium on The Physical and Failure Analysis of Integrated Circuits, 2009, pp. 228-232.

VITA

姓 名：張堂龍 學 歷：

國立台灣科技大學電機工程系 (94 年 9 月~97 年 6 月) 國立交通大學電子研究所碩士班 (97 年 9 月~99 年 9 月)

研究所修習課程：

類比積體電路 吳介琮教授

數位積體電路 周世傑教授

積體電路之靜電放電防護設計特論 柯明道教授

半導體物理及元件（一） 侯拓宏教授

穩健設計之品質工程 黎正中教授

奈米電子元件 荊鳳德教授

固態物理 林聖迪教授

量子力學導論 李建平教授

永久地址：高雄市小港區松金街 59 號 Email：tanlong8888@hotmail.com m9711567@alab.ee.nctu.edu.tw