Chapter 1 Introduction
1.3 Thesis Organization
This thesis includes six chapters which focus on different temperature sensor design and its application such as: 3D-IC and DRAM refresh. The following briefly introduces the content of each chapter.
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Chapter 2 gives an overview of previous temperature sensors. It include conventional BJT based, analog CMOS, delay-based and frequency-based temperature sensor. Also, some of newest technique is introduced and compared.
Chapter 3 proposes 0.5V~0.25V process, voltage and temperature sensors for temperature measurement in the energy harvesting DVFS systems. It composes of process, voltage and temperature sensor. The process sensor and voltage (PV) sensor monitor the process variation and voltage variation continuously and give the variation information for temperature compensation. We will show simulation result and performance summary in the end of this chapter.
Chapter 4 presents a 0.4V fully integrated process invariant frequency-based temperature sensor. The effect of process variation is significantly reduced. We will show experimental result, chip photo and performance summary in the end of this chapter.
Chapter 5 demonstrates the heterogeneous 3D-IC architecture which contains CPU, SRAM, DRAM and analog circuits. To prevent hot spot on the intra layer and reduce DRAM refresh power, we proposed a refresh controller utilizing the process invariant temperature sensor.
Chapter 6 gives the conclusion of this thesis and future work.
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Chapter 2
Previous Works of Temperature Sensors
2.1 Introduction
Traditionally, the temperature sensors were constructed by proportional to absolute temperature (PTAT) and complimentary to absolute temperature (CTAT) sensors which were usually fabricated in bipolar processes. To be more compatible with standard CMOS technologies, the substrate bipolar transistor was used instead for thermal sensing [2.1]–[2.3]. For accuracy enhancement, the sensors needed extra analog -to-digital convertors (ADCs) which took up more chip area and consumed more power. Most high-accuracy and high-resolution temperature sensors are based on the temperature characteristic of parasitic bipolar transistors. The inaccuracy of state-of-art smart voltage-domain temperature sensors were only ±0.1˚C(3σ) [2.4],[2.5].
Their digital output resolution can be no less than 0.025˚C. Those were achieved by using dynamic element matching, a combination of correlated double-sampling and system-level chopping for offset cancellation, precision mismatch-elimination layout, and individual trimming at room temperature after packaging. However, all these analog techniques led to complex architecture, slow conversion rate, and large area/power overhead. It is hard to fit these voltage-domain temperature sensors within the form factor/ power-budget of a miniature microwatt system.
Time-to-Digital-Converter (TDC) is usually used to replace analog circuit. Its
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applications are gradually expanding such as a phase comparator of all-digital-PLL [2.6], [2.7], Temperature sensors circuit [2.8]-[2.10], jitter measurement [2.11], modulation circuit and demodulation circuit as well as a TDC-based ADC [2.12].
However, for a TDC, hundreds of inverters were required to obtain enough pulse delay to achieve sufficient temperature resolution. It has problems of occupying large area and consuming high power. The bottom line is that TDC is not suitable for near-threshold and sub-threshold, so we utilize frequency-to-digital converter (FDC) technology to make up temperature sensor and achieve small area and low power and operate at low voltage.
2.2 BJT Based Temperature Sensor
Most of all temperature sensors are using a technique by comparing the difference in the base–emitter voltage of two bipolar junction transistors (BJTs) at different current densities. The main objective of the temperature sensor is to generate Iref current and Iptat current, which are the inputs of the ADC. A simplified schematic of [2.13] that generates three currents, Iptat, Ictat , and Iref, is presented in Figure 2.1. Iptat current increases proportional to temperature and is generated by two n-p-n vertical BJTs with a 20:1 ratio. Ictat current decreases linearly with temperature and is generated by the base–emitter voltage Vbe of the BJT. The voltages across Rptat and Rctat have a temperature coefficient of about 0.3 mV/˚C and -2 mV/˚C, respectively. An Iref current, constant over temperature, can be generated by proper summation of Iptat and Ictat.
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Figure 2.1 Schematic of BJT based temperature sensor [2.13].
Figure 2.2 (a) shows a simplified circuit diagram for an ideal dual-slope integrating ADC. It consists of an integrator, a comparator, and switches for Iptat and Iref. An integrator consists of an integrating capacitor and a two stage opamp and a comparator is also the same circuit topology as a two-stage opamp without the phase compensation network for faster speed. Resolution of the ADC is 9 bits and bandwidth is 32K samples per second with a 32-μs thermometer cycle. One internal clock with an 8-ns period corresponds to 1゜ in this design.
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(a)
(b)
Figure 2.2 Dual-slope integrating ADC for (a) genetic design, (b) timing diagram [2.13].
During the initialization period, Iptat and Iref are disconnected from the integrator and VX is precharged to Vref with an assumption that VOS1 and VOS2 are zero. Vref is 1 V in this design but also assumed to VSS in Figure 2.2 for simple analysis and description.
The dual-slope ADC performs its conversion in two phases: integration phase and deintegration phase. During the integration phase, Iptat is connected to the integrator for fixed time T1 (4 μs) shown in Figure 2.2(b) and VX is charged up to a peak value that is proportional to Iptat and, hence, proportional to temperature. During the deintegration time, switching input from Iptat to Iref discharges VX with a constant slope set by Iref until VX falls below Vref. This deintegration interval T2 shown in Figure 2.2(b) depends on the current ratio of Iptat and Iref.
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[2.14],[2.15] presents a temperature sensor in a 32 nm high-k metal gate digital CMOS process for integration in a microprocessor core. The sensor uses a ratio of currents driven into a BJT pair with current chopping to up-convert the temperature signal. A second order sigma-delta 1-bit ADC is used to digitize the chopped signal, which is then down-converted and filtered in the digital domain to obtain a temperature measurement. The sensor operates from 10 to 110˚C, achieving a 3σ resolution of 0.45 C, and < 5˚C inaccuracy without calibration/trimming.
Pertijs et al. [2.5] proposed such a scheme by using a switched capacitor integrator that balances the charge ratio between and voltage generated by charge summing.
Figure 2.3 shows the block diagram of the temperature measurement system with a time-multiplexed BJT sense stage, a ADC, and a digital backend. The ratiometric measurement of the ΣΔADC, (VBE-VBE2) / (VBE+VBE2), is non-linear with temperature.
The raw ADC output is linearized to yield
BG In [2.5], the gain factor is implemented using a capacitor ratio and multiple clock cycles.
This increases the area of the first integrator.
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Figure 2.3 Schematic of the thermal sensing system [2.13].
Figure 2.4 shows the simplified schematic of the BJT sense stage. The top-row current sources feed currents in to a pair of matched BJTs to develop a differential voltage. The current ratio, m, between the BJTs results in a differential voltage. In practice, the BJT performance changes with current density. At low current density generation-recombination dominates the BJT behavior while at high current density high-injection dominates. A region of optimal current density (flat- β) is selected to ensure BJTs have comparable β at both current ratios. In this work, the bias current of a single current source is nominally 80 uA. The current is generated using constant-gm bias circuit that uses an nMOS transistor in linear region as a resistive reference.
Different current densities can be realized by current, or the BJT emitter area scaling, or both. In this work current scaling was selected as different emitter areas cannot be matched perfectly owing to interconnect-dominated mismatch as the mismatch is dominated by the interconnect. The effective emitter resistance in each BJT branch will
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be different due to differences in the routing resistance connecting the constituent BJT elements. Additionally, the variable resistance to each unit BJT produces a non-uniform current in that BJT leading to variations and errors. The use of equal area BJTs allow for a layout with symmetrical metal connections to ensure matched contact resistance.
The input current in each branch is swapped between the BJTs every 128 cycles so that differential output voltage is up-converted to the chopping frequency. The selection of the current sources to chop the currents to the BJTs is illustrated in Figure 2.5. The current ratio in the BJTs must be accurate for a measurement with low variations. Each individual current source must be matched so that an exact ratio can be obtained.
Careful attention to layout is necessary to eliminate systematic process induced mismatches; a common centroid layout of the unit transistors is used. A discussion of the random mismatch in a high-k metal gate CMOS process is presented. One way to improve the random mismatch is to use long channel length devices, but is area inefficient. Another way to improve matching is to use a dynamic element matching (DEM) between the current sources. A number of redundant current sources are used to generate the current ratio. In the current scheme NCS, discrete current sources are used to generate the current ratio. A digital controller combines the DEM selection with the chopping logic to connect the current sources to the BJT.
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Figure 2.4 Schematic of the front end sense stage with active cascode impedance enhancement, DEM and chopped currents in BJT pairs. Output VBE1 and VBE2 are
routed to the input ADC input MUX [2.13].
Figure 2.5 Illustration of the current chopping to up-convert the temperature signal to fchop [2.13].
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2.3 Analog CMOS Based Temperature Sensor
With the use of bipolar transistors for temperature sensing, and advanced techniques including chopping circuit, dynamic element matching and sigma-delta ADC for noise suppression and cancellation, Pertijs et al. [2.5] developed an on-chip temperature sensor with a 3σ inaccuracy of ±1˚C at the expense of increased circuit complexity. With the use of three CMOS transistors for temperature sensor was presented in [2.17]. The three-transistor temperature sensor shows in Figure 2.6, which utilizes the temperature characteristic of the threshold voltage, shows highly linear characteristics at a power supply voltage of 1.8 V. The conditions of this temperature sensor are defined as follows.
Figure 2.6 Conventional three-transistor temperature sensor [2.17].
1) All transistors operate in the saturation region.
2) The output voltages of each node are equal.
3) The sinking currents at each node are equal.
The temperature is obtained by measuring VOUT, where the two currents, IOUT1 and IOUT2, have the same value. When the substrate bias effect of the transistor M2 is
15 using (2.7). Finally, (2.9) is solved against VGS1 and we get
V T
16 also become constant. Therefore, the output voltage corresponds to the temperature coefficients of the transistor threshold voltages.
Figure 2.7 Conventional three-transistor temperature sensor [2.17].
Figure 2.7 shows the characteristics at 1.8V and 1V supply voltages, where the intersections of and correspond to the operating points of this sensor. This method shows highly linear characteristics at a power supply voltage of 1.8V or more, which enables us to define the operating conditions well above twice the threshold voltage.
But the linearity diminishes after scaling down the supply voltage to 1V using a 90-nm CMOS process. Because the temperature coefficient of the operating point‘s current at a 1V supply voltage is steeper than the coefficient at a 1.8V supply voltage, the operating point‘s current at high temperature becomes quite small and the output
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voltage goes into the sub-threshold region or the cutoff region.
To improve linearity at a 1V supply voltage, an accurate four-transistor temperature sensor was designed in [2.18], and developed for thermal testing and monitoring circuits in deep submicron technologies, which is shown in Figure 2.8. Note that to operate the additional transistor in the saturation region, an extra bias voltage VGS0‘ is required. Of course, the bias voltage generation circuit must not possess temperature dependency, and, in some cases, this circuit becomes larger than the temperature sensor itself.
Figure 2.8 Four-transistor, voltage output, temperature sensor [2.18].
In addition, the W/L ratio of the transistors M0‘ and M1‘ should be as small as possible so that the current IOUT1‘ remains small. However, the smaller W/L ratio requires a longer channel, so it occupies larger chip area. Consequently, there is a tradeoff between the current consumption and the chip area.
The IDS VGS characteristics and the operating conditions of both the proposed four-transistor sensor is the following:
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T I V
I V
VOUT DS T DS T
3
3 3 2
2 2 1
2 2
(2.13)
3 3 2
2 2
2IDS IDS can be assumed as a constant value. Thus, (2.13) shows that the output voltage is mainly proportional to the temperature characteristics of the threshold voltage (M2andM3).
The output current of four- transistor temperature sensor is more high linearity with high temperature than conventional three-transistor circuit shows in Figure 2.9.
Figure 2.9 Operating points of four-transistor temperature sensor [2.18].
2.4 Delay Based Temperature Sensors
2.4.1 Time-to-Digital Converter Based Temperature Sensors
The temperature sensor composed of temperature-to-pulse generator and cyclic time-to-digital converter, shows in Figure 2.10. Temperature-to-pulse generator, it can
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generate a pulse width is linear to temperature variation. A simple circuit utilizing gate delays to generate the thermally sensitive pulse is shown in Figure 2.11. The START signal is delayed a certain amount of time by the delay line composed of even number of inverter. The high-to-low and low-to-high propagation delay time for an inverter can be expressed as [2.19]
5 )
Figure 2.10 Block diagram of the time-to-digital temperature sensor [2.19].
Figure 2.11 Temperature-to-pulse generator [2.19].
Where kN NCOX(W/L)N , kP PCOX(W/L)P and CL are the trans -conductance parameters and effective load capacitance of the inverter. Note that we
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assume square-law behavior for the CMOS devices and thereby ignore the effects of velocity saturation. For an inverter with equivalent NMOS and PMOS, the propagation delay can be derived as
5 ) will both decrease. In the case of VDD much larger than VT, the thermal effect of the propagation delay will be dominated by the mobility. That is, the thermal coefficient of the propagation delay will become positive. The major problem of the simple temperature-to-pulse generator is that the width of the output pulse at the lower bound of the measurement range is usually much larger than zero. This will cause a large DC offset at the smart temperature sensor output. The second delay line with thermal compensation for temperature sensitivity reduction is inserted in the lower transmission path of the START signal to reduce the width offset of the output pulse, which is shown in Figure 2.12. The width offset of the output can be easily reduced by adjusting the number of delay cells in delay line 2.
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Figure 2.12 Width offset reduction accomplished by delay line 2 [2.19].
As shown in Figure 2.13, a simple thermal compensation circuit is used to reduce the sensitivity of the inverter in delay line2. The diode connected transistors P1, N1, and P3 serve as the core of the thermal compensation circuit. Since P1, P3, and N1 are all diode connected, they will operate in saturation if bias current is flowing. Thus, we have
Figure 2.13 Operating points of four-transistor temperature sensor [2.19].
) 1
( ) )(
2 ( 1
3 2
3
3 OX GSP T GSP
DP V V V
L C W
I
(2.19)By substituting (2.17) and (2.18) into (2.19), the equation becomes
22 observed for the difference between mask channel length and effective channel length.
The thermal sensitivity of channel length modulation term (1VGSP3)will be neglected in the following deviations since it is much smaller than those of mobility and threshold voltage over the temperature range we are interested.
To get the minimum thermal sensitivity, let 3 0
After simplification, we have
km
The sizes of transistors P1 and N1 are adjusted to make the gate-to-source voltage of P3 fit the requirement stated in (2.21) as closely as possible. The conduction current of transistor P3 can be found by substituting (2.21) back into (2.20) to yield
)
When
km 2
, the drain current will become totally thermal independent )Through the help of the current mirrors (P1, P2) and (N1, N2), the drain current of
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the inverter will be kept thermally insensitive as well, as will the propagation delay of delay line 2. This greatly reduces the design difficulty and enhances the tolerance to process variation.
For accuracy enhancement, a novel time-domain SAR smart temperature sensor suitable for curvature compensation is proposed in [2.20]. The corresponding architecture is shown in Figure 2.14 which evolves from the former time-domain digital thermostat [2.21]. A SAR control logic is added to speed up the set-point programming of the thermostat for adjusting the ARDL delay to approximate the TDDL delay. The final set-point value is defined as the output of the proposed sensor.
Figure 2.14 Implemented architecture of the proposed smart temperature sensor [2.21].
More specifically, the SAR control logic, ARDL and time comparator can be viewed as an equivalent time-to-digital converter to measure the TDDL delay for any temperature under test. The accuracy enhancement is accomplished mainly by a new
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technique called curvature compensation by which the curvature of ARDL temperature-to-time transfer curve is designed to compensate for TDDL curvature to substantially improve the sensor‘s linearity.
From (2.15),(2.16) and (2.17), (2.15) can be rewritten as
(2.23) where the constant β is almost temperature-independent. Although the unit reference delay of ARDL can be easily implemented as one reference clock period, or a part of it, to be theoretically temperature-insensitive, the curvature of the smart sensor output will inevitably resemble that of curve and the sensor accuracy will be seriously limited as predicted in Figure 2. 15(a). One feasible linearization technique for the smart sensor output is to compensate for the curvature of TDDL curve by that of ARDL curve, as revealed in Figure 2. 15(b).
Figure 2. 15 Sensor output linearity for (a) temperature-insensitive and (b) curvature -compensating ARDL cell delay [2.21].
To reduce the thermal sensitivity of the ARDL delay cell to make its delay as a unit time reference, the temperature compensation circuit adopted in the former
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time-domain sensor [2.19] is utilized likewise. However, the conventional temperature compensation circuit consumes continuous power. NMOS switch NS1 is added to shut down the quiescent current of the ARDL delay cell between measurements to reduce power consumption as shown in Figure 2.16 where the Stop signal is activated at the end of conversion. The other switch NS2 is inserted to match the source resistances of N1 and N2 for reducing current mirror error. To cut the delay line size and the conversion time in half, the ARDL delay cell can be theoretically implemented as a temperature-compensated NOT gate instead of a delay buffer [2.10]. In this case, however, the rise time and fall time of the NOT gate are not equal since the pull up current is usually not the same as the pull down current. This mismatch will cause additional errors between even and odd stages. Therefore, a thermally compensated buffer is used instead as the unit ARDL delay cell.
Figure 2.16 Modified temperature compensation circuit for the ARDL delay cell [2.21].
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2.4.2 Dual-DLL-Based All-Digital Temperature Sensor
With process scaling down continuously, PVT variation will be a big problem about Time-to-digital based temperature sensors. A new type DLL-based all-digital temperature sensor [2.22] was presented. It has two improvements. First, it removes the effect of process variation on inverter delays via calibration at one temperature point, thus, reducing high volume production cost. Second, we used two fine-precision DLLs, one to synthesize a set of temperature-independent delay references in a closed loop, the other as a TDC to compare temperature-dependent inverter delays to the references. The use of DLLs simplifies sensor operation and yields a high measurement bandwidth (5kS/s) at 7bit resolution, which could enable fast temperature tracking.
We execute calibration and delay normalization using the circuit of Figure 2.17. It contains an open-loop delay line, and a DLL that synthesizes temperature
We execute calibration and delay normalization using the circuit of Figure 2.17. It contains an open-loop delay line, and a DLL that synthesizes temperature