Chapter 3 0.5V~0.25V Process, Voltage and Temperature Sensors with Adaptive
3.4 Simulation Results
The proposed process, voltage and temperature sensors are implemented via TSMC general purpose 65-nm CMOS technology. The supply voltage is adaptive scaled from 0.25V to 0.5V. The temperature simulation error is -1.76°C ~+1.96°C for adaptive voltage range, as shown in Figure 3.18. The maximum error occurs when supply is 0.25V and 0.5V. The effective resolution is 0.15˚C /LSB at 50k samples/sec conversion rate. The minimum power consumption is about 2.3μW at 0.25V supply voltage. Table 3.1 lists the comparison of recent temperature sensors [3.8], [3.11], [3.13], [3.17]-[3.18] and proposed temperature sensor. The proposed temperature
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sensor has ultra-low DVS operation ability, high conversion rate and ultra-low power consumption. The temperature inaccuracy of proposed temperature sensor is sufficient for dynamic thermal management applications.
-2
Figure 3.18 Simulation error of proposed temperature sensor.
Table 3.1 Temperature sensor comparisons
Sensor Technology Sensor Type Supply(V) Power (μW)
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3.5 Summary
The frequency-based process, voltage and temperature sensors without any ADC are proposed for on-chip temperature measurement in the DVFS systems of energy harvesting. It composed of process, voltage and temperature sensor. The process sensor and voltage (PV) sensor monitor the process variation and voltage variation continuously and give the variation information for temperature compensation. The temperature sensor has six TSROs generating frequency proportional to the measurement temperature at suitable supply voltage, and converts the frequency into digital code. The sensor was designed in TSMC 65nm CMOS technology. It operate over an ultra-low supply voltage range from 0.25V~0.5V. The power consumption is 2.3μW at 0.25V supply voltage and 50k samples/sec conversion rate. The above characteristics make the proposed sensor special applicable for energy-harvesting miniature portable platform.
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Chapter 4
0.4V Fully Integrated Process Invariant Temperature Sensor
4.1 Introduction
This chapter describes an voltage fully integrated process invariant frequency-based temperature sensor. The proposed temperature sensor utilizes two temperature sensitive ring oscillators (TSROs) to build a temperature-to- frequency-ratio generator capable of operating at 0.4V supply voltage. One is operated in near-threshold region, named Near-TSRO, to generate a fixed pulse width forming the denominator. The other one is operated in sub-threshold region, named SB-TSRO, to provide the required frequency as the numerator. The ratio of the SB-TSRO frequency to the Near-TSRO frequency is implemented to be linearly increasing with the measured temperature. Because of the different MOSFETs near-/sub-threshold conduction current characteristics, the effect of process variation is significantly reduced by the proposed temperature sensor.
The rest of this chapter is organized as follows. The design concepts of ultra-low voltage process invariant temperature sensor will be discussed in section 4.2. The specific architecture of temperature sensor will be revealed in section 4.3. Simulation and experiment results will be given in section 4.4. Finally, section 4.5 would conclude this chapter.
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4.2 Design Concepts of Process Invariant Temperature
Sensor
Although the process sensor in previous chapter can sense the process corner information and compensate temperature sensor, the process variation standards is not fine enough. As shown in Figure 3.4, the digital output of temperature sensor still suffers from process variation. As the result, we have to sacrifice some function, adaptive voltage scaling, to let the design be simple.
In order to remove the effect of process variation, the CLK in Figure 3.4 is replaced by a near-threshold temperature sensitive ring oscillator (Near-TSRO) as shown in Figure 4.1. The frequency of the Near-TSRO is fo1. The S-bit counter is still triggered by the SB-TSRO with fo2 frequency. Hence, the output pulse width of fixed pulse width generator becomes 2N−1/ fo1. The corresponding digital output of S-bit counter will be 2N−1 fo2/ fo1.
Near-th.
TSRO
Sub-th.
TSRO START
fo1
fo2
2N-1fo2/fo1∝ Temp.
N-bit Counter D-FF
RESET
VDD D
C[N-1]
Q
W W=2N-1/fo1
S-bit Counter Fixed Pulse Width Generator
Figure 4.1 Block diagram of the proposed ultra-low voltage frequency-based temperature sensor with process variation immunity enhancement.
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There are two temperature sensitive ring oscillator (TSRO) in the proposed temperature-to-frequency-ratio generator with process variation immunity. One TSRO is operated in sub-threshold region, called SB-TSRO, and its frequency is proportional to the conduction current, ID_sb. The other TSRO is operated in near-threshold region, called Near-TSRO, and its frequency is also proportional to the conduction current
Based on (4.1), the digital output of S-bit counter can be represented by
near By substituting (3.2) and (3.3), the equation becomes
)
where Vth1 is device threshold voltage in Near-TSRO, and Vth2 is the device threshold voltage in SB-TSRO. Noted that the * ( )
67 There are two terms within the curly brackets of the numerator in (4.5). Similarly, the second term is temperature independent since the temperature effect of threshold voltage in (4.6) is cancelled with that of thermal voltage. The remaining terms of the numerator in (4.5) is proportional to T2. Meanwhile, the denominator of (4.5) is proportional to T based on (4.7). Therefore, the output of the proposed temperature sensor with enhanced process variation immunity becomes
I T
Equation (4.8) is only valid provided that fo2 is generated in sub-threshold region whereas fo1 is generated in near-threshold region. In order to ensure the SB-TSRO (fo2) and the Near-TSRO (fo1) operate in sub-threshold and near-threshold region, respectively, the design principles of the device threshold voltage within the two TSROs for the proposed temperature sensor with enhanced process variation immunity are range of the sensor respectively.
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On the other hand, the enhanced process variation immunity is achieved by the temperature-to-frequency-ratio structure. Some process parameters of ID_sb are cancelled with those of ID_near, including inversion layer mobility, gate oxide capacitance, effective channel width, and effective channel length. The simulation results of the proposed temperature sensor under process variation are shown in Figure 4.2. The effect of process variation is reduced significantly.
700 800 900 1000 1100 1200 1300
0 25 50 75 100
FF, 0.40V TT, 0.40V SS, 0.40V
Temperature
11-bit Digital Output
w/o Near-th TSRO
@ FF corner
w/o Near-th TSRO
@ SS corner
Figure 4.2 The effect of process variation on the proposed process invariant temperature sensor.
4.3 Specific Architecture of Process Invariant Temperature
Sensor
An ultra-low voltage process invariant frequency domain temperature sensor is implemented in TSMC 65nm bulk CMOS technology. The block diagram is shown in Figure 4.3. The SB-TSRO uses regular threshold voltage (RVT) CMOS. For the design convenience, the device effective length of the RVT CMOS is adjusted for having its
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threshold voltage equals to VDD at 125˚C satisfying (4.9). The clock of the fixed pulse width generator is provided by the Near-TSRO instead of system clock. The low threshold voltage (LVT) CMOS is adopted to construct the inverters within the Near-TSRO. The device effective length of the LVT CMOS is adjusted for having its threshold voltage identical to one half of VDD at -25˚C based on (4.10). In order to achieve sufficient temperature resolution, the Near-TSRO has 51 stages; while the SB-TSRO has 13 stages.
11-bit
Figure 4.3 The implementation of the proposed process invariant temperature sensor.
With 0.4V supply voltage, the proposed temperature sensor has two input signals, CLK and START. The CLK is provided from the system clock directly, and it is very flexible, and the only requirement of it is faster than 500kHz. That is sufficient for the control unit since the simulated maximum conversion rate of the proposed temperature sensor is 50kHz. The START triggers the sensor to perform on-chip temperature measurement. Each positive edge of the START can enable the measurement one time, and have the Q of the D flip-flop inserted. The Srst is then inserted one CLK cycle to reset 11-bit digital output counter, and RDY is reset to 0. Also, the PW then becomes 1
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to enable both the SB-TSRO and the Near-TSRO. The SB-TSRO is used for the clock signal of the 11-bit digital output counter; while the Near-TSRO is used for clock signal of the 10-bit counter. The 10-bit counter of the fixed pulse width generator continues counting until the most significant bit, Qmsb, is inserted. It will reset the D flip-flop to make the Q become 0. The control unit then resets PW to 0, and has Nrst inserted to reset the 10-bit fixed pulse width generator. Meanwhile, the RDY is inserted after several CLK periods to ensure the 11-bit digital output, TS, is ready. The TS equals to 512×
fo2/fo1, and it is proportional to temperature according to (4.8). The timing diagram of the proposed temperature sensor is shown in Figure 4.4.
START
TS RDY
PW Qmsb
SB-TSRO
512
Near-TSRO
fo1
Figure 4.4 The timing diagram of the proposed process invariant temperature sensor.
4.4 Simulation and Experimental Results
To verify effectiveness and capabilities of the proposed temperature sensor with enhanced process variation immunity, it was designed by full-custom EDA tools and fabricated in a TSMC general purpose 65-nm one-poly ten-metal (1P10M) CMOS process. Also, the impact of process/voltage variations on the proposed temperature sensor is evaluated in this section. The area of the proposed sensor core is only 55μm ×
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18μm without I/O pads as shown in Figure 4.6. The proposed process invariant temperature sensor is composed of a near-threshold ring oscillator, a sub-threshold ring oscillator, a fixed pulse width generator, counters, and a control unit. The double guard ring surround the near-threshold ring oscillator and sub-threshold ring oscillator to prevent other circuit from interference but increase area slightly. Figure 4.5(a) shows digital output TS[10:0] remains almost the same across corners in post-layout simulation. The measurement error over 0˚C~ 100˚C is within -2.8˚C~ +3.0˚C as shown in Figure 4.5(b), which demonstrates good process immunity for the proposed sensor. The effective resolutions for all test chips spread over 0.25˚C.
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Figure 4.5 (a) Digital output of sensor in post-layout simulation. (b) Simulated output error for 0˚C~100˚C.
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940μm
940μm
55μm
18μm
Fixed Pulse Width Generator
Near-th. RO
Sub-th. RO
Control Unit
Counters
Figure 4.6 Microphotograph of proposed process invariant temperature sensor
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The proposed sensor shared I/O pads with other designs within the 0.94mm × 0.94mm chip. For measuring convenience, we design PCB board as shown in Figure 4.7. Several regulator circuits are set for filter bouncing noise. Besides, there are a jumper and a switch for selection between DC-DC converter and temperature. The SMA terminal is utilized to receive START signal, because sample frequency is higher than normal condition.
Figure 4.7 PCB board design.
The measurement environment was set up as shown in Figure 4.8. Before measuring each test chip, the temperature of the programmable temperature and
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humidity chamber EZ040- 72001 was set to 0˚C first and one hour was waited for the chamber temperature to be stable. For 0˚C measurement, CLK signal was generated by pulse/function generator 8116A for the control unit of the test chip. Meanwhile, START signal was issued to reset the test chip and activate the proposed sensor conversion.
After the counters of the test chip complete one operation, RDY signal will be inserted by the control unit of the test chip. The 11-bit digital output TS signals were then recorded by logic analyzer 16900A. It is worth noticing that the test chips were not firmly packaged and the bare die could be seen as shown in Figure 4.9. Such setting can help stabilize the core temperature of the test chips during measurement. The measurement of the proposed sensor was done in 5˚C steps over 0˚C~100˚C temperature range. A 0.5˚C/min heating slope was set to increase chamber temperature smoothly. Each temperature measurement was recorded after holding desired temperature point for 10 minutes.
Test Chip
Digital Oscilloscope Function Generator
Pattern Generator
Programmable Power Supply
Logic Analyzer Temperature
Controller CLK
START
Programmable Temperature & Humidity
Chamber
VDD 4
RDY
TS 11
Figure 4.8 Measurement environment for the test chips.
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Figure 4.9 Bare die of the test chip on PCB board.
The supply voltage for the test chips is 0.4V. The measurement errors are -1.81˚C~+1.52˚C for 12 test chips after one-point calibration, as shown in Figure 4.10.
To ease chip realization, one-point calibration was fulfilled offline by linear curve fitting with the digital outputs of 80˚C. The corresponding 3σ inaccuracy is -2.79˚C~+2.78˚C. The average effective resolution of the test chips is measured to be 0.49˚C/LSB. The average power consumption is 520nW at 0.4V supply voltage and 45k samples/sec conversion rate. The measurement results of 12 test chips are shown in Figure 4.11 having an excellent linearity. Also, the ability of the proposed sensor suppressing the effect of process variation is demonstrated. To reveal the effect of voltage variation, the corresponding measurement errors are depicted in Figure 4.12 for 0.36V~0.44V (10% supply voltage variation). The inaccuracy of temperature measurement under voltage variation is within -6˚C~+8˚C.
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-4 -3 -2 -1 0 1 2 3 4
0 10 20 30 40 50 60 70 80 90 100 Temperature (°C)
Error (°C)
Figure 4.10 Measured error curves for 12 test chips.
700 800 900 1000 1100 1200 1300
0 25 50 75 100
Temperature
11-bit Digital Output
w/o Near-th TSRO
@ FF corner
w/o Near-th TSRO
@ SS corner
Figure 4.11 Measured result curves for 12 test chips.
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Figure 4.12 Measurement error curves for voltage variations.
In Table 4.1, the achieved performance of proposed ultra-low voltage process invariant frequency-domain temperature sensor is compared with recent temperature sensors. The ultra-low voltage operation ability of the proposed sensor achieves extreme low power consumption per conversion rate of only 11.6pJ/sample.
Table 4.1 Performance Comparison of Recent Temperature Sensors.
Sensor Technology Power Conv. Rate
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4.5 Summary
A process invariant frequency-domain temperature sensor has been presented to enable on-chip temperature measurement. The sensor was designed to achieve ultra-low voltage operation. It composed of two temperature sensitive ring oscillators (TSROs). One was operated in near-threshold region (Near-TSRO) for the clock source of the proposed fixed pulse width generator. The other one was operated in sub-threshold region (SB-TSRO) for the clock source of the digital output counter.
With a 2-input AND circuit, the digital output of the proposed temperature sensor was proportional to the ratio of the SB-TSRO frequency to the Near-TSRO frequency, fo2/fo1. According to the different conduction current in near- /sub-threshold region, the effect of process variation on the proposed sensor could be greatly suppressed.
Meanwhile, the relationship between temperature and fo2/fo1 was linearly positive related.
The realization in TSMC general purpose 65nm CMOS technology meets the target to be capable of 0.4V supply voltage operation over the temperature range of 0˚C to 100˚C. The area of the sensor core (without I/O pads) is only 990μm2. The power consumption per conversion rate is 11.6pJ/sample, which is a hundredfold improvement over previous work [4.4], [4.6]. All these characteristics make the proposed sensor special applicable for energy-limited miniature portable platforms.
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Chapter 5
Temperature-Aware DRAM Refresh Controller in TSV 3D-IC
5.1 Introduction
Though-silicon-via (TSV) has emerged as a promising solution in building 3D stacked devices. It is a technology where vertical interconnects formed through the wafer to enable communication among the stacked chips [5.1], [5.2]. There are also other wafer level processing technologies to form 3D structures including the single-crystal Si layer stacking method [5.3], [5.4]. TSV technology is believed to have the potential to open up many new horizons in the semiconductor industry in the near future. This is because it provides many benefits including high density, high band-width, low-power, and small form-factor [5.5], [5.6]. Also, as we near the limit of technology scaling, it is believed to be a promising solution to overcome the scaling limit.
Another possible application is ―logic+memory‖ combination, where a single or multiple memories are directly stacked on top of a logic chip [5.7], [5.8]. Here, the logic chip and the memory can communicate through thousands of IOs allowing high-bandwidth with low power. Also heterogeneous integration circuits and 3D logic chip applications are expected to emerge in the future. In the former application, TSVs
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are used to interconnect logic, memory, analog, RF sensor and MEMS chips among others. In the latter one, a logic chip itself such as CPU, can be built 3-dimensionally [5.9]. Figure 5.1 is a conceptual schematic of a hyper-integrated 3D-IC combined with a contemporary flip chip package and heat sink technology.
Figure 5.1 3D circuit architecture connected to a conventional heat removal device [5.16].
However, for multi-level 3D-IC, high level of integration introduces the problem of thermal and self-heating, which is the result of increased power density. Although the power consumption of a die within a 3D-IC is expected to decrease due to the shorter interconnects, the heat removing of a 3D-IC is much more difficult than that of a 2D-IC. The cause is that the ambient environment of the die of a 2D-IC is the cooling material, but the ambient environment of a die within a 3D-IC may be another die which also generates heat. Therefore, the thermal issue of a 3D-IC is much severer than that of a 2D-IC. This feature makes the circuits in 3D-IC must operate adaptively according to the thermal condition of each layer.
This chapter proposes a temperature-aware refresh controller of the dynamic random access memory (DRAM) in intra layer of 3D-ICs. Also, previous works of
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DRAM refresh mechanisms are discussed. To analyze the data retention time accurately, a 1Kb DRAM block is build up with TSMS 65nm CMOS process. Besides, a process invariant frequency-domain temperature sensor proposed in chapter 4 is utilized to measure DRAM block temperature and control the refresh frequency adaptively for DRAM thermal monitor and power consumption control.
The rest of this chapter is organized as follows. The thermal issues and solutions in 3D DRAM will be discussed in section 5.2. In section 5.3, System architecture of heterogeneous 3D Integration is build up. Next, temperature-aware refresh controller of DRAM layer in 3D-IC will be proposed in section 5.4. Simulation results of proposed architecture are given in section 5.5. Finally, section 5.6 concludes this chapter.
5.2 Thermal Issues and Solutions in 3D-IC and DRAM
Refresh
5.2.1 Thermal Issues in 3D-IC
To study the thermal impact of hot spot size and power density on 3D stack design, thermal finite element simulations were performed in [5.10]. Two simulation setups have been used. The fine grain simulation of [5.11] takes into account the complete back-end -of-line (BEOL) and layout structure whereas in the FEM simulation of [5.12]
simplified models are using volume-averaged material properties. These finite element simulations have been calibrated with a test structure that consists of heaters integrated
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with thermal sensors (diodes). Heaters with a size of 50×50 μm2 and 100×100μm2 are located in the metal 2 layer of the BEOL in the top tier of the 3D chip-stack, as well as in a 2D reference die. Both in the top and the bottom die of the stack, a set of five diodes at different distances from the hot spot centre are added are integrated below the heater.
This configuration of diodes allows capturing the local temperature peak due to the hot spot power dissipation. The simulation results and experimental validation [5.13]
(Figure 5.2) indicate that power dissipation in a 3D stacked structure approximately has a higher maximum temperature increase compared to the 2D reference case, requiring thermal-aware floor-planning to avoid thermal problems in the stack.
Figure 5.2 Temperature increase on the top die in a 3D chip-stack caused by a 100×100μm2 hot spot is approximately three times higher than the temperature increase
in a 2D SoC chip [5.10].
To implement the thermal-aware floor-planning in 3D stacks, a thermal compact model has been developed [5.14]. With this model, the temperature distribution is calculated in each die, using the power maps of the heat generation in each tier as input.
This compact model allows studying the thermal interaction of heat sources in the 3D stack, both on the same die as well as on other levels of the stack. Furthermore, the
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compact model allows thermal optimization of the placement of the heat sources as a function of the geometrical and material properties of the interface and interconnects structures. Figure 5.3 shows the graphical interface of this thermal compact model.
Figure 5.3 Graphical interface of the thermal compact model for 3D stacked structures [5.10].
5.2.2 The 3D-IC with Interlayer Cooling
In CMOSAIC [5.15], a multi-disciplinary team will jointly conduct experimental research, develop the necessary modeling tools, simulate 3D-IC stacks and test various prototype stacks to develop practical methods for heat removal in high performance
In CMOSAIC [5.15], a multi-disciplinary team will jointly conduct experimental research, develop the necessary modeling tools, simulate 3D-IC stacks and test various prototype stacks to develop practical methods for heat removal in high performance