Summary - Previous Works of Temperature Sensors

Chapter 2 Previous Works of Temperature Sensors

2.7 Summary

Figure 2.29 shows the fishbone diagram of temperature sensor patents (US patents). There are 2770 search results in term of temperature sensor, BJT based and analog CMOS based temperature sensors belonging to the majority. These two type temperature sensors utilize BJT bias and band-gap reference to sense temperature variation. TDC based and FDC based temperature sensors are in the minority, utilizing inverter chain and ring oscillator to generate time pulse and frequency linearly with temperature. Figure 2.30 and Table2.1 compare several temperature sensors in previous

(2.24)

section. As the conversion speed goes up, the more current is needed. Therefore the power consumption is compared with respect to the measurement bandwidth. The voltage and current based temperature sensors [2.4], [2.5], [2.14]-[2.16] have large power consumption per conversion rate and low area efficiency because they make use of ADCs. Power consumption per conversion rate of TDC based temperature sensors, [2.19]-[2.21], are lower than previous one, but the delay chain occupies large area.

[2.23] have less power consumption but smaller sensing range (-10˚C~30˚C) which is suitable for RFID. [2.24] has extreme low power because slow conversion rate, but it‘s effected significantly by process variation. While consuming the lowest power per conversion rate, the FDC based temperature sensor [2.25] shows moderate resolution.

Ring oscillator

1172 Voltage Based

Delay-locked loop

Temp.

Sensor 2770

Delay Based 109

Frequency Based 637

4 28

10 Delay pulse

generation

Band-gap reference

1022 Current Based

18 _Band-gap reference

Figure 2.29 The fishbone diagram of temperature sensors.

▲ Pertijs, JSSC, 2005 [2.5]

3.3V, ±0.1°C, 0~100°C, 0.01°C

▲ Aita, ISSCC, 2009 [2.4]

3.3V, ±0.1°C, -55~125°C, 0.025°C

▲ Vroonhoven, ISSCC, 2008 [2.16]

5V, ±0.05°C, -55~125°C, 0.025°C

▲ Chen, JSSC, 2005 [2.19]

3.3V, -0.7~+0.9°C, 0~100°C, 0.16°C

▲ Chen, JSSC, 2010 [2.21]

3.3V, -0.25~+0.35°C, 0~90°C, 0.092°C

▲ Woo, ISSCC, 2009 [2.22]

1.2V, -1.8~+2.3°C, 0~100°C, 0.66°C

▲ Kim, CICC, 2009 [2.25]

1.2V, -2.9~+2.75°C, -40~110°C, 0.043°C

▲ Li, ISSCC, 2009 [2.14]

1.05V, ±5°C, -10~110°C, 0.45°C

* Supply, Inaccuracy, Range, Resolution 1E-5

Power Consumption per Conversion Rate (μW/samples/sec) 10²

32nm 65nm 0.13μm 0.35μm 0.7μm Technology Node (μm)

Figure 2.30 Comparison of temperature sensors.

Table 2.1 Comparison of each type temperature sensors.

Type Paper Advantage Disadvantage

BJT Based

[2.5],[2.14]

-[2.16]

High resolution and small inaccuracy.

Large area and large power.

Can‘t be operated in low voltage. supply voltage and power than BJT-based

Need additional ADC and bias circuits.

Large area of delay line. Can‘t be operated in low voltage.

Leakage Based

[2.24] Small power and area. Low conversion rate.

Additional log counter is required. Can‘t be operated in low voltage.

Frequency Based

[2.25] High conversion rate. Worse inaccuracy.

Chapter 3 0.5V~0.25V Process, Voltage and Temperature Sensors with Adaptive Voltage Selection

The 0.5V~0.25V process, voltage and temperature (PVT) sensors with adaptive voltage selection are proposed for temperature measurement in the energy harvesting dynamic voltage and frequency scaling (DVFS) systems. It composes of process, voltage and temperature sensor. The process sensor and voltage (PV) sensor monitor the process variation and voltage variation continuously and give the variation information for temperature compensation. The temperature sensor has six TSROs generating frequency proportional to the measurement temperature at suitable supply voltage, and converts the frequency into digital code. The sensor was designed in TSMC 65nm CMOS technology. The sensor operate over an ultra-low voltage range from 0.25V~0.5V and have 2.3μW power consumption, 0.15˚C resolution and 50k samples/sec conversion rate.

3.1 Introduction

In recent years, numerous portable electronic products have been launched to the market with considerable market growth. Energy efficiency of electronic circuits is a critical concern in every application. Lowering the supply voltage and frequency is one

of the attractive approaches to reduce power consumption. Furthermore, dynamic voltage and frequency scaling (DVFS) system achieves extremely efficient energy saving by adjusting system supply voltage and frequency depending on workload monitor [3.1]. As we continue to reduce the supply voltage to ultra-low voltage that the transistor reach the near/sub-threshold regions, circuits would become more sensitive to process, voltage and temperature (PVT) variations than super threshold [3.2]-[3.4].

Figure 3.1 The DVFS system of energy harvesting.

With process scaling down continuously, the high level of integration also introduces the problem of self-heating, which is the result of increased power density.

The environmental variations are so large that variation-aware near-/sub-threshold circuit design is necessary to prevent functional failure [3.5]. Besides, the energy harvesting systems, which power source include solar, RF and thermo, have critical factor of power efficiency [3.6]-[3.7]. As the result, the power consumption of temperature sensors should be as low as possible to be applicable to the DVFS systems of energy harvesting. As shown in Figure 3.1, the system is constructed by several

DVFS domains, DC-DC converter and DVFS controller.

Traditionally, the temperature sensors were constructed by proportional to absolute temperature (PTAT) and complimentary to absolute temperature (CTAT) sensors which were usually fabricated in bipolar processes. To be more compatible with standard CMOS technologies, the substrate bipolar transistor was used instead for thermal sensing [3.8]–[3.9]. These sensors needed extra analog-to-digital convertors (ADCs) which took up more chip area and consumed more power. However, these analog techniques led to complex architecture, slow conversion rate, and large area and power overhead. Therefore, the delay-based temperature sensors is proposed recently to replace analog circuits and the time-to-digital-converter (TDC) is utilized in [3.10]-[3.11]. But, a TDC requires hundreds of inverters to obtain enough pulse delay to achieve sufficient temperature resolution. It has problems of occupying large area and consuming high power.

The rest of this chapter is organized as follows. The design principle of temperature sensor in ultra-low voltage will be discussed in section 3.2. A novel architecture of 0.5V~0.25V PVT sensors with adaptive voltage selection will be proposed in section 3.3. Simulation results of proposed sensor will be given in section 3.4. Finally, section 3.5 concludes this chapter.

3.2 Design Principles in Ultra-Low Voltage

3.2.1 Challenges of Temperature Sensor in Ultra-Low

Voltage

A temperature-to-delay-difference generator [3.10] was designed to produce an output pulse with a width as linearly proportional to the measured temperature. As shown in Figure 3.2(a), the START signal went through two different delay lines. One was temperature sensitive, and the other was temperature insensitive. The difference of propagation delay between those two delay lines, Td1 － Td2, was generated by the XOR gate to form temperature-dependent output pulse width. The temperature insensitive delay line (TIDL) was inserted to avoid large DC offset. However, the characteristics of temperature sensitive delay line (TSDL) become distinct as the supply voltage scaling down. There are three operation regions of the MOSFETs, including super-, near-, and sub-threshold region. The corresponding current equations are listed as follows.

Super-threshold region: (V_GS >> V_th)

)

Figure 3.2(a) Temperature-to-delay-difference generator.(b) Temperature-to-frequency-difference generator.

where Vth denotes threshold voltage and μ^* denotes the effective channel mobility. The thermal voltage is represented by U_T. Considering the transistor figure of merit for temperature sensing, the temperature coefficient of current (TCC) [3.12] was used. For a long channel transistor, the TCC in the super-threshold region of operation based on (3.1) is given by

The relative change of TCCsp is a negative few thousandths per degree because the

negative mobility sensitivity dominates. In sub-threshold region, the TCC based on (3.3) (assuming VDS is much larger than UT ) is given by voltage sensitivity dominates in sub-threshold region due to the exponential dependence upon it. As the transistor goes deeper into weaker inversion, yield TCCsb of 6% per degree and more. Based on (3.4) and (3.5), the relationship of the TSDL propagation delay versus temperature in super-/sub-threshold region is shown in Figure 3.3. The TSDL propagation delay in super-threshold region increases with temperature whereas that in sub-threshold region decreases with temperature. However, the linearity of the TSDL propagation delay in sub-threshold region is much worse as shown in Figure 3.3. Therefore, the characteristic of the TSDL in sub-threshold region is not suitable for ultra-low voltage temperature measurement.

0.1

Normalized Propagation Delay of TSDL

Temperature

Figure 3.3 The linearity of temperature sensitive delay line (TSDL) in super-threshold, near-threshold and sub-threshold region.

On the other hand, the TIDL in [3.10] was also hard to implement when the supply

voltage is lower to near-/sub- threshold region. The design principle of TIDL was setting I_D/T 0 to yield the thermal independent conduction current. The first challenge is that the conduction current equation in super-threshold region is very different from that in sub-threshold region, especially the power of Vth term. The second one is that the relative change of TCC in sub-threshold region is several positive hundredths per degree while the relative change of TCC in super-threshold region is a negative few thousandths per degree. The third one is that the conduction current equation of sub-threshold region shown in (3.3) is affected by the thermal voltage to the power of 2, U . _T²

In [3.13], a temperature-to-frequency-difference generator was designed to have the temperature sensitive ring oscillator (TSRO) to be the clock source for up-counting, and the temperature insensitive ring oscillator (TIRO) to be the clock source for down-counting. With the same counting period, the output of the up-down counter was equal to the frequency difference of the two oscillators, f_o₁ f_o₂, as shown in Figure

3.2(b). The counter output, f_o₁ f_o₂, was designed to be linearly proportional to the measured temperature. It adopted a modified TIRO to solve the voltage head room problem. However, the implementation of the TIRO was still based on setting

0 / 

I_D T to acquire the minimum thermal sensitivity. Adopting the TIRO in ultra-low voltage region encounters the same difficulty as the TIDL in [3.10]. To carry out temperature measurement in ultra low voltage, the frequency-based technique is adopted.

3.2.2 Ultra-Low Voltage Frequency-Based Temperature

Sensor

A frequency-based temperature sensor is shown in Figure 3.4(a) for ultra-low voltage temperature measurement. It composes of a sub-threshold temperature sensitive ring oscillator (SB-TSRO), a 2-input AND, a counter and a fixed pulse generator. The proposed sensor is designed to have the frequency ratio between the SB-TSRO and CLK of the fixed pulse width generator proportional to the test temperature. Thus, the proposed temperature sensor can be regarded as a temperature-to-frequency-ratio generator. Once EN signal is inserted, the fixed pulse generator will generate an N cycles pulse, W. The SB-TSRO is designed to generate a frequency, fSB_TSRO, linearly proportional to the measured temperature. Using the 2-input AND, the clock output of the SB-TSRO can only trigger the counter within the pulse period, W. Therefore, the digital output of S-bit counter is equal to N fSB_TSRO / f_CLK.

Counter

Fixed pulse

generator

CLK

f_{SB_TSRO} fCLK

N/fCLK

Nf_{SB_TSRO} f_CLK

Sub-th. TSRO

IN OUT

(a) (b)

Figure 3.4 (a) Ultra-low voltage frequency-based temperature sensor. (b)Inverter used in SB-TSRO.

One of the key components of the proposed sensor is the SB-TSRO. It should produce an output clock with frequency as linearly proportional to the measured temperature as possible. The inverter with enable function used in proposed SB-TSRO is shown in Figure 3.4(b).The frequency of SB-TSRO constructed by the inverters is proportional to the conduction current since f = I_D/ (VDD × C_eq).

Noted that supply voltage, VDD, and equivalent capacitor of an inverter, Ceq, are assumed to be temperature independent. The inversion layer effective mobility depends on temperature according to [3.14]

By substituting (3.7) and (3.8) into (3.3), the equation becomes

   

Using Taylor series expansion for exponential function, the equation becomes

   

 .It‘s temperature independent.

Normalized Frequency of SB-TSRO

(a) (b)

Figure 3.5 (a) The relationship between temperature and threshold voltage. (b) The relationship of SB-TSRO output frequency versus temperature.

There are two terms within the curly brackets of (3.11). The second term is related to threshold voltage, Vth, and thermal voltage, UT . Based on [3.15], the Vth can be expressed as

 

T V

 

T₀ (T T₀)

V_th  _th   , (3.12)

where α is a negative coefficient. It represents the threshold voltage decreases as the temperature goes high as shown in Figure 3.5(a). Thus, the second term within the curly brackets of (3.11) is temperature independent since the temperature effect of threshold voltage is cancelled with T of thermal voltage. Finally, the temperature effect of conduction current depends on the term, KT²^^a. When a equals to -1, the conduction

current will become linearly proportional to temperature. It also means the frequency of SB-TSRO is proportional to temperature based on (3.6). In order to ensure proposed SB-TSRO operates in sub-threshold region, the design principle of the proposed SB-TSRO threshold voltage is

 

_DD

th T V

V  when T T_MAX (3.13)

where the supply voltage, V_DD, is equal to V_GS. The T_MAX represents the maximum temperature operation range of the sensor.

Based on (3.13), the threshold voltage of SB-TSRO MOSFETs at 125˚C is implemented to be VDD for the design convenience. The relationship of SB-TSRO output frequency versus temperature is a strictly increasing linear function as shown in Figure 3.5(b).

3.3 PVT Sensors with Adaptive Voltage Selection

To perform dynamic thermo management in the DVFS system in Figure 3.1, the supply voltage and process variation must be considered besides temperature. The adaptive voltage selection range is from 250mV to 500mV, so a voltage sensor is utilized to monitor voltage variation. Because the process variation is extremely significant in the ultra-low voltage, a process sensor is required as well. Therefore, the process and voltage (PV) sensor is utilized to compensate temperature sensor as shown in Figure 3.6. The whole circuit can be simply divided into six blocks, including finite state machine (FSM), PV sensor, temperature sensor, process register, voltage mapping table and PV compensation. The FSM send EN_ZTC and EN_TSRO to enable PV sensor and temperature sensor respectively. The PV sensor measure process and

voltage information and send it to process register and voltage mapping table.

According to signal of process register, P[4:0] , the voltage mapping table decides current voltage condition and send V[2:0] to temperature sensor. The temperature sensor measure current temperature and send temperature information, T[11:0], to PV compensation block. The PV compensation block compensate T[11:0] with P[4:0] and V[2:0] to cancel the variation of voltage and process variation.

V[2:0]

Process Register

PV[8:0]

PV[8:4]

Process & Voltage Sensor

Temperature Sensor

Voltage Mapping

FSM

RESET EN

CLK P[4:0]

EN_ZTC

T[11:0]

EN_TSRO

PV-compensation

T_OUT[12:0]

Figure 3.6 Architecture of proposed sensor.

3.3.1 Finite State Machine

The state diagram and signal waveform of FSM is shown in Figure 3.7 and Figure 3.8 respectively. The implement circuit of FSM, as shown in Figure 3.9, can be operated in 250mV to 500mV supply voltage. In the beginning the RESET signal is pulled up, FSM is initialized. Later, when RESET signal is set to low level the sensor start sensing process condition for one CLK cycle time. After sensing process condition, P_done signal is pulled up to alert the process register to stall the process value. Then, the sensor is idle until EN signal is alerted to monitor voltage and temperature. At the first cycle, the FSM reset counters of PV sensor and temperature sensor by the reset

signal RESET_CTR. Then, the PV sensor is enabled by EN_ZTC to sense voltage condition at the second cycle. Next, voltage mapping table decide current voltage range according to voltage condition sensed in the previous cycle and value in the process register. After knowing current voltage is within which range, the temperature sensor measure temperature for four cycles. Finally, PV compensation block calculate the temperature value according to value in the process register and voltage information. If EN is still high, FSM would back to first state. Otherwise, FSM will back to idle state.

Reset Counter

IDLE RESET=1

Reset FSM

Process Sensing

RESET=0

Voltage Sensing

Voltage Mapping

Temp.

Sensing PV

Comp.

EN=1

EN=0

4 cycles

Figure 3.7 State diagram of FSM.

EN RESET

CLK

EN_ZTC

EN_TSRO P_done RESET_CTR

Figure 3.8 Signal waveform diagram of FSM.

CLK

3-bit Counter

reset

D Q D Q

RESET

EN_ZTC

EN_TSRO

RESET EN

P_done

Q1 RESET_CTR

Figure 3.9 Implement circuit of FSM.

3.3.2 Process and Voltage Sensor

The current of transistor vary with temperature, process, and voltage. Mutual compensation of mobility and threshold voltage temperature variations may result in a zero temperature coefficient (ZTC) bias point of a MOS transistor. In TSMC 65nm bulk CMOS technology, the ZTC points of NMOS and PMOS are at about 0.4V and 0.6V respectively, as shown in Figure 3.10. According to simulation results, the delay of unit inverter will not change with temperature variation at 0.5V. Because at 0.5V supply voltage, NMOS drain current decreases with temperature, PMOS drain current increases with temperature. The PMOS and NMOS mutual current compensation leads to the output frequency of ring oscillator is constant with temperature variation.

Figure 3.10 ZTC point simulation of NMOS and PMOS.

The ZTC ring oscillator is the major component of PV sensor, as shown in Figure 3.11. The inverter utilized in ZTC ring and the circuits in Figure 3.4(b) are the same structure but different size. The low threshold voltage (LVT) CMOS is adopted to construct the inverters and nand gate. The weight / length ratio of transistors are 120nm/300nm. When the FSM turn to process or voltage sensing state, the EN_ZTC signal enable the 31 stages ZTC ring oscillator and the 9-bit counter is triggered by the oscillator. Therefore, the digital output of counter is also temperature invariant and only effected by process variation. In this work, we don‘t require too high digital output resolution, so we only utilize PV [8:4] for process measurement. The simulation results are shown in Figure 3.12, the digital output vary with process variation. When process corner is located at SS, TT and FF, the digital output is 7, 11 and 16 respectively. The digital output is not effected significantly by temperature.

EN_ZTC

9-bit Counter

reset

RESET_CTR PV[8:0]

31 stages ZTC ring osc.

Figure 3.11 Implement circuit of PV sensor.

Moreover, the PV sensor can be utilized to sense supply voltage condition when supply voltage is dynamic scaling, because the frequency of ZTC ring oscillator is also voltage dependent. When EN_ZTC pulse period is fixed, the digital output is proportional to voltage but lightly affected by temperature, as shown in Figure 3.12 (b).

However, the voltage sensing (VS) digital output is still affected by process variation, so we compensate digital output according to process information stored in process register by the circuits in right part of Figure 3.13(a). The multiplexer choose compensating value according to P[4:0] and add it to PV[8:0] as shown in left part of Figure 3.13(a). The mapping table convert compensated value to simplified digital output, V[2:0], for temperature sensor. The relationship of digital output and supply voltage is shown in Figure 3.13 (c).

Figure 3.12 (a) The relationship between digital output and process variation.(b) The Monte Carlo simulation.

Figure 3.13 (a) Compensation circuits and mapping table of voltage sensor. (b) Voltage sensor digital output under variation. (c) Digital output after process compensation.

3.3.3 Temperature Sensor

The temperature sensor is composed of six TSROs, a 12-bit counter, multiplexers and a decoder, as shown in Figure 3.14. TSROs are controlled by EN05, EN045, EN04, EN035, EN03 and EN025 and only operated when EN_TSRO is high. After voltage mapping state, V[2:0] signal is sent to decoder and multiplexer to choose suitable TSRO for current voltage. Based on (3.13), the threshold voltage of TSRO must equal

to supply voltage at the maximum temperature operation range. Therefore, TSROs with different threshold voltage are designed for different supply voltage (i.e., 250mV to 500mV). The threshold voltage behavior can be adjusted by using multi-threshold CMOS (MTCMOS) setting and increasing the effective channel length to adjust MOSFETs threshold voltage [3.16]. Besides, the stage number of each TSRO is arranged to let digital output slope ratio be the same for resolution improvement. The simulation results of temperature sensor can be roughly separated into 3 parts, FF, TT and SS corner, as shown in Figure 3.15. For each corner, digital output slopes of different TSROs is roughly identical for convenience of compensation.

Temperature Sensitive Ring Oscillators (TSROs) L=60n HVT 31 stage

EN04

EN035

EN03

EN025 EN045

L=85n HVT 15 stage L=90n RVT 19 stage L=190n RVT 7 stage L=120n LVT 11 stage

L=250n LVT 5 stage

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