Chapter 5 Temperature-Aware DRAM Refresh Controller in TSV 3D-IC
5.4 Temperature-Aware Refresh Controller of DRAM Layer
5.4.2 Proposed Refresh Control Scheme
In order to achieve small self-refresh current, DRAM required on-chip thermometer with self-refresh scheme. When a thermometer is implemented in a memory chip, many factors should be considered, including number, location, accuracy, area, and power consumption. Among the factors, the number, location, area penalty, and power consumption of the thermometer are the main items restricting the usage of the thermometer in memory chips. The number and location of thermometer are especially important factors for the chips with high power consumption. Moreover, timing control is important to refresh DRAM cells in the right time, so refresh period generator is required. On-chip, low power and small area temperature sensor is required for DRAM thermal monitor and power consumption control.
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As shown in Figure 5.16(a), the DRAM array is separated to several sub-blocks which share temperature sensor with near blocks. The temperature sensors are located on the corner position of each sub-block, as shown in Figure 5.16(b). Therefore, we can use least temperature sensor to monitor largest DRAM array region effectively.
On the other hand, the VRM composed of voltage regulator and DC-DC converter provides various voltages in this layer. The higher supply voltage (VDD) is in the range of 1.5V to 1.2V and provided from regulator. The lower supply voltage (VDDL) is in the range of 1.2V to 0.4V and provided from DC-DC converter.
The temperature sensor is placed in the scheme to monitor the sub-block temperature. After temperature sensor measuring the temperature information, it sends the temperature information to temperature mapping table. Because the temperature senor we proposed is operated in VDDL (0.4V) the level shifter is necessary to shift voltage level to DRAM operating voltage, VDD (1.2V). The mapping table would convert digital output of temperature sensor into Ctrl [1:0] signal to control the refresh CLK generator. The refresh CLK generator divides CLKIN into various slower frequencies according to Ctrl [1:0] and send divided clock signal to refresh counter as shown in Table 5.1. The refresh counter output control row decoder to choose which row should be refreshed. One word line refresh one time every 128 CLKREF periods.
Table 5.1 The relation between control signal and refresh frequency Temperature(˚C) Ctrl [1:0] CLKREF (MHz)
100-75 11 20
75-50 10 10
50-25 01 5
25-0 00 2.5
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Figure 5.16 (a) The DRAM layer in 3D-IC. (b) The refresh controller of DRAM sub-block.
The refresh CLK generator shown in Figure 5.17(a) is able to divide the frequency to 2, 4 or 8, according to how many flip-flops are in the loop. For example, when Ctrl [1:0] is equal to 10, the clock loop will propagate through only one flip-flop, thus the output frequency is the division of CLKIN by 2. Table 5.1 lists the relation between Ctrl [1:0] and CLKREF frequency. The 20MHz CLKIN frequency is provided by a stable
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temperature-independent clock source. In each CLKREF period, the sense amplifier controller shown in Figure 5.17 (b) sends the signals, SAN, SAP and PRE to control the sense amplifier. The SAN signal swing between ground and VDD/2, and SAP signal swing between VDD/2 and VDD. The delay line made of inverter chain is utilized to control refresh timing and let sense amplifier operate normal and prevent cell data corruption.
D Q D Q D Q D Q 1
0 0
1 0
1
Ctrl[0]
Ctrl[1]
Ctrl[1]
Ctrl[0]
Ctrl[1]
CLKIN
CLKREF
△T △T
△T
SAN
SAP
CLKREF PRE
(a)
(b)
VDD VDD/2
VDD/2
Figure 5.17 (a) Refresh CLK generator. (b) The sense amplifier control circuit.
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5.4.3 Simulation Results
The proposed temperature-aware refresh controller of DRAM layer in 3D-IC is implemented in TSMC 65nm 1P9M CMOS technology. In order to verify the proposed design, we carry out the implementation of a 1-Kb DRAM block. For convenience, 1Kb block is utilized to analyze the standby power of 2Mb DRAM in third layer. The operation waveform of sub-block system is shown as Figure 5.18. The VSN00, VSN10 andVSN20 are the storage node voltage in first bit cell on WL0, WL1 and WL2 respectively.
CLKIN
CLKREF
Row[6:0]
PRE SAN SAP WL0
WL1
WL2
VSN00
VSN00
VSN10
VSN10
VSN20
VSN20
Figure 5.18 The operation waveform of sub-block system.
Figure 5.19 shows standby power analysis at 25˚C, 50˚C, 75˚C and 100˚C. The standby power is dominated by 2Mb array and increase with temperature. Also, the power overhead, including temperature sensor, mapping table, sense amplifier
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controller and refresh clock generator is not significant. The power overhead is about 26 % at 25˚C and 15.39% at 100˚C.
0 0.2 0.4 0.6 0.8 1 1.2
25 50 75 100
P o w e r( m W )
Temperature(℃)
Array Mapping CLK+Ctrl TS+LS
Figure 5.19 Standby power analysis of 2Mb DRAM.
The power reduction is shown in Figure 5.20. The line without controller adopted the refresh period based on data retention time at 100˚C. The other line utilized proposed refresh control scheme with variable refresh period achieve up to 67.67%
standby power reduction compared with without controller one. Therefore, the proposed temperature-aware DRAM refresh controller reduces standby power significantly.
107 0%
20%
40%
60%
80%
20 40 60 80 100
Power reduction percentage(%)
Temperature(℃)
W/ Controller W/o Controller
67.67%
Figure 5.20 Standby power reduction of 2Mb DRAM.
5.5 Summary
This chapter presents and discusses thermal issues on 3D-IC and some solution at first. Also some conventional DRAM refresh approaches are discussed. Next, the heterogeneous architecture which contains CPU, SRAM, DRAM and analog circuits is presented. To prevent hot spot on the intra layer and reduce DRAM refresh power, we proposed a refresh controller utilizing the process invariant temperature sensor of chapter 4. Thanks for tiny power consumption of temperature sensor, the controller reduces standby power significantly, 67.67% without much power overhead.
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Chapter 6
Conclusions and Future Work
6.1 Conclusions
The advanced CMOS process makes it possible to integrate many designs into a single chip. As a result, certain areas of the chip involving high switching activities can generate a localized high-temperature area called a ―hotspot.‖ Furthermore, in system-in-a-package design with 3D integrated-circuit technology or stack dies, the situation will become worse than before. In this thesis, we focus on temperature sensor design to solve hotspot and thermal issue in 3D integrated-circuit technology.
Also, to achieve ultra low power we proposed two type of temperature sensor which can be operated at ultra low voltage, including 0.5V~0.25V PVT sensors with adaptive voltage selection and 0.4V fully integrated process invariant temperature sensor.
The 0.5V~0.25V PVT sensors with adaptive voltage selection composes of process, voltage and temperature sensor. The process and voltage (PV) sensor monitor the process and voltage variation continuously and give the variation information for temperature auto-compensation. It operate over an ultra-low supply voltage range from 0.25V~0.5V. The power consumption is 2.3μW at 0.25V supply voltage and 50k samples/sec conversion rate. The above characteristics make the proposed sensor special applicable for energy-harvesting miniature portable platform.
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Next, the ultra-low voltage fully integrated process invariant frequency-based temperature sensor is proposed. The effect of process variation is significantly reduced.
The realization meets the target to be capable of 0.4V supply voltage operation over the temperature range of 0˚C to 100˚C. The area of the sensor core (without I/O pads) is only 990μm2. The power consumption per conversion rate is 11.6μJ/sample. The high area/energy efficiency characteristics make the proposed sensor applicable for energy-limited miniature portable platforms.
Finally, the heterogeneous 3D integration which contains CPU, SRAM, DRAM and analog circuits is presented. To prevent hot spot on the intra layer and reduce DRAM refresh power, we proposed a refresh controller utilizing the process invariant temperature sensor. Thanks for tiny power consumption of temperature sensor, the controller reduces standby power significantly, 67.67% without much power overhead.
6.2 Future Work
Wireless medical micro-sensors are usually with two different operating modes:
Low-Power Mode and Performance Mode because the well-known signals of the
main characteristics of cardiac activity. More than 99% operating time of sensor nodes are operating in low-power mode to record various physiological signals throughout its life time while only less than 1% operating time in performance mode to process and transmit real-time informative cardiovascular parameters to a host.
This low-power-mode-dominated scenario is capable of further reducing total energy consumption if dynamic voltage frequency scaling (DVFS) technique is applied. The benefit of DVFS technique is attributed to the quadratic savings in active CVDD2
f
110
power.
The proposed 0.5V~0.25V PVT sensors can be used for DVFS system operated in sub/near-threshold region. Figure 6.1 shows the sub/near-threshold DVFS system, it is composed of two switched-capacitor (SC) DC-DC converters, decoupling capacitors (DeCaps), the proposed clock generator, level shifters (LS), DVFS controller, PVT sensors, supply switch, and near/sub-threshold 8T SRAM-based FIFO.
The PVT sensors are used to measure environment process, voltage and temperature variation information. This information will be utilized by DVFS controller to switch supply voltage and scale operating frequency.
VddH
Figure 6.1 Sub/near-threshold DVFS system.
The process invariant temperature sensor can be utilized to monitor temperature variation in 3D IC. The process invariant property would make it special suitable to sense temperature in different layer without much inaccuracy. The conceptual image of heterogeneous 3D integration is shown in Figure 6.2. Based on discussion in section 5.2.2, the thermal issue is taken into account. Microchannel cooling elements
111
are set between face of each chip to remove the heat dissipated locally by each chip.
The cold fluid is injected into microchannel and heat of chips is taken away by hot fluid. If there is some approach to control the fluid strength with the proposed temperature sensor, we can make temperature in the 3D-ICs as stable as possible. In this way, the power consumption of system would be reduced significantly.
Cold Fluid
Hot Fluid
TSV & Bonding Front-End Circuit
DRAM
L2 Cache
Multi-Core + L1 Cache
Figure 6.2 Conceptual image of heterogeneous 3D integration with interlayer cooling.
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[4.1] A. L. Aita, M. A. P. Pertijs, and K. A. A. Makinwa, ―A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ±0.25˚C (3_) from -70_C to 130_C,‖ in IEEE International Solid-State Circuits Conf. , pp. 342–343, 343a.,Feb. 2009,
[4.2] M. A. P. Pertijs, K. A. A. Makinwa, and J. H. Huijsing, ―A CMOS smart temperature sensor with a 3_ inaccuracy of ±0.1˚C from -55˚C to 125˚C,‖ IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2805–2815, Dec. 2005.
[4.3] P. Chen, C. C. Chen; C. C. Tsai, W. F. Lu, ―A Time-to-Digital-Converter-Based CMOS Smart Temperature Sensor,‖ in IEEE J. Solid-State Circuits, vol. 40, no. 8, PP1642-1648, August 2005.
[4.4] P. Chen, C. C. Chen, Y. H. Peng, K. M. Wang, Y. S. Wang , "A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of −0.4°C ∼ +0.6°C Over a 0°C to 90°C Range," in IEEE Journal of Solid-State Circuits, vol.45, no.3, pp.600-609, March 2010
[4.5] K. Woo, S. Meninger, T. Xanthopoulos, E. Crain, D. Ha, and D. Ham,
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68–69, Feb. 2009.
121
[4.6] Kisoo Kim, Hokyu Lee, Sangdon Jung, Chulwoo Kim, "A 366kS/s 400uW 0.0013mm2 frequency-to-digital converter based CMOS temperature sensor utilizing multiphase clock,‖ in IEEE Custom Integrated Circuits Conf. ,pp.203-206, 13-16 , Sept. 2009
[4.7] H. Lakdawala, Y.W. Li, H. Lakdawala, A. Raychowdhury, G.Taylor, K.
Soumyanath, "A 1.05 V 1.6 mW, 0.45 ˚C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process," in IEEE Journal of Solid-State Circuits, vol.44, no.12, pp.3621-3630, Dec. 2009
Chapter 5
[5.1] A. W. Topol et al., ―Three-dimensional integrated circuits,‖ IBM J. Res. Dev.,
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