Chapter 1 Introduction
1.3 Thesis Overview…
Fig. 1.3 Double-Conversion system spectrums
1.3 Thesis Overview
Chapter 2 will give basic ideas of phase-locked loops (PLLs) as well as some important characteristics in a frequency synthesizer. A design flow is described along with detailed parameter setting and architecture together with some examples is demonstrated.
Chapter 3 will present frequency synthesizer which is Fractional N synthesizer.
At first we will discuss the motivation including several design issues, such as: jitter and Phase noise in Ring VCO Then, analysis and implementation of circuit are introduced in detail.
In chapter 4, A spur-reduction architecture will be proposed to further improve the spur reduction function. At first we will discuss the motivation including several design issues and several building block, such as: phase noise, reference spur …..Then, analysis and implementation of our circuit are introduced in detail.
In chapter 5 also; the experimental results will be presented in the end of this chapter.
Finally, chapter 6 will conclusion to this work is given. Suggestions for future works are recommended at the ending of this thesis.
Chapter 2
Fundamental of frequency synthesizers
2.1 Introduction to PLL
In general, the charge pump PLL contains five major building blocks which are phase/frequency detector charge pump, loop filter, voltage-controlled oscillator, and divide. By varying the dividing ratio of the divider, the PLL can synthesizer an output frequency which is a multiple of the input clock. Since the loop characteristics would be influenced by the dividing ratio, we need consider the loop stability carefully when we design the loop parameters. Fig 2.1 shows the topology of a typical frequency synthesizer. The oscillator generates a waveform whose fundamental oscillation frequency is controlled by the input voltage. When a divider is used, this oscillation frequency is divided by an integer number N. THE Phase of the resulting waveform is compared with a reference clock in a phase/frequency divider. Both up and down signals are generated to indicated which direction should the oscillation frequency be corrected. The error signal is low-passed filtered and finally fed a control voltage to the oscillator. The frequency division ratio N adjustable, several oscillation frequencies can be synthesized. Under condition of lock, two inputs of the phase detector have a constant phase relationship and thus equal frequency.
Fig. 2.1 Typical frequency synthesizer architecture The main applications of PLL are as follows:
1. Clock recovery: Some data streams, especially high-speed serial data
streams, (such as the raw stream of data from the magnetic head of a disk drive) are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLL's oscillator. Typically, some sort of redundant encoding is used; 8B10B is very common.
2. Deskewing: If a clock is sent in parallel with data, that clock can be used to
sample the data. Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent.
One way of eliminating this delay is to include a de-skew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock.
3. Clock generation: Most electronic systems include processors of various
sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertzes and the reference crystal is just tens or hundreds of
megahertz.
4. Spread spectrum: All electronic systems emit some unwanted radio
frequency energy. Various regulatory agencies (such as the FCC in the United States) put limits on this emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spread-spectrum PLL to reduce interference with high-Q receivers by spreading the energy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen by FM receivers which have a bandwidth of tens of kilohertz.
2.2 General Consideration
In additional to frequency accuracy and channel selection, two other aspects also influence the performance of a transceiver front-end: phase noise, and spurs.
Fig. 2.2 (a) Ideal; (b) Practical power spectrum of an oscillator 2.2.1 Phase Noise
Ideally, the output of the frequency synthesizer should be pure tones as shown in Fig. 2.2(a). However, due to the thermal noise of the resistors and transistors in
the oscillator or some noise at the frequency tuning input of the oscillator, the phase of the oscillation will fluctuate. In frequency domain, the phase fluctuation forms a skirt of noise power around the carrier impulse as shown in Fig. 2.2(b). In order to quantify the phase noise, the noise power per unit bandwidth at an offset frequency (△w) with respect to the carrier frequency (wc) is compared with the carrier power, and this quantity is expressed in the unit of dBc/Hz. If the noise source is white, the phase noise in the frequency domain is proportional to 1/△f2.
Fig. 2.3 (a) Receiver and (b) Transmitter
The effects of the phase noise in both the receiver and transmitter are shown in Fig. 2.3, which shows the receiver path. If there is a large interference signal near the small desired signal, both the desired signal and interference will be mixed down to the IF. In the mixing both signals will also have the same noise skirt as that of the impure LO signal because the down-conversions is actually a convolution in the frequency domain. Since the power of the interfering signal is generally large, the noise down-converted to the frequency of the desired signal can significantly degrade the signal-to-noise ratio (SNR) of the desired signals. The effect is called
“ reciprocal mixing. ”However, the effect in the transmit path is shown in Fig.2.3(b), where larger-power transmitted signals with substantial phase noise can corrupt weak nearby signals. Therefore, the output spectrum of the LO must be
extremely sharp, and set of stringent phase-noise requirements must be satisfied in the wireless communication system.
Fig. 2.4 Frequency domain representation of spur 2.2.2 Spurs
Other than the phase noise due to the internal thermal noise and external noise, the oscillator can also be modulated by some noise of fixed frequency due to the switching of other circuits in the synthesizer. One of the main noise sources is the switching noise of the charge pump at the reference frequency. The input noise modulate the control voltage and hence the output frequency of the VCO. Two to will appear at the upper and lower sideband of the carrier as shown in Fig.2.4. The tones are called reference spurs and measured by the difference between the power the carrier and the spurs at some frequency offset (△w) in the units of dBc.
Fig. 2.5 Effect of sideband in a receiver
Similar to the case of phase noise, as shown in Fig. 2.5, if there is a interference signal appearing at the frequency which reference spur also exist the desired signal and the interference will be mixed down to the IF, as degrade SNR of the desired one. In a zero-IF system, the down-converted interferer generation the dc offset and thus still affects the system SNR.
2.3 Phase-Locked Loop (PLL) Fundamentals
When designing a PLL-based frequency synthesizer, it is very important to understand the behaviors of each functional block as well as the overall closed-loop behavior. The following discussion focuses on charge-pump PLLs, which is the most popular type of PLLs nowadays and is adopted in our work.
2.3.1 Phase Frequency Detector (PFD)
Phase frequency can detector both phase and frequency difference between the reference signal and the output signal of the frequency divider. As shown in Fig. 2-6, if the frequency of A is greater than the frequency of B, then QA is high, but QB is still low. If the frequency of A and B are equal, then the circuit will check the phase difference between the two inputs, and generates a pulse equal to the phase difference at QA or QB (depends on which input has phase leading).
Fig. 2.6 (a) PFD block diagram (b) PFD state diagram (c) PFD timing diagram
Fig. 2-7(a), it shows a possible implementation of the above PFD. This circuit contains two reset table D-flip flops and a NAND gate. The input signals of A and B are as clock input and the input of two D-flip flops is always high. And we set the initial condition is QA=QB=0. If A is from 0 to 1, until B is from 0 to 1 and QB becomes high to make the two D-flip flops reset. And Fig. 2-7(b), shows the input-output characteristic of the PFD.
Fig. 2.7 (a) PFD implementation (b) PFD characteristic
Fig. 2-8(a) shows the PFD circuit. It is negative-trigger and has the same function as we discuss above. But it still has a drawback. When this type of PFD incorporated with charge pump circuit, it has a drawback that a dead zone exist, as shown in Fig. 2-8(b). If the reset signal is not delayed sufficiently, the output of charge pump will not change for small phase error, thus the dead zone translates to jitter in PLL and must be voided. In Fig. 2-8(a), the delay chain to increase delay of reset signal for eliminating dead zone.
Fig. 2.8 (a) Phase frequency detector (b) Dead zone in PFD 2.3.2 Charge pump
A PFD could not alone provide the exact voltage (or current) signal proportional to the phase difference at its inputs. A charge pump serves to convert the two digital output signals QA and QB of the PFD into charge flows whose quantity is proportional to the phase error. A passive filter then shape the output current signal of the charge pumps to suppress the useless messages buried in that signal.
A PFD together with a charge pump and a single capacitor C1 as the loop filter are shown in Figure 2.9, with the corresponding time-domain response shown as well. As a higher frequency than B or has the same frequency as B but with a leading phase, the charge pump sources a constant-valued current I1 through switch S1 into the capacitor, and the output voltage increases steadily. Similarly, if the frequency of input A is lower or the phase is lagging, the output waveform will be a steadily downward one. What happens if the inputs are exactly the same? Careful examination shows that QA and QB will have pulses of short duration. In this case, if the currents of the two current sources are the same in quantity, as indicated in
Figure 2.10, at the time that both S1 and S2 are on, the current sourced by I1 is exactly sunk by I2. Thus no net current will flow through C1 and Vout remains unchanged as in the case when both S1 and S2 are off.
Fig. 2.9 PFD with charge pump and the timing diagram
The phase frequency detector and the charge pump can be together characterized as:
Where IPUMP is the output current of the charge pump, ψe=ψA-ψB represents the phase error between the two PFD inputs and I=I1-I2 is the current value of the two current sources in the charge pump. This representation, however, is an approximate one. One should note that the charge pump is a discrete-time system, and it provides good approximation only when the loop bandwidth is much less than the input reference frequency.
The single-capacitor loop filter nevertheless has an infinite dc gain, which might unstablilize the close loop. To avoid instability, a resistor RP in series with CP is added, which in effect adds a LHP (left-half-plane) zero to the overall open-loop transfer function. The transfer function of the resolution loop filter is:
2
e p u m p
I I φ
= π (2.1)
Note that this representation indicates a conversion from an input current a output voltage, and thus is directly applicable in conjunction with Equation. (2.1).
Fig. 2.10 Addition of a zero to a charge pump 2.3.3 Voltage-Controlled Oscillator
Many applications need that the oscillators be “tunable”. The most popular circuit is the voltage-controlled oscillator, whose frequency is a linear function of its input control voltage. The transfer function is as follows:
Hereω0is the free running frequency, KVCO is gain or sensitivity of the VCO, (usually in rad/s/V). Next, we want to derive the phase transfer function:
Only the second term of the total phase is of interest. We call
0 t
VCO cont
K
∫
V dt as the “excess phase”, denoted byφex. In fact, in the analysis of PLLs, we respect the VCO as a system whose input as the control voltage and output as the excess phase.If the system is LTI, then we get:
Therefore the VCO acts as an ideal integrator, providing a pole at s = 0 in the open loop transfer function in the PLL.
2.3.4 Loop Filter
Fig. 2.11 PLL-based frequency synthesizer linear model
However, before further examining the loop filter, linear models of the PLL-based frequency synthesizer should be established. With proper characteristic of each function block, the close-loop behavior of frequency synthesizers can be analyzed. A linear model of a charge-pump PLL-based frequency synthesizer is shown in Fig. 2.11. Note that the input and output signals are phase (rad/s). Phase errorφe, the difference between the input phase φin and the feedbackφfb, is extracted by the PFD, which is represented by a simple PLL in the linear model. The charge pumps (CP) then translate φe into a current signal with a gain of IP/2π, where IP is the pump current. This current signal (A) flows into the passive filter (Ω ), and is converted to voltage signal (V) at the control input of the VCO. The VCO generates an output signal whose frequency is related to the control input voltage with a gain of KVCO (Hz/V). Since the phase signal rather than frequency signal is the variable in this linear model, the VCO block include a“1/ s”term that integrates the frequency signal to derive the phase signal. The frequency divider in the feedback path is still a sample“1/ M”factor since division in frequency domain has the same effect in phase domain. Hence, the open-loop transfer function can be represented as:
2 1 transfer function, can be found assuming that K is much greater than wz:
Thus the open-loop transfer function can be rewritten as:
( ) s 2wz
G s K
s
= ⋅ + (2.10)
The simplest LPF is to connect a capacitor to the control voltage. The open-loop transfer function is derived as follows:
1
Since the loop gain has two poles at the origin, this topology is called a “type II” PLL. It is unstable because the loop gain has two poles at the origin. As illustrated in Fig. 2.12(a), each integrator provides constant 90phase shift. Thus the system will oscillate at the unit-gain frequency. So, we have to add a zero to increase phase margin.
We can thus add a resistor in series with the original capacitor. The open-loop transfer function is derived as follows:
1 severe problem occurred in such PLLs. Due to the resistor in series with capacitor, each time a current is injected into the loop filter and then produces large voltage jump. It makes ripples of control voltage of VCO and degrades the purity of the output frequency spectrum.
20log HOPEN 20log HOPEN
Fig. 2.12 (a) Loop gain of simple PLL (b) addition of zero
We can ease this effect by adding a second capacitor in parallel withRPandCP. The loop filter is now of 2nd order and the open loop transfer function of PLL now is of third-order and has stability problem, as shown in Fig. 2.13 (a). But if we makeC2is about one-fifth to one-tenth ofCP, the open-loop transfer function is near the second-order and would be stable.
2
where add additional LPF to suppress the spur that is frefoffset from the carrier frequency, as shown in Fig. 2.13 (b). The loop filter transfer function is
2 significantly attenuate the spurs. However, it must be at least five times higher than the loop bandwidth, or the loop will almost assuredly become unstable.
Fig. 2.13 (a) 2nd order loop filter (b) 3rd order loop filter 2.3.5 Frequency Divider
Frequency dividers are used to synthesize a high frequency LO from a precise low frequency crystal oscillator. The output frequency fdiv equals the input frequency fin divided by an integer number. From this information we could derive a model for
the divider in the phase domain.
The phase θin of the input signal is given by
And the instantaneous frequency of the input signal is:
And the phase of the output signal can now be found as:
2.4 Noise Analysis of the PLL Synthesizer
The job of any frequency synthesizer is to generate a spectrally pure output signal. An ideal periodic output in the frequency domain has only an impulse at the fundamental frequency and perhaps some other impulse energy at DC and harmonic.
In the actual oscillator implementation, the zero crossings of the periodic wave vary with time as shown in Fig. 2.14. This varying of the zero crossings is known as time domain jitter.
Fig. 2.14 Periodic signal with jitter
A PLL-based frequency synthesizer suffers from introduced at input or
generate by the other building blocks. It is important to learn how different noise sources affect the noise performance of the output signal. The sources of noise may be classified into two types: (1) the noise at input, and (2) the noise of VCO.
2.4.1 Input Noise Source
An input reference signal with phase noise can be modeled in the PLL as shown in Fig. 2.15(a) [5].
The input noise, Φin, is treated as an input signal and the same PLL transfer function for the input noise transfer function. The input phase noise transfer function is plotted in Fig. 2.15(b).
Fig. 2.15 (a) PLL Input Phase Noise Model (b) Bode plot normalized transfer function
The input phase is shaped by the low-pass characteristic of the second-order PLL. In order to reduce the phase noise in the output signal due to the input phase noise it is desired to make the PLL bandwidth as narrow as possible. Notice that the input noise is amplifier by a factor of N. If input noise is a concern, the lowest
input phase noise is not a concern because the reference signal generally comes from a low phase noise crystal oscillator.
2.4.2 Noise of VCO
The phase noise of the VCO can be modeled as Fig. 2.16(a) [5]. The VCO phase noise, VCON, is treated as an input signal and following transfer function is plotted in Fig. 2.16(b).
The VCO phase noise is shaped by a high-pass characteristic by the second-order PLL. In order to reduce the phase noise in the output signal due to the VCO phase noise it is desirable to make the PLL bandwidth as wide as possible.
Here a tradeoff regarding loop bandwidth position and its effect on input phase noise contribution and VCO phase noise contribution is observed. The optimum loop bandwidth depends on the application. It is optimal to have a narrow loop bandwidth
Here a tradeoff regarding loop bandwidth position and its effect on input phase noise contribution and VCO phase noise contribution is observed. The optimum loop bandwidth depends on the application. It is optimal to have a narrow loop bandwidth