Chapter 2 Fundamental of frequency synthesizers
2.4 Noise Analysis of the PLL Synthesizer
2.4.2 Noise of VCO
The phase noise of the VCO can be modeled as Fig. 2.16(a) [5]. The VCO phase noise, VCON, is treated as an input signal and following transfer function is plotted in Fig. 2.16(b).
The VCO phase noise is shaped by a high-pass characteristic by the second-order PLL. In order to reduce the phase noise in the output signal due to the VCO phase noise it is desirable to make the PLL bandwidth as wide as possible.
Here a tradeoff regarding loop bandwidth position and its effect on input phase noise contribution and VCO phase noise contribution is observed. The optimum loop bandwidth depends on the application. It is optimal to have a narrow loop bandwidth for input noise performance. cycle fluctuations in the power supply[7][8]. With the VCO contributing significant phase noise it is optimal to make the loop bandwidth as wide as possible.
2
Fig. 2.16 (a) Noise transfer function of a PLL from VCO to output (b) Bode plot of the normalized transfer function
The total phase noise can be derived by adding the above two eventual phase noises, as shown in Fig. 2.17. It is obviously that when the frequencies nears carrier, the REF in the closed loop dominate the total phase noise. Otherwise, the VCO dominates. If we want to suppress the phase noise of REF, we can decrease the BW.
However, it will raise the phase noise of VCO. On the contrary, increasing the BW will suppress the phase noise of VCO but raise the phase noise of Ref. It is a trade off. How we decide the best BW is important.
2
1 f
3
1 f
1 f
Fig. 2.17 Total output phase noise
Chapter 3
Fractional-N PLL
3.1 The Fractional Mechanism
Before studying the fractional architecture, we make an observation. Suppose, as shown in Fig. 3.1, a pulse is removed every TP seconds from a periodic signal x(t) that has a frequency f1. The resulting waveform, y(t) then exhibits f1‧TP-1 pulses every TP seconds, i.e., y (t) has an “average”frequency equal to f1-1/TP. This method can be used to vary the average frequency of a signal by small steps. We should note, however, that f (t) is not a strictly periodic signal. The idea of removing pulses nevertheless useful in fine-step frequency synthesis.
Fig. 3.1 Periodic removal of a pulse from a periodic waveform
Fig. 3.2(a) shows simple fractional-N architecture. In addition to the PFD, LPF, and VCO, the loop incorporates a pulse remover, a circuit that blocks one input pulse upon assertion of the remove command. Since under locked condition the two
frequencies presented to the phase detector must be equal, the average output frequency of the pulse remover equals fref, and hence fout=fref+1/TP, where TP is the periodic with which the remove command is applied. Note that fout can vary by a fraction of fref because the frequency fp=1/TP can be derived from fref by simply division. Provided by a crystal oscillator, fref is typical limited to a few tents of megahertz. Thus, as shown in Fig. 3.2(b), a fractional-N synthesizer incorporates a divider in the feedback to generate high output frequencies.
Fig. 3.2 (a) simple fractional-N synthesizer (b) use of divider in the loop While the original fractional-N topology was based on the pulse remover concept [9], modern implementations of this architecture operate on a somewhat different principle. Depicted in Fig. 3.3, such a synthesizer replaces the pulse remover and the divider of Fig. 3.2 (b) with a dual-modulus prescaler. If the prescaler divides by N for TN output pulses (of the VCO) and by N+1 for TN+1 output pulses, shown in Fig. 3.3 (b), then the equivalent divide ratio is shown as
1 ( 1)
This value can vary between N and N+1 in fine steps by proper choice of A and B. The resulting modulus is sometimes written as N.f, where the dot denotes a decimal point and N and f represent the integer and fractional parts of the modulus.
Fig. 3.3 (a) Fractional-N synthesizer using a dual-modulus divider, (b)Timing diagram
3.2 The First Order Fractional-N Synthesizer
Fig. 3.4 shows the fractional-N PLL [10] which the accumulator and the cycle swallower become part of the circuit. The operation principle of this structure is the same as the one described in Fig. 3.3(b). Fig. 3.5 shows the detail circuits and timing diagram of the cycle swallower. To operate, a chain of VCO pulses serves as the clock for the flip-flop. A swallow trigger signal is illustrated generally as being
edge of swallow trigger and output a Q1 pulse to flip-flop. When the next negative edge of VCO signal appears at the clock of flip-flop, the Q2 output goes negative.
This output resets flip-flop and also provides an “off”input to AND gate. Thus, the next VCO pulse will not appear at the output of AND gate; that is, has been swallowed. The negative edge of pulse again triggers flip-flop allowing the subsequent pulses of the VCO signal to pass through AND gate.
Fig. 3.4 Fractional-N synthesizer using a cycle swallower and an accumulator
Fig. 3.5 (a) Cycle swallower circuit, (b) Its timing diagram
From Fig. 3.3(b), this periodic modification of the divider modulus gives rise to a sawtooth phase error (Fig. 3.6). If unfiltered, the phase error causes severe spurious tones-fractional spurs at all multiples of the offset frequency (.f×fref).
Fig. 3.6 Sawtooth phase error for the first order fractional-N synthesis
3.3 The Second Order Fractional-N Synthesizer
The fractional spurs in the above-mentioned averaging fractional-N synthesis are a serious problem. An important can be achieved by analog compensation of the phase error [11, 12, 13]. The output of the phase register of the digital accumulator is a measure for the phase error. The phase register is a kind of “bookkeeping system”that tracks the phase advancement of the VCO for every reference cycle.
Due to the loop integration the actual phase detector output becomes an analog sawtooth waveform which is mentioned in Fig.3.7.Using a DAC (Digital-to-Analog) the staircase output of the phase register can be converted to an analog sawtooth current, scaled by A (Fig. 3.7) to match the phase error. By summing the phase detector output and the DAC output on the loop filter capacitors, the AC component is in the ideal case removed from the phase error. The VCO output is now only driven by the wanted DC phase error, canceling all fractional spurs in the output spectrum.
However, this method has several disadvantages. First of all, the maximum
amplitude of the phase error depends on fref, such that the DAC output amplitude must be variable, while its input is constant. Secondly, the sampling frequency of the DAC can be rather high. To have fast setting (large loop bandwidth), the fref can easily be some tens of MHz. The sampling frequency of the DAC must be at least 2×fref, for a full Nyquist DAC, to be able to compensate spurs up to the reference frequency. To have a spurious suppression of at least -70dB, required in most telecommunication system, the accuracy of the DAC must be around 8 bits [14].
This occupies a larger chip area and dissipates the power consumption. Thirdly, due to matching issues, the accuracy of the cancellation is limited, requiring external adjustment and calibration. Therefore, the analog compensation method is not a viable solution for all integration of frequency synthesizers for wireless communication systems in CMOS technology.
Fig. 3.7 The analog phase interpolator
3.4 The Third Order Fractional-N Synthesizer
The next significant evolutionary step for fractional-N synthesizer will be an all-digital implementation, known as delta-sigma modulator (DSM), eliminating spurious digitally and allow good phase noise performance by digitally noise-shaping techniques, as shown in Fig. 3.8 [15]. The DSM architecture used in this paper terms as a Multistage Noise Shaping (MASH) which is cascaded by three
first-order modulator to ensure the stability. It is assumed random to model each 1-bit quantizes as a unity gain element with added quantization noise. N.F is the desired rational divide ratio and Ndiv (k) is the actual sequence presented to the integer divider. The transfer function is
( ) ( ) (1 1 3) ( )
Ndiv z N f z z E 3 z
q
= + − − ×
⋅ (3.2)
In a locked PLL,
1 3 3
( ) ( ) ( )(1 )
out div ref
out ref q ref
f N f
F z N F z⋅ f E z z− f
= ×
= × + − × (3.3)
Where the first term is the desired frequency and the second term represents frequency noise due to delta-sigma modulation.
By converting to the frequency domain and generating to any number of modulators, the power spectral (PSD) which is considered with small offset ranges compared to the reference frequency is [15].
2 ( 1) accumulator is a compact realization of the delta-sigma modulator as shown in Fig.
3.8 (b). This architecture leads to the all digital implementation easily. Regardless of the advantages of low phase noise, low reference feedthrough spurs, fast tuning speed, and small step size for this architecture, fractional spurs is a design issue to overcome. In addition, when the DSM is fed with a DC input, the quantized signal bounces between two levels and may be periodic. The structure of such quantization is known as pattern noise, or idle tones. Since this is the desired architecture for the fractional-N synthesizer in this thesis, we will consider this problem and figure out how to solve these problems?
3.4.1 Delta-sigma modulators
DSMs are basically divided into two types: single-stage and cascaded. Digital DSMs, unlike their analog counterparts, don，t have any non-idealities, and when the modulator is stable, there is no overload problem. Cascaded digital modulators won，t suffer from mismatches and noise leakage from front stages, and multi-bit quantizer won，t suffer from any nonlinearity, which doesn’t exit digital modulator at all.
To understand the function of the DSM, one should know the building block:
the first-order DSM or the accumulator. A block diagram of the first-order DSM with the error-feedback topology is shown in Fig. 3.9(a), where the quantizer is modeled as an additive white noise source e[n]. The signal-flow graph for this modulator in its digital implementations is illustrated in Fig. 3.9(b), where the m-bit
input signal K[n] is summed with the m-bit register content to produce the (m+1)-bit quantizer input signal v[n]. The 1-bit quantization process is accomplished by simply taking the most significant bit (MSB) of v[n]. The residual m-bit signal, which represents the negative of the quantization error signal, is then stored in the m-bit register to be summed with the input signal at the next clock cycle. The accumulator overflow and the accumulator result correspond to the 1-bit quantizer output and the negative of the quantization error at any time, respectively.
Fig. 3.9: A first-order DSM (a) block diagram, (b) its digital implementation The transfer function of the first-order DSM is
Thus the power spectral density is
Where fs is the sampling frequency or the reference frequency, fref, for the synthesizer. Note that 1-bit quantizer is assumed to have uniform quantization error and the power is spread over a bandwidth of fref. Consequently, the power spectral density (PSD) of quantization error is 1/ (12 fref). Note that the second term of Eq.
3.7 is the PSD introduced by the quantization noise. Generally, where m is the order of the DSM.
To illustrate the noise shaping action of the DSM, one can apply a sinusoid with amplitude A, frequency fo to the DSM input. Fig. 3.2 shows the PSD of the first-order DSM. The high frequency band shows the 20dB/dec noise shaping. Note that there exists many spurs around the signal which will effect the noise requirement targeted in many wireless system. Thus, the first DSM is not suitable to the fractional-N synthesis.
Fig. 3.10 Noise shaping in the first-order DSM
2nd and 3-order DSMs are practically used for fractional-N synthesizers. 4th or even higher order modulators are rarely used because it，s difficult to suppress the phase noise at higher frequencies by limited order of loop filter. We will study the second-order cascaded and single-loop DSM in the next two sections.
3.4.2 The Cascaded Modulator
The cascaded 1-1 or MASH (multi-stage noise-shaping) DSM modulator is shown in Fig. 3.11. The MASH modulator consists of a cascaded of first-order modulators, whose quantization error –Ei is the input to the next modulator. By summing the filtered versions of the first-order outputs, the quantization error of the first modulator is cancelled. Since the DSM modulator in fractional-N PLLs is an all
2
digital implementation, the cancellation is perfect. The output of the modulator with
The equations expose the most important quality of a MASH modulator, i.e. its unconditional stability for any modulator order, because of its first order nature.
Another advantage is the integration of the MASH modulator in plain CMOS technology, since only adders and register are needed to implement the noise shaping function.
Fig. 3.11 The 2nd –order MASH modulator
In the implementation of Fig. 3.11, the output is a 2-bit word with a mean value, fractional number .f. With Nnorm added, the nominal frequency could be tuned for the purpose of targeted frequency band. Note that to increase the output dynamic range of the modulator to accommodate more division moduli, multiple MSBs can be taken as outputs of the first-order modulators instead of the single bit output, of1[16].
To obtain the theoretical PSD in the locked PLL, using Eq. (3.10)
(3.11) is the frequency fluctuations of Fout(z),
1 2 2
We want phase fluctuations, not frequency fluctuation.
( )t w t d t( ) 2 fE d t
φ =
∫
= π∫
(3.12)Employing a simple rectangular integration to represent ∫ dt in the z-domain,
1 1 that the offset range is small compared to the reference frequency.
2 ( 1 )
Note that this is the derivation of Eq. (3.4).
In the frequency domain, the intensive use of modulus dynamic range translates
in substantial levels of high frequency. This is reflected in the noise transfer function (NTF) of the MASH modulator, which is (1-z-1)2 (see Eq. (3.10)). Fig. 3.12 shows the simulated output spectrum for this MASH 1-1 modulator. Compared to the Eq.
(3.8), it provides the 40Db per decade for high frequency noise shaping.
Fig. 3.12 The theoretical and simulated output spectrum for the MASH 1-1 modulator
3.4.3 The Single-Loop DSM Modulator
The single loop DSM multiple-feedback modulator is shown in Fig. 3.13. In contrast to the MASH modulator, this modulator consists of a single, 2nd-order discrete time filter with multiple feedback coefficients, which influence the NTF.
Compared with MASH architectures, single-loop architecture has better noise shaping characteristics for dc inputs. But it is subject to instability and smaller stable input range. The latter limitation can be eliminated with a multi-bit quantizer in digital DSMs. Note that the input is also subject to a non-unity transfer function.
This poses no problem for frequency synthesis, since the DC value of the input is passed unaltered. But problems arise when the synthesizer is used for data transmission, where the modulated data stream will be shaped by the DSM signal transfer function. The dc output of this modulator is given by X/M where X and M are parameters that can be set externally. Thu use of an M quantizer allows the
a fixed 2k. The introduction of M is also for the stability purpose making the wider quantization room.
The NTF of this single-loop DSM is:
1 1 2
Fig. 3.13 The 2nd-order single-loop DSM with multiple feedback coefficients
3.5 Other Types
The basic idea adopted by the three kinds of the structures discussed previously is to get the fractional output frequency by changing the “integer”ratio in the trick of averaging. A technique, fractional-N synthesizer, evolves from the fundamental principles of integer-N synthesis. The only difference is that the frequency divider is replaced with a fractional divider. A fractional frequency divider is no longer a simple digital counter. The period of the divider output, Tdo, is given by not time varying once N and 0.F are set. In other words, a rising edge occurs at the output each and every N and 0.F VCO cycles. Fig. 3.14 is a timing diagram
illustrating the operation of a fractional divider where N.F is set to be 2.25.
Fig. 3.14 Timing diagram of a fractional-N frequency divider
( 0 . )
V C O r e f
f = N + F × f (3.19)
A brief description of a simple circuit realization of a fractional frequency divider is given. The block diagram is depicted in Fig. 3.15(a) [17]. As is clear from this figure, the divider comprises a dual modulus divider (DMD), a delay locked loop (DLL), a multiplexer (MUX) and digital phase accumulator (DPA). Note, however, that a fractional divider does not have to be based on a DLL. The DLL shown in this figure consists of a set of cascaded, tunable, delay element, a PD, a CP and a D-type flip-flop. The negative nature of the feedback in the DLL ensures that the total delay through the delay line is one VCO cycle. Since the delay elements are, ideally, identical, a VCO period is broken up into Nd equal of phase, where Nd is the number of delay elements in the delay line.
A simple digital phase accumulator is made of an adder and a register, as is shown in Fig. 3.15(b). The register is clocked by the reference. The input to the DPA is an m-bit word. The content of the register are used to control the MUX. On every reference rising edge, the contents will be incremented by the value of the input, x, which is presented by an m bits word. The output of the DPA, ie., the carry-out of the adder, is a 1-bit quantization of the input. The number of bits in the accumulator is related to the number of discrete of phase by Nd=2m, the output of the DPA controls the DMD. When carry-out is high, the DMD divides by N+1 as opposed to
N when carry-out is low. As we will see in the following example, the fractional division ratio, N+0.F, for a DPA input of x is equal to N+x/2m. Suppose the DPA has 3 bits and, therefore, the delay line has 8 elements each phase corresponds to 1/8 of a VCO cycle. Also assume that the input is equal to 2, which corresponds to a 0.F of 2/8. When no carry-out occurs, the DMD divides by N. Its output, however, is not immediately presented to the PFD of the PLL. Rather, it will be delayed by a number of phase controlled or selected by the MUX. This number is equal to the content of the PDA, which is incremented by 2 every reference cycle. This means that the output is phase shifted by a progressively increasing number of phase, i.e., 0, 2, 4, 6, 8 each reference cycle. As a result, the period of the DMD output is increased by 2/8 of a VCO cycle. Therefore, the effective division ratio becomes N+0.25, which is what it should be. When the DPA content reaches 8, the content of DPA will be reset and the output of the DMD will not be delayed by the delay line.
However, this coincides with a carry-out, which forces the DMD to divide by N+1.
This is equivalent to the DMD dividing by N and its output being delayed by 8 phase, i.e., one VCO cycle.
The design of the fractional divider dictates the fractional modulus or fractional denominator to be Nd, the number of delay elements. Since all the elements in the delay line operate at the VCO speed, the added power consumption can be significant, especially when the VCO frequency and/or fractionality are high.
Another drawback of this method is that the edges of the fractional divider output mat be contaminated or jittery as a result of jitter on the outputs of the delay elements. Jitter is present due to mismatch and phase error due to the phase error correcting action of the DLL. The edge contamination may result in a significant increase in the PD noise floor.
Fig. 3.15: (a) An example of fractional-N divider (b) digital phase accumulator
3.6 Expressions for Jitter and Phase noise in Ring Oscillator
Although the expressions obtained in the section for the rms and dc value of the ISF can be used to calculate the phase noise, it is desirable to express phase noise and jitter in terms of design parameters such as power dissipation and frequency. In
Although the expressions obtained in the section for the rms and dc value of the ISF can be used to calculate the phase noise, it is desirable to express phase noise and jitter in terms of design parameters such as power dissipation and frequency. In