Chapter 4 Spur-reduction Frequency Synthesizers for DTV and WIMAX
4.5 Fractional-N Frequency Synthesizer System
Fig. 4.2 shows architecture of DTV based on three-order Σ∆ modulator. Fig.
4.45 (a) shows the VCO control voltage. We can obviously find that the control voltage is stability. Fig. 4.45 (b) shows the carrier spectra, the reference spur about 65dbm.
Fig. 4.45 (a) VCO control voltage and (b) Out Spectrum when LO is 2.088GHz Fig. 4.3, Fig. 4.4 shows architecture of WIMAX (mobile) based on three-order Σ∆ modulator. Fig. 4.46 (a), Fig. 4.47 (a) shows the VCO control voltage. We can obviously find that the control voltage is stability. Fig. 4.46 (b), Fig. 4.47 (b) shows the carrier spectra, the reference spur about 71dbm, 70dbm.
The random charge PLL in Fig. 4.5 shows architecture of WIMAX (mobile) based on three-order Σ∆ modulator. Fig. 4.48 (a) shows the VCO control voltage.
We can obviously find that the control voltage is stability. Fig. 4.48 (b) shows the carrier spectra, the reference spur about 80dbm.
Fig. 4.46 (a) VCO control voltage, sample capacitor, lock detector and random clock (b) Out Spectrum is 2.5GHz
Fig. 4.47 (a) VCO control voltage, sample capacitor, lock detector and random clock (b) Out Spectrum is 2.5GHz
Fig. 4.48 (a) VCO control voltage and lock detector (b) Out Spectrum is 2.5GHz
The closed-loop simulation results in Fig. 4.45, Fig. 4.46, Fig. 4.47 and Fig.
4.48, using HSPICE are done. The parameters and performance summaries of the frequency synthesizer are listed in Table 4-9.
TABLE 4-9 Fractional-N PLL performance summaries
Chapter 5
Testing Setup and Experimental Results
5.1 Experimental Results
The proposed Σ∆ frequency synthesizer has been fabricated in a 0.18-µm 1P6M mixed-signal technology. Shown in Fig. 5.1(a), 5.2(a) is the layout and 5.1(b), 5.2(b) is the die photo of the chip. This chip occupies an area of 1.027*1.026mm2, 1.14 X 1.14mm2. Shown in Fig. 5.3(a), Fig. 5.3(b), Fig. 5.3(c), is representation from Fig.
4.3, Fig. 4.4, and Fig. 4.5.
(a) (b) Fig. 5.1 (a) Layout (b) Die photo
(a) (b) Fig. 5.2 (a) Layout (b) Die photo
(a) (b)
(c)
Fig. 5.3 (a) Layout1 (b) Layout2 (c) Layout3
5.2 Test Setup
The fabricated synthesizer was tested to determine its performance.
Measurement was performed with raw dies mounted on the PCB to prevent the parasitic effect of the package. Because the synthesizer is a mixed-mode system, we separate the powers and grounds of digital and analog parts. Then, we connect the ground of analog part and that of digital part with an inductor. The inductor shorts the DC voltage of the digital and analog grounds, while preventing the high-frequency noise in the digital circuit from coupling to the analog circuit by their grounds.
The analog and digital powers are generated by LM317 adjustable regulators as shown in Figure 5.4. The regulator circuit is easy to use and the output voltage could be predicted by equation (5.1)
VO U T = 1 . 2 5 1
(
+ R1 R 2)
+ IA D J iR2 (5.1)The IADJ is the DC current that flows out of the ADJ terminal of the regulator.
Besides, the capacitors C1 and C2 are the bypass capacitors.
Fig. 5.4 LM317 regulator
The outputs of the regulators are bypassed on the PCB with the parallel combination capacitors then connected to the chip. The bypass filter network is combined by 10µF, 1µF, 0.1µF and 0.01µF capacitors as shown in Fig. 5.5. The
arrangement can provide decoupling of both low-frequency noise with large amplitudes and high-frequency noise with small amplitudes [31].
Fig. 5.5 Bypass filter at the regulator output
The measurement setup of the synthesizer is shown in Fig. 5.6. The input clock is produced from the signal generator (Agilent 81110A). The output spectrum is observed by a Spectrum Analyzer (Agilent E4440A).The testing PCB is shown in Fig. 5.7.
Fig. 5.6 Measurement setup of the synthesizer
Fig. 5.7 The testing PCB in the synthesizer
5.3 Measurement Results
Fig. 5.8 shows the measured transfer curve of VCO. The measure tuning range is 2.11GHz~0.732 GHz, 2.86GHz~2.1GHz for VCO. The DTV system has 7 bands
Fig. 5.8 Measure VCO transfer curve
(a) (b)
Fig. 5.9 Measured output spectrum of WIMAX (mobile) synthesizer
(a) 2.5MHz offset (b) 3MHz offset
-36.9-10log (30‧103) =-81.67dBc/Hz -42.56-10log (30‧103) =-87.33dBc/Hz Fig. 5.10 Measured phase noise of lock synthesizer for WIMAX
(a) (b)
Reference spur=-36.76dBc Reference spur=-43.49dBc Fig. 5.11 Measured reference spur of lock synthesize
Fig. 5.12 Measured output spectrum of divide in lock 2.5GHz
Fig. 5.13 Measured output spectrum of DTV synthesizer
(a) 1MHz offset (b) 3MHz offset
-41.62-10log (10‧103) =-81.62dBc/Hz -57.1-10log (10‧103) =-97.1dBc/Hz Fig. 5.14 Measured phase noise of lock synthesizer for DTV
-58.51-10log (100‧103) =-108.51dBc/Hz Reference spur=-69.78dBc
Fig. 5.15 Measured phase noise and reference spur of lock synthesizer for DTV
5.4 Measured Summary
In Fig. 5.9 shows the measured output spectrum of WIMAX (mobile) synthesizer where the PLL is locked. The output frequency is 2.5GHz, 2.7GHz which equals dividing ratio of 100, 108. In Fig. 5.11 the measured value of reference spur, there are 36.76dBc, 43.49dBc.Table 5.1 summarized the measured performance of the propose frequency synthesizer for DTV, WIMAX (mobile) system.
TABLE 5.1 Measure synthesizer performance summaries Technology(TSMC) 0.18-um CMOS 0.18-um CMOS
Carrier Frequency 2.5GHz ~2.7GHz 1.15GHz~2.08GHz
Reference Frequency 25MHz 36MHz
Phase Noise @1MHz Phase Noise @2.5MHz
Phase Noise @3MHz Phase Noise @5MHz
N/A
-81.67dBc/Hz -87.33dBc/Hz N/A
-81.62dBc/Hz N/A
-97.1dBc/Hz -108.51dBc/Hz
Spur Level -43.49dBc -69.78dBc
Power dissipation 32mW 33mW
Supply Voltage 1.8V 1.8V
Die area 1.027mm×1.026 mm 1.14mm×1.14 mm
Chapter 6
Conclusions
6.1 Conclusions
A propose suppression technique is proposed for integer-N frequency synthesizer to reduce the amplitude and random the periodic ripple in lock without changing the loop parameter. The PLL synthesizer is composed of five building blocks: the phase frequency detector, the charge pump, the loop filter, the VCO and the programmable divider. A lot of design challenges can be found in each block, but this work has tackled the problems of the VCO, reference spur. We reduce the VCO gain and random the ripple in the frequency synthesizer.
The all-digital DSM is widely used in the fractional-N synthesizer because of many good properties. One major advantage is the reduction of the reference spur by randomizing the feedback division ratio such that the quantization noise of the fractional-N divider is transferred to higher frequency.
Some suggestions for the future work are given as follows. Firstly, the ESD protection should be considered in the circuit design and physical layout to avoid the instantaneous high voltage breaking down the circuit. Finally, parallel control bits of the modulator can be designed as serial input scheme to reduce the large number of PAD, which will save the area.
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