Circuit analysis

The ripples on control voltage of VCO denoting as g(t), are modeled as narrow, rectangular pulses having a width △T and a height △V, as shown in Fig.4.9[24]. V1 is the dc value of control voltage and the periodic of ripples are mTref which equals to the period of the decomposing random clock generator signal.

Fig. 4.9 Simplified model for disturbance on control line

By making the assumptions above, we can express the output of VCO as:

0 1

( ) c o s ( )

o u t F R v c o V C O

V t = V  w t + K

∫

g t d t + K

∫

V d t  ^(4.2) The Fourier series expansion of g (t) is given by

0

Where the first term represents the dc component and can be merged with V1.

Inserting Equation (4.2) into (4.3), we can approximate Vout (t) as:

0 1 Vout (t) can be expressed as:

0 0 0

The Fourier coefficients of g (t) denoted as am can be expressed as:

( )

periodic ripples and those disturbed by random clock. We can know if random clock generates a “1”, a pulse is generated aligned with the original one. And if random clock generates a “0”, it means the pulse will deviate from the original one 1/2Tref. In other word, 0 and 1 of random clock outputs represent different delay the position of ripples.

Fig. 4.10 Illustration of Random clock disturbance 4.3.4 Sampling Switches

An important attribute of the switch, in CMOS, is that under DC conditions the gate of the MOSFET does not draw a current. Therefore, neglecting capacitances from the gate to the drain/source, we find that the gate control signal does not interfere with information being passed through the switch. Figure 4.11 shows

fundamental component of any dynamic circuit is the switch. Figure 4.12 shows the small-signal resistance of the switch of Figure 4.11 plotted against input voltage.

The benefits of using the CMOS transmission gate are seen from the figure, namely overall resistance. Another benefit of using the CMOS TG is that it can pass a logic high or logic low without a threshold voltage drop. The largest voltage that an NMOS switch can pass is VDD- VTHN, while the lowest voltage a PMOS switch can pass is VTHP.

Fig. 4.11 MOSFETs used as switch

Fig. 4.12 Small-signal on resistance of MOSFET switches

While MOS switches may offer substantial benefits, they are not without some detraction. Two nonideal effects typically associated with these switches may ultimately limit the use of MOS switches in some application. These two effects are known as charge injection and clock feedthrough.

Charge injection can be understood with the Fig. 4.13. When the MOSFET switch is on and VDS is small, the charge under the gate oxide resulting from the

inverted channel is Q^,ch. When the MOSFET turns off, this charge is injected onto the capacitor and into Vin. Because Vin is assumed to be a low-impedance, source-driven node, the injected charge has effect on this node. However, the charge injected onto Cload results in a change in voltage across it. However, the fact the input voltage is connected to Cload through the channel resistance makes this error unimportant (the voltage across C_load charges to V_in through the MOSFET^，s channel resistance).

Fig. 4.13 Simple configuration using an NMOS switches to how charge injection In Fig. 4.14 the schematic of the NMOS switch representation clock feedthrough. Here the capacitances between the gate/drain and gate/source of the MOSFET are modeled with the assumption that the MOSFET is operating in the triode region. When the gate clock signal,ψ, goes high, the clock signal feeds through the gate/drain and gate/source capacitances. However, as the switch turns on, the input signal, Vin, is connected to the load capacitor through the NMOS switch.

The result is that Cload is charged to Vin and the capacitive feedthrough has no effect on the final value of Vout. However, now consider what happens when the clock signal makes the transition low, that is, the n-channel MOSFET turn off. A capacitive voltage divider exists between the gate-drain (source) capacitance and the load capacitance. As a result, a portion of the clock signal,ψ,appears across as:

o v e r l a p

Where Coverlap is the overlap capacitance value, and LD is the length of the gate

that overlaps the drain/source.

, o v e r l a p o x

C = C ⋅W ⋅ L D (4.8)

Fig. 4.14 Illustration of capacitive feedthrough

Many methods have been reported that reduce the effects of charge injection and clock feedthrough. One of the most widely used is the dummy switch, as seen in Fig. 4.15. Here, a switch, M2, with its drain and source shorted is placed in series with the desired switch M1. Notice that the clock signal controlling the dummy switch is the complement of the signal controlling M1, and in addition, should also be slightly delayed.

Fig. 4.15 Dummy switch circuit used to minimize charge injection

When M1 turns off, half of the channel charge is injected toward the dummy switch, this explaining why the size of M2 is one-half that of M1. Although M2 is effectively shorted, a channel can still be induced by applying a voltage on the gate.

Therefore, the charge injected by M1 is essentially matched by the charge induced by M2, and the overall charge injection is canceled. Note what happens when M2 turns off. It will inject half of its charge in both directions. However, because the drain and source are shorted and M1 is on, all of the charge from M2 will be injected into the low-impedance, voltage-driven source, which is also charging Cload. Therefore, M2^，s charge injection will not affect the value of voltage on Cload.

Another method for counteracting charge injection and clock feedthrough is to replace the switch with a CMOS transmission gate (TG) in Fig. 4.16. This results in low changes in Vout because the complementary signals that are used will act to cancel each other. However, this approach requires precise control on the complementary clocks (the clocks must be switched at exactly the same time) and assumes that the input signal, Vout, is small since the symmetry of the turn-on and turn-off waveforms depend on the input signal.

Fig. 4.16 Use of complementary switches to reduce charge injection

4.4 Building Blocks

In this section, Low jitter clock generator, Phase-frequency detector (PFD), Charge Pump (CP), Voltage control oscillator (VCO), Random clock generator, lock detector (LD), Programmable Frequency Divider, Prescaler, loop filter and three-order sigma-delta would be introduced and transistor-level simulation to prove their function.

4.4.1 Low jitter clock generator, PFD, CP

This clock needs to have sufficiently low jitter in order not to increase the VCO output noise floor due to non-shaped jitter noise. Some design strategies are adopted to minimize clock jitter due to device and supply noise. Figure 4.17 shows the simplified circuit to generate the low jitter clock. To reduce common mode noise probably coupled to the testing board and to obtain the least amount of clock jitter

possible to generate the low jitter clock with sufficient driving capability because any extra stages generate extra device noise, hence larger clock jitter. To reduce the supply noise, a dedicated and clean supply is used solely for the low jitter clock generation circuit. Fig. 4.18 simulates its operation situation

Fig. 4.17 Low jitter on-chip clock generator

Fig. 4.18 Low jitter clock generator simulation

A common drawback for some phase frequency detector is a dead zone in the phase characteristic at the equilibrium point. The dead zone generates phase jitter because the control system does not change the control voltage when the phase error is within the dead zone. This influence can be improved by increasing the precision of the PFD. To reduce the dead zone and to overcome the speed limitation, we choose the dynamic phase frequency detector shown in Fig. 4.19 [25]. Compared with the conventional PFD, the transistor numbers are decreased to 12 and thus possesses smaller parasitic inherently. According to the phase difference between both input signals, UP is used to increase and DN is used to decrease the frequency of the output signal. Fig. 4.20 simulates its operation situation.

Fig. 4.19 Phase frequency detector

Fig. 4.20 The time diagram of the PFD

The implementation of a charge pump is illustrated in Fig. 4.21. The switch-at-gate charge pump has more stable output voltage than the switch-at-drain charge pump because it eliminates charge sharing and clock feed-through errors and thus reduces output voltage jitter. Although it may suffer from reviewed switching speed due to the large parasitic capacitance at the gate, we design the current flow such that it eliminates the parasitic charge. Cascade NMOS and PMOS are design to reduce channel length modulation. The current mismatch of the charge pump in the PLL generates a phase offset which increases spurs in the PLL output signals. When the current mismatch occurs in the charge pump, the amount of the phase offset is given by:

2 the reference clock period, the charge pump current, and the current mismatch of the charge pump, R is the resistor value in the loop filter, Kvco is the VCO gain, fref is the reference frequency for the PFD and fpl is the frequency of the pole in the loop filter respectively. Pr is the amount of reference spur. The Fig. 4.21 shows a charge pump circuit and charge pump current match. The Fig. 4.22 shows PFD and charge pump Dead zone. The Fig. 4.23 shows output voltage range of charge pump

Fig. 4.21 The charge pumps circuit and simulation

Fig. 4.22 Dead zone simulation of PFD with CP

Fig. 4.23 The output voltage range of charge pump 4.4.2 Voltage control oscillator (Ring VCO)

Fig. 4.24 Circuit implementation of the propose (a) delay cell (b) ring oscillator The circuit schematics of the proposed delay cell and the whole ring oscillator are shown in Fig. 4.24. The delay cell consist of one NMOS input pair (Mn1), one PMOS positive feedback pair (Mp1) for maintaining oscillator, one diode-connected PMOS (Mp2), and one PMOS transistor (Mb1) for frequency tuning. The ring oscillator consists of two delay cells for power-consumption and phase-noise minimization. The design guidelines that determine the delay-cell design are as follows.

A. High-Frequency Operation:

An NMOS input pair is used to maximize the transconductance-tocapacitance (gm=C) ratio to achieve high operating frequency with low power dissipation. To reduce the gm requirement and thus power dissipation, only parasitic capacitors of devices are utilized. Moreover, only two delay cells are included in the oscillator to

minimize the power consumption.

B. Wide Frequency-Tuning Range

A large tuning range is required to overcome the problem of process variation.

The operating frequency of a ring oscillator can be tuned by variable capacitor (varactor) or by variable load impedance. A varactor is typically implemented by p-n-junction, and therefore frequency-tuning range is limited to be within 10~ 20%.

In this design, frequency tuning is achieved by tuning the transconductance (gm) of the diode-connected PMOS devices Mp2. By controlling the current of Mb1, gm of Mp2 can be adjusted from zero to a value close to gm of Mp1. Therefore, over 50%

tuning range can be easily achieved.

C. Low Phase-Noise Performance

As phase noise is defined as the difference between carrier power and noise power, phase-noise performance can be improved by either increasing carrier power or reducing noise power. In the proposed design, the source nodes of devicesMp1 are directly connected to supply to eliminate current limitation of the output nodes and thus maximize output amplitude. Since output amplitude becomes large, transistors are turned off periodically. As shown in Fig. 4.25, noise current nn1, np1, np2 is zero when output amplitude is large. The carrier power is increased and the noise power is reduced simultaneously, and as a result, the phase-noise performance is improved [26].

Fig. 4.25 Delay cell waveforms and thermal noise current

For DTV system the VCO designs: In Fig. 4.26, the VCO design for the DTV system and Fig. 4.27, the simulation for HSPICE. The Fig. 4.26 (b) we add source follow extended frequency [27].

Fig. 4.26 The VCO design for the DTV system

Fig. 4.27 The VCO simulation for HSPICE

Fig. 4.28 Phase noise of the VCO

Fig. 4.29 The output swing with the PAD effect TABLE 4-1 Process corners simulation (DTV)

Process Corners TT FF FS SS SF

Frequency(GHz)

Band: (0000) 2.06~2.17 2.11~2.24 2.08~2.19 2.03~2.14 2.06~2.18 Frequency(GHz)

Band: (0001) 1.96~2.10 2.02~2.17 2.00~2.13 1.93~2.06 1.95~2.10 Frequency(GHz)

Band: (0011) 1.85~2.01 1.90~2.08 1.90~2.05 1.82~1.97 1.81~2.0 Frequency(GHz)

Band: (0110) 1.69~1.90 1.74~1.98 1.77~1.96 1.66~1.86 1.63~1.87 Frequency(GHz)

Band: (1100) 1.49~1.77 1.53~1.84 1.60~1.84 1.46~1.72 1.38~1.71 Frequency(GHz)

Band: (1110) 1.22~1.61 1.26~1.69 1.40~1.71 1.22~1.55 1.07~1.52 Frequency(GHz)

Band: (1111) 0.843~1.39 0.869~1.48 1.10~1.54 0.836~1.34 0.634~1.26

TABLE 4-2 Process corners simulation (DTV):

Process Corners TT FF FS SS SF

Frequency(GHz) 0.843~2.17 0.869~2.24 0.84~2.16 0.836~2.14 0.634~2.18 In Fig. 4.28, shows its phase noise performance. Fig. 4.29 shows the out swing is approach 650mV considering the PAD effect. Finally, we simulate the VCO tuning range in the different corner conditions shown in the Table 4-1 and Table 4-2.

For WIMAX (mobile) system, the VCO tuning range in Fig. 4.30. We simulate the VCO tuning range in the different corner conditions shown in the Table 4-3.

Fig. 4.30 The VCO tuning range (corner case: TT, FF, SS) TABLE 4-3 Process corners simulation (WIMAX mobile):

Process Corners TT FF SS

Frequency(GHz) 2.25~2.9 2.32~2.95 2.2~2.87 4.4.3 Programmable Frequency Divide, Prescaler, Loop filter

Programmable dividers have to operate at the highest VCO frequency.

Therefore, the choice of the divider architecture is essential for achieving low power dissipation and high design flexibility. Fig. 4.31 depicts the programmable frequency divider. These feedback lines enable simple optimization of power dissipation. Another advantage is that the topology of the different cells in the divider is the same, therefore facilitating layout work.

Fig. 4.31 The architecture of programmable frequency divider

The programmable divider can provide an output signal with a period of:

T_out =

(

2⁵+p4⋅2⁴+p3⋅2³+p2⋅2²+ p1⋅2¹+p0

)

×T_in (4.10) Therefore, this equation shows that the division ratios from 32 (if all pn=0) to 63 (if all pn=1) is achieved. The circuit of the 2/3 divider is shown in Fig. 4.32 (a).

The logic functions of the 2/3 cells are implemented with the Source Coupled Logic (SCL) structure presented in Fig. 4.32 (b). The logic tree combines a latch function with an AND gate [28].

Fig. 4.32 (a)Functional blocks and logic implementation of a 2/3 divider cell (b)SCL implementation of an AND gate combined with a latch function Because of the oscillatory frequency of the VCO is very high, we first employ a prescaler to decrease the input clock frequency of the following multi-modulus divider. Fig. 4.33(a) shows the block diagram of common 1/2 frequency divider using two D-latches in a master-slave configuration with negative feedback. In high speed operation, it’s usual practice to design the slave as the “dual of the master”, such that they can be driven by a single clock [29]. Nevertheless, duality will make one of the latches uses PMOS devices in the signal path, lowering the maximum operation speed. Razavi proposed a divider utilizing two identical D-latches, driving by complementary clocks [30], as illustrated in Fig. 4.33(b). The transmission gate in the non-inverted phase is to minimize the skew between CK andCK.

Fig. 4.33 Master-slave divider with (a) single clock (b) complementary clocks Fig. 4.34 shows the high speed divider circuit [30]. Each latch comprises two sense devices (M1, M2, M7, M8), a regenerative loop (M3, M4, M9, M10), and two pull-up devices (M5, M6, M11, M12). When the CK is high, M5 and M6 are off, and the master is in the sense mode. In the same time, M11 and M12 are on, and the slave is in the store mode. When CK changes to low, the reverse occurs. In Fig 4.35 shows VCO, Prescaler and Programmable dividers are linked simulation in HSPICE.

CK

Fig. 4.34 High speed, low voltage frequency divider

Fig. 4.35 VCO, Prescaler and Programmable dividers simulation

As we know, the loop filter mainly determines the noise and dynamic performance of the PLL. In order to effectively attenuate the reference spur, we adopt the 3^rd order loop filter. To decide the proper values of each element, the basic steps are as follows:

Fig. 4.36 Relationship between zero, poles, reference and loop bandwidth 1. As a rule, the relationship between zero, poles, and reference and loop bandwidth

are shown in Fig. 4.36. Deciding the proper values of open-loop unity-gain

3. Calculate the time constant T2.

T2 = 1 ^ω _c²

(

T 1 + T 3

)

^ (4.14) 4. Thus we can derive the value of each element.

( )

2 result is as we expect. It proves the above equations are precise enough to estimate PLL parameters.

Fig. 4.37 Bode plot of close loop PLL 4.4.4 Lock detector (LD), Random clock generator

We need a lock detector to switch the current paths and the voltage paths to facilitate the transient behavior. The implementation of lock detector circuit is shown in Fig. 4.38. The concept is very simple: we use two DFFs for Ref and Clk to sample each other. Two delay lines, T and 2T specify the locking window to judge if the two inputs are closed enough. Fig. 4.39 shows the timing diagram for explanation. The first DFF uses CLK as its sampling clock and Ref, which is delayed by T, as input data. Therefore, if the Ref leads Clk by more than T, the transition edge of the delayed Ref will go up earlier than that of Clk and this DFF would output logic 0 forQ. On the other hand, the second DFF adopts Clk, which is delayed by 2T, as sampling clock and Ref, which is delayed by T, as input data.

Hence, if the Ref lags Clk by more than T, logic 0 is generated in Q for the second DFF. After combining the outputs by the NAND gate, LDis low if the absolute value of phase difference for Ref and Clk is less than T and vice versa.

Fig. 4.38 Lock detector

Fig. 4.39 Timing diagram of lock detector

This detecting strategy describe above is quite simple. But now can we determine the delay of locked windows? If we allocate a large value for T, it means the lock detector would send a message, “the loop is locked”, to charge pump and spur-reduction control too early. If we chose T which is smaller than the static phase error, Ref and Clk never have chance to come closely enough and the lock detector always outputs an “unlocked”message to spur-reduction control.

Therefore, by considering the trade-off describe above, T is set to about 1.18ns to ensure stability. Fig 4.40 shows the circuit architecture Random clock generator. It consists D flip-flops and one XOR logic. Fig 4.41 shows simulation in HSPICE.

Fig. 4.40 Timing diagram of Random clock generator

Fig. 4.41 Random clock generator simulation 4.4.5 Three-order Sigma-Delta Modulator

In the actual implementation, the limited precision of the accumulators result in the loss of accuracy and minimum frequency resolution synthesizer can achieve. In general, the higher dynamic range accumulator provides better tracking on the desired mean value but increases the power consumption and chip area. For the other consideration of frequency resolution, the required frequency resolution of the system. To achieve this requirement, the data length of DSM (dynamic range of accumulator) should be as:

2

r a n g e L

f = f ≤ s y s t e m r e s o l u t i o n

 (4.18)

Where△f is the frequency resolution, frange is the output frequency range (i.e.

the product of reference frequency and division ratio of prescaler) and L is the data length of DSM. In this design, the reference frequency is 36MHz and 25MHz, the division ratio is 58 and 100 hence, the 10-bits of DSM are derived. Note that, the divide-by-2 prescaler causes a one-bit resolution loss. Therefore, the extra 1-bit should be added to data length of DSM for compensation. Then the frequency detail of circuit design will be discussed in the following two parts.

Fig. 4.42 Pipelined 3^rd-order Σ∆ modulator

Fig. 4.43 Noise cancellation network of MASH 1-1-1 DSM

From Fig. 4.43, we can find if we design the circuit intuitively, two 4-bits adders (B, D) and two 4-bits two^，s complement adders (A, C) are needed. However, in order to simplify design, we analyze each adder^，s logic states and design the decoder for the noise cancellation network instead. First of all, the adder A has three

From Fig. 4.43, we can find if we design the circuit intuitively, two 4-bits adders (B, D) and two 4-bits two^，s complement adders (A, C) are needed. However, in order to simplify design, we analyze each adder^，s logic states and design the decoder for the noise cancellation network instead. First of all, the adder A has three

在文檔中 應用於數位電視和WIMAX 之低相位雜訊三角積分調變頻率合成器 (頁 69-0)