Chapter 2 Fundamental of frequency synthesizers
2.3 Phase-Locked Loop (PLL) Fundamentals…
2.3.1 Phase Frequency Detector
Phase frequency can detector both phase and frequency difference between the reference signal and the output signal of the frequency divider. As shown in Fig. 2-6, if the frequency of A is greater than the frequency of B, then QA is high, but QB is still low. If the frequency of A and B are equal, then the circuit will check the phase difference between the two inputs, and generates a pulse equal to the phase difference at QA or QB (depends on which input has phase leading).
Fig. 2.6 (a) PFD block diagram (b) PFD state diagram (c) PFD timing diagram
Fig. 2-7(a), it shows a possible implementation of the above PFD. This circuit contains two reset table D-flip flops and a NAND gate. The input signals of A and B are as clock input and the input of two D-flip flops is always high. And we set the initial condition is QA=QB=0. If A is from 0 to 1, until B is from 0 to 1 and QB becomes high to make the two D-flip flops reset. And Fig. 2-7(b), shows the input-output characteristic of the PFD.
Fig. 2.7 (a) PFD implementation (b) PFD characteristic
Fig. 2-8(a) shows the PFD circuit. It is negative-trigger and has the same function as we discuss above. But it still has a drawback. When this type of PFD incorporated with charge pump circuit, it has a drawback that a dead zone exist, as shown in Fig. 2-8(b). If the reset signal is not delayed sufficiently, the output of charge pump will not change for small phase error, thus the dead zone translates to jitter in PLL and must be voided. In Fig. 2-8(a), the delay chain to increase delay of reset signal for eliminating dead zone.
Fig. 2.8 (a) Phase frequency detector (b) Dead zone in PFD 2.3.2 Charge pump
A PFD could not alone provide the exact voltage (or current) signal proportional to the phase difference at its inputs. A charge pump serves to convert the two digital output signals QA and QB of the PFD into charge flows whose quantity is proportional to the phase error. A passive filter then shape the output current signal of the charge pumps to suppress the useless messages buried in that signal.
A PFD together with a charge pump and a single capacitor C1 as the loop filter are shown in Figure 2.9, with the corresponding time-domain response shown as well. As a higher frequency than B or has the same frequency as B but with a leading phase, the charge pump sources a constant-valued current I1 through switch S1 into the capacitor, and the output voltage increases steadily. Similarly, if the frequency of input A is lower or the phase is lagging, the output waveform will be a steadily downward one. What happens if the inputs are exactly the same? Careful examination shows that QA and QB will have pulses of short duration. In this case, if the currents of the two current sources are the same in quantity, as indicated in
Figure 2.10, at the time that both S1 and S2 are on, the current sourced by I1 is exactly sunk by I2. Thus no net current will flow through C1 and Vout remains unchanged as in the case when both S1 and S2 are off.
Fig. 2.9 PFD with charge pump and the timing diagram
The phase frequency detector and the charge pump can be together characterized as:
Where IPUMP is the output current of the charge pump, ψe=ψA-ψB represents the phase error between the two PFD inputs and I=I1-I2 is the current value of the two current sources in the charge pump. This representation, however, is an approximate one. One should note that the charge pump is a discrete-time system, and it provides good approximation only when the loop bandwidth is much less than the input reference frequency.
The single-capacitor loop filter nevertheless has an infinite dc gain, which might unstablilize the close loop. To avoid instability, a resistor RP in series with CP is added, which in effect adds a LHP (left-half-plane) zero to the overall open-loop transfer function. The transfer function of the resolution loop filter is:
2
e p u m p
I I φ
= π (2.1)
Note that this representation indicates a conversion from an input current a output voltage, and thus is directly applicable in conjunction with Equation. (2.1).
Fig. 2.10 Addition of a zero to a charge pump 2.3.3 Voltage-Controlled Oscillator
Many applications need that the oscillators be “tunable”. The most popular circuit is the voltage-controlled oscillator, whose frequency is a linear function of its input control voltage. The transfer function is as follows:
Hereω0is the free running frequency, KVCO is gain or sensitivity of the VCO, (usually in rad/s/V). Next, we want to derive the phase transfer function:
Only the second term of the total phase is of interest. We call
0 t
VCO cont
K
∫
V dt as the “excess phase”, denoted byφex. In fact, in the analysis of PLLs, we respect the VCO as a system whose input as the control voltage and output as the excess phase.If the system is LTI, then we get:
Therefore the VCO acts as an ideal integrator, providing a pole at s = 0 in the open loop transfer function in the PLL.
2.3.4 Loop Filter
Fig. 2.11 PLL-based frequency synthesizer linear model
However, before further examining the loop filter, linear models of the PLL-based frequency synthesizer should be established. With proper characteristic of each function block, the close-loop behavior of frequency synthesizers can be analyzed. A linear model of a charge-pump PLL-based frequency synthesizer is shown in Fig. 2.11. Note that the input and output signals are phase (rad/s). Phase errorφe, the difference between the input phase φin and the feedbackφfb, is extracted by the PFD, which is represented by a simple PLL in the linear model. The charge pumps (CP) then translate φe into a current signal with a gain of IP/2π, where IP is the pump current. This current signal (A) flows into the passive filter (Ω ), and is converted to voltage signal (V) at the control input of the VCO. The VCO generates an output signal whose frequency is related to the control input voltage with a gain of KVCO (Hz/V). Since the phase signal rather than frequency signal is the variable in this linear model, the VCO block include a“1/ s”term that integrates the frequency signal to derive the phase signal. The frequency divider in the feedback path is still a sample“1/ M”factor since division in frequency domain has the same effect in phase domain. Hence, the open-loop transfer function can be represented as:
2 1 transfer function, can be found assuming that K is much greater than wz:
Thus the open-loop transfer function can be rewritten as:
( ) s 2wz
G s K
s
= ⋅ + (2.10)
The simplest LPF is to connect a capacitor to the control voltage. The open-loop transfer function is derived as follows:
1
Since the loop gain has two poles at the origin, this topology is called a “type II” PLL. It is unstable because the loop gain has two poles at the origin. As illustrated in Fig. 2.12(a), each integrator provides constant 90phase shift. Thus the system will oscillate at the unit-gain frequency. So, we have to add a zero to increase phase margin.
We can thus add a resistor in series with the original capacitor. The open-loop transfer function is derived as follows:
1 severe problem occurred in such PLLs. Due to the resistor in series with capacitor, each time a current is injected into the loop filter and then produces large voltage jump. It makes ripples of control voltage of VCO and degrades the purity of the output frequency spectrum.
20log HOPEN 20log HOPEN
Fig. 2.12 (a) Loop gain of simple PLL (b) addition of zero
We can ease this effect by adding a second capacitor in parallel withRPandCP. The loop filter is now of 2nd order and the open loop transfer function of PLL now is of third-order and has stability problem, as shown in Fig. 2.13 (a). But if we makeC2is about one-fifth to one-tenth ofCP, the open-loop transfer function is near the second-order and would be stable.
2
where add additional LPF to suppress the spur that is frefoffset from the carrier frequency, as shown in Fig. 2.13 (b). The loop filter transfer function is
2 significantly attenuate the spurs. However, it must be at least five times higher than the loop bandwidth, or the loop will almost assuredly become unstable.
Fig. 2.13 (a) 2nd order loop filter (b) 3rd order loop filter 2.3.5 Frequency Divider
Frequency dividers are used to synthesize a high frequency LO from a precise low frequency crystal oscillator. The output frequency fdiv equals the input frequency fin divided by an integer number. From this information we could derive a model for
the divider in the phase domain.
The phase θin of the input signal is given by
And the instantaneous frequency of the input signal is:
And the phase of the output signal can now be found as:
2.4 Noise Analysis of the PLL Synthesizer
The job of any frequency synthesizer is to generate a spectrally pure output signal. An ideal periodic output in the frequency domain has only an impulse at the fundamental frequency and perhaps some other impulse energy at DC and harmonic.
In the actual oscillator implementation, the zero crossings of the periodic wave vary with time as shown in Fig. 2.14. This varying of the zero crossings is known as time domain jitter.
Fig. 2.14 Periodic signal with jitter
A PLL-based frequency synthesizer suffers from introduced at input or
generate by the other building blocks. It is important to learn how different noise sources affect the noise performance of the output signal. The sources of noise may be classified into two types: (1) the noise at input, and (2) the noise of VCO.
2.4.1 Input Noise Source
An input reference signal with phase noise can be modeled in the PLL as shown in Fig. 2.15(a) [5].
The input noise, Φin, is treated as an input signal and the same PLL transfer function for the input noise transfer function. The input phase noise transfer function is plotted in Fig. 2.15(b).
Fig. 2.15 (a) PLL Input Phase Noise Model (b) Bode plot normalized transfer function
The input phase is shaped by the low-pass characteristic of the second-order PLL. In order to reduce the phase noise in the output signal due to the input phase noise it is desired to make the PLL bandwidth as narrow as possible. Notice that the input noise is amplifier by a factor of N. If input noise is a concern, the lowest
input phase noise is not a concern because the reference signal generally comes from a low phase noise crystal oscillator.
2.4.2 Noise of VCO
The phase noise of the VCO can be modeled as Fig. 2.16(a) [5]. The VCO phase noise, VCON, is treated as an input signal and following transfer function is plotted in Fig. 2.16(b).
The VCO phase noise is shaped by a high-pass characteristic by the second-order PLL. In order to reduce the phase noise in the output signal due to the VCO phase noise it is desirable to make the PLL bandwidth as wide as possible.
Here a tradeoff regarding loop bandwidth position and its effect on input phase noise contribution and VCO phase noise contribution is observed. The optimum loop bandwidth depends on the application. It is optimal to have a narrow loop bandwidth for input noise performance. cycle fluctuations in the power supply[7][8]. With the VCO contributing significant phase noise it is optimal to make the loop bandwidth as wide as possible.
2
Fig. 2.16 (a) Noise transfer function of a PLL from VCO to output (b) Bode plot of the normalized transfer function
The total phase noise can be derived by adding the above two eventual phase noises, as shown in Fig. 2.17. It is obviously that when the frequencies nears carrier, the REF in the closed loop dominate the total phase noise. Otherwise, the VCO dominates. If we want to suppress the phase noise of REF, we can decrease the BW.
However, it will raise the phase noise of VCO. On the contrary, increasing the BW will suppress the phase noise of VCO but raise the phase noise of Ref. It is a trade off. How we decide the best BW is important.
2
1 f
3
1 f
1 f
Fig. 2.17 Total output phase noise
Chapter 3
Fractional-N PLL
3.1 The Fractional Mechanism
Before studying the fractional architecture, we make an observation. Suppose, as shown in Fig. 3.1, a pulse is removed every TP seconds from a periodic signal x(t) that has a frequency f1. The resulting waveform, y(t) then exhibits f1‧TP-1 pulses every TP seconds, i.e., y (t) has an “average”frequency equal to f1-1/TP. This method can be used to vary the average frequency of a signal by small steps. We should note, however, that f (t) is not a strictly periodic signal. The idea of removing pulses nevertheless useful in fine-step frequency synthesis.
Fig. 3.1 Periodic removal of a pulse from a periodic waveform
Fig. 3.2(a) shows simple fractional-N architecture. In addition to the PFD, LPF, and VCO, the loop incorporates a pulse remover, a circuit that blocks one input pulse upon assertion of the remove command. Since under locked condition the two
frequencies presented to the phase detector must be equal, the average output frequency of the pulse remover equals fref, and hence fout=fref+1/TP, where TP is the periodic with which the remove command is applied. Note that fout can vary by a fraction of fref because the frequency fp=1/TP can be derived from fref by simply division. Provided by a crystal oscillator, fref is typical limited to a few tents of megahertz. Thus, as shown in Fig. 3.2(b), a fractional-N synthesizer incorporates a divider in the feedback to generate high output frequencies.
Fig. 3.2 (a) simple fractional-N synthesizer (b) use of divider in the loop While the original fractional-N topology was based on the pulse remover concept [9], modern implementations of this architecture operate on a somewhat different principle. Depicted in Fig. 3.3, such a synthesizer replaces the pulse remover and the divider of Fig. 3.2 (b) with a dual-modulus prescaler. If the prescaler divides by N for TN output pulses (of the VCO) and by N+1 for TN+1 output pulses, shown in Fig. 3.3 (b), then the equivalent divide ratio is shown as
1 ( 1)
This value can vary between N and N+1 in fine steps by proper choice of A and B. The resulting modulus is sometimes written as N.f, where the dot denotes a decimal point and N and f represent the integer and fractional parts of the modulus.
Fig. 3.3 (a) Fractional-N synthesizer using a dual-modulus divider, (b)Timing diagram
3.2 The First Order Fractional-N Synthesizer
Fig. 3.4 shows the fractional-N PLL [10] which the accumulator and the cycle swallower become part of the circuit. The operation principle of this structure is the same as the one described in Fig. 3.3(b). Fig. 3.5 shows the detail circuits and timing diagram of the cycle swallower. To operate, a chain of VCO pulses serves as the clock for the flip-flop. A swallow trigger signal is illustrated generally as being
edge of swallow trigger and output a Q1 pulse to flip-flop. When the next negative edge of VCO signal appears at the clock of flip-flop, the Q2 output goes negative.
This output resets flip-flop and also provides an “off”input to AND gate. Thus, the next VCO pulse will not appear at the output of AND gate; that is, has been swallowed. The negative edge of pulse again triggers flip-flop allowing the subsequent pulses of the VCO signal to pass through AND gate.
Fig. 3.4 Fractional-N synthesizer using a cycle swallower and an accumulator
Fig. 3.5 (a) Cycle swallower circuit, (b) Its timing diagram
From Fig. 3.3(b), this periodic modification of the divider modulus gives rise to a sawtooth phase error (Fig. 3.6). If unfiltered, the phase error causes severe spurious tones-fractional spurs at all multiples of the offset frequency (.f×fref).
Fig. 3.6 Sawtooth phase error for the first order fractional-N synthesis
3.3 The Second Order Fractional-N Synthesizer
The fractional spurs in the above-mentioned averaging fractional-N synthesis are a serious problem. An important can be achieved by analog compensation of the phase error [11, 12, 13]. The output of the phase register of the digital accumulator is a measure for the phase error. The phase register is a kind of “bookkeeping system”that tracks the phase advancement of the VCO for every reference cycle.
Due to the loop integration the actual phase detector output becomes an analog sawtooth waveform which is mentioned in Fig.3.7.Using a DAC (Digital-to-Analog) the staircase output of the phase register can be converted to an analog sawtooth current, scaled by A (Fig. 3.7) to match the phase error. By summing the phase detector output and the DAC output on the loop filter capacitors, the AC component is in the ideal case removed from the phase error. The VCO output is now only driven by the wanted DC phase error, canceling all fractional spurs in the output spectrum.
However, this method has several disadvantages. First of all, the maximum
amplitude of the phase error depends on fref, such that the DAC output amplitude must be variable, while its input is constant. Secondly, the sampling frequency of the DAC can be rather high. To have fast setting (large loop bandwidth), the fref can easily be some tens of MHz. The sampling frequency of the DAC must be at least 2×fref, for a full Nyquist DAC, to be able to compensate spurs up to the reference frequency. To have a spurious suppression of at least -70dB, required in most telecommunication system, the accuracy of the DAC must be around 8 bits [14].
This occupies a larger chip area and dissipates the power consumption. Thirdly, due to matching issues, the accuracy of the cancellation is limited, requiring external adjustment and calibration. Therefore, the analog compensation method is not a viable solution for all integration of frequency synthesizers for wireless communication systems in CMOS technology.
Fig. 3.7 The analog phase interpolator
3.4 The Third Order Fractional-N Synthesizer
The next significant evolutionary step for fractional-N synthesizer will be an all-digital implementation, known as delta-sigma modulator (DSM), eliminating spurious digitally and allow good phase noise performance by digitally noise-shaping techniques, as shown in Fig. 3.8 [15]. The DSM architecture used in this paper terms as a Multistage Noise Shaping (MASH) which is cascaded by three
first-order modulator to ensure the stability. It is assumed random to model each 1-bit quantizes as a unity gain element with added quantization noise. N.F is the desired rational divide ratio and Ndiv (k) is the actual sequence presented to the integer divider. The transfer function is
( ) ( ) (1 1 3) ( )
Ndiv z N f z z E 3 z
q
= + − − ×
⋅ (3.2)
In a locked PLL,
1 3 3
( ) ( ) ( )(1 )
out div ref
out ref q ref
f N f
F z N F z⋅ f E z z− f
= ×
= × + − × (3.3)
Where the first term is the desired frequency and the second term represents frequency noise due to delta-sigma modulation.
By converting to the frequency domain and generating to any number of modulators, the power spectral (PSD) which is considered with small offset ranges compared to the reference frequency is [15].
2 ( 1) accumulator is a compact realization of the delta-sigma modulator as shown in Fig.
3.8 (b). This architecture leads to the all digital implementation easily. Regardless of the advantages of low phase noise, low reference feedthrough spurs, fast tuning speed, and small step size for this architecture, fractional spurs is a design issue to overcome. In addition, when the DSM is fed with a DC input, the quantized signal bounces between two levels and may be periodic. The structure of such quantization is known as pattern noise, or idle tones. Since this is the desired architecture for the fractional-N synthesizer in this thesis, we will consider this problem and figure out how to solve these problems?
3.4.1 Delta-sigma modulators
DSMs are basically divided into two types: single-stage and cascaded. Digital
DSMs are basically divided into two types: single-stage and cascaded. Digital