Chapter 4 Spur-reduction Frequency Synthesizers for DTV and WIMAX
4.4 Building Blocks
4.4.1 Low jitter clock generator, PFD, CP
This clock needs to have sufficiently low jitter in order not to increase the VCO output noise floor due to non-shaped jitter noise. Some design strategies are adopted to minimize clock jitter due to device and supply noise. Figure 4.17 shows the simplified circuit to generate the low jitter clock. To reduce common mode noise probably coupled to the testing board and to obtain the least amount of clock jitter
possible to generate the low jitter clock with sufficient driving capability because any extra stages generate extra device noise, hence larger clock jitter. To reduce the supply noise, a dedicated and clean supply is used solely for the low jitter clock generation circuit. Fig. 4.18 simulates its operation situation
Fig. 4.17 Low jitter on-chip clock generator
Fig. 4.18 Low jitter clock generator simulation
A common drawback for some phase frequency detector is a dead zone in the phase characteristic at the equilibrium point. The dead zone generates phase jitter because the control system does not change the control voltage when the phase error is within the dead zone. This influence can be improved by increasing the precision of the PFD. To reduce the dead zone and to overcome the speed limitation, we choose the dynamic phase frequency detector shown in Fig. 4.19 [25]. Compared with the conventional PFD, the transistor numbers are decreased to 12 and thus possesses smaller parasitic inherently. According to the phase difference between both input signals, UP is used to increase and DN is used to decrease the frequency of the output signal. Fig. 4.20 simulates its operation situation.
Fig. 4.19 Phase frequency detector
Fig. 4.20 The time diagram of the PFD
The implementation of a charge pump is illustrated in Fig. 4.21. The switch-at-gate charge pump has more stable output voltage than the switch-at-drain charge pump because it eliminates charge sharing and clock feed-through errors and thus reduces output voltage jitter. Although it may suffer from reviewed switching speed due to the large parasitic capacitance at the gate, we design the current flow such that it eliminates the parasitic charge. Cascade NMOS and PMOS are design to reduce channel length modulation. The current mismatch of the charge pump in the PLL generates a phase offset which increases spurs in the PLL output signals. When the current mismatch occurs in the charge pump, the amount of the phase offset is given by:
2 the reference clock period, the charge pump current, and the current mismatch of the charge pump, R is the resistor value in the loop filter, Kvco is the VCO gain, fref is the reference frequency for the PFD and fpl is the frequency of the pole in the loop filter respectively. Pr is the amount of reference spur. The Fig. 4.21 shows a charge pump circuit and charge pump current match. The Fig. 4.22 shows PFD and charge pump Dead zone. The Fig. 4.23 shows output voltage range of charge pump
Fig. 4.21 The charge pumps circuit and simulation
Fig. 4.22 Dead zone simulation of PFD with CP
Fig. 4.23 The output voltage range of charge pump 4.4.2 Voltage control oscillator (Ring VCO)
Fig. 4.24 Circuit implementation of the propose (a) delay cell (b) ring oscillator The circuit schematics of the proposed delay cell and the whole ring oscillator are shown in Fig. 4.24. The delay cell consist of one NMOS input pair (Mn1), one PMOS positive feedback pair (Mp1) for maintaining oscillator, one diode-connected PMOS (Mp2), and one PMOS transistor (Mb1) for frequency tuning. The ring oscillator consists of two delay cells for power-consumption and phase-noise minimization. The design guidelines that determine the delay-cell design are as follows.
A. High-Frequency Operation:
An NMOS input pair is used to maximize the transconductance-tocapacitance (gm=C) ratio to achieve high operating frequency with low power dissipation. To reduce the gm requirement and thus power dissipation, only parasitic capacitors of devices are utilized. Moreover, only two delay cells are included in the oscillator to
minimize the power consumption.
B. Wide Frequency-Tuning Range
A large tuning range is required to overcome the problem of process variation.
The operating frequency of a ring oscillator can be tuned by variable capacitor (varactor) or by variable load impedance. A varactor is typically implemented by p-n-junction, and therefore frequency-tuning range is limited to be within 10~ 20%.
In this design, frequency tuning is achieved by tuning the transconductance (gm) of the diode-connected PMOS devices Mp2. By controlling the current of Mb1, gm of Mp2 can be adjusted from zero to a value close to gm of Mp1. Therefore, over 50%
tuning range can be easily achieved.
C. Low Phase-Noise Performance
As phase noise is defined as the difference between carrier power and noise power, phase-noise performance can be improved by either increasing carrier power or reducing noise power. In the proposed design, the source nodes of devicesMp1 are directly connected to supply to eliminate current limitation of the output nodes and thus maximize output amplitude. Since output amplitude becomes large, transistors are turned off periodically. As shown in Fig. 4.25, noise current nn1, np1, np2 is zero when output amplitude is large. The carrier power is increased and the noise power is reduced simultaneously, and as a result, the phase-noise performance is improved [26].
Fig. 4.25 Delay cell waveforms and thermal noise current
For DTV system the VCO designs: In Fig. 4.26, the VCO design for the DTV system and Fig. 4.27, the simulation for HSPICE. The Fig. 4.26 (b) we add source follow extended frequency [27].
Fig. 4.26 The VCO design for the DTV system
Fig. 4.27 The VCO simulation for HSPICE
Fig. 4.28 Phase noise of the VCO
Fig. 4.29 The output swing with the PAD effect TABLE 4-1 Process corners simulation (DTV)
Process Corners TT FF FS SS SF
Frequency(GHz)
Band: (0000) 2.06~2.17 2.11~2.24 2.08~2.19 2.03~2.14 2.06~2.18 Frequency(GHz)
Band: (0001) 1.96~2.10 2.02~2.17 2.00~2.13 1.93~2.06 1.95~2.10 Frequency(GHz)
Band: (0011) 1.85~2.01 1.90~2.08 1.90~2.05 1.82~1.97 1.81~2.0 Frequency(GHz)
Band: (0110) 1.69~1.90 1.74~1.98 1.77~1.96 1.66~1.86 1.63~1.87 Frequency(GHz)
Band: (1100) 1.49~1.77 1.53~1.84 1.60~1.84 1.46~1.72 1.38~1.71 Frequency(GHz)
Band: (1110) 1.22~1.61 1.26~1.69 1.40~1.71 1.22~1.55 1.07~1.52 Frequency(GHz)
Band: (1111) 0.843~1.39 0.869~1.48 1.10~1.54 0.836~1.34 0.634~1.26
TABLE 4-2 Process corners simulation (DTV):
Process Corners TT FF FS SS SF
Frequency(GHz) 0.843~2.17 0.869~2.24 0.84~2.16 0.836~2.14 0.634~2.18 In Fig. 4.28, shows its phase noise performance. Fig. 4.29 shows the out swing is approach 650mV considering the PAD effect. Finally, we simulate the VCO tuning range in the different corner conditions shown in the Table 4-1 and Table 4-2.
For WIMAX (mobile) system, the VCO tuning range in Fig. 4.30. We simulate the VCO tuning range in the different corner conditions shown in the Table 4-3.
Fig. 4.30 The VCO tuning range (corner case: TT, FF, SS) TABLE 4-3 Process corners simulation (WIMAX mobile):
Process Corners TT FF SS
Frequency(GHz) 2.25~2.9 2.32~2.95 2.2~2.87 4.4.3 Programmable Frequency Divide, Prescaler, Loop filter
Programmable dividers have to operate at the highest VCO frequency.
Therefore, the choice of the divider architecture is essential for achieving low power dissipation and high design flexibility. Fig. 4.31 depicts the programmable frequency divider. These feedback lines enable simple optimization of power dissipation. Another advantage is that the topology of the different cells in the divider is the same, therefore facilitating layout work.
Fig. 4.31 The architecture of programmable frequency divider
The programmable divider can provide an output signal with a period of:
Tout =
(
25+p4⋅24+p3⋅23+p2⋅22+ p1⋅21+p0)
×Tin (4.10) Therefore, this equation shows that the division ratios from 32 (if all pn=0) to 63 (if all pn=1) is achieved. The circuit of the 2/3 divider is shown in Fig. 4.32 (a).The logic functions of the 2/3 cells are implemented with the Source Coupled Logic (SCL) structure presented in Fig. 4.32 (b). The logic tree combines a latch function with an AND gate [28].
Fig. 4.32 (a)Functional blocks and logic implementation of a 2/3 divider cell (b)SCL implementation of an AND gate combined with a latch function Because of the oscillatory frequency of the VCO is very high, we first employ a prescaler to decrease the input clock frequency of the following multi-modulus divider. Fig. 4.33(a) shows the block diagram of common 1/2 frequency divider using two D-latches in a master-slave configuration with negative feedback. In high speed operation, it’s usual practice to design the slave as the “dual of the master”, such that they can be driven by a single clock [29]. Nevertheless, duality will make one of the latches uses PMOS devices in the signal path, lowering the maximum operation speed. Razavi proposed a divider utilizing two identical D-latches, driving by complementary clocks [30], as illustrated in Fig. 4.33(b). The transmission gate in the non-inverted phase is to minimize the skew between CK andCK.
Fig. 4.33 Master-slave divider with (a) single clock (b) complementary clocks Fig. 4.34 shows the high speed divider circuit [30]. Each latch comprises two sense devices (M1, M2, M7, M8), a regenerative loop (M3, M4, M9, M10), and two pull-up devices (M5, M6, M11, M12). When the CK is high, M5 and M6 are off, and the master is in the sense mode. In the same time, M11 and M12 are on, and the slave is in the store mode. When CK changes to low, the reverse occurs. In Fig 4.35 shows VCO, Prescaler and Programmable dividers are linked simulation in HSPICE.
CK
Fig. 4.34 High speed, low voltage frequency divider
Fig. 4.35 VCO, Prescaler and Programmable dividers simulation
As we know, the loop filter mainly determines the noise and dynamic performance of the PLL. In order to effectively attenuate the reference spur, we adopt the 3rd order loop filter. To decide the proper values of each element, the basic steps are as follows:
Fig. 4.36 Relationship between zero, poles, reference and loop bandwidth 1. As a rule, the relationship between zero, poles, and reference and loop bandwidth
are shown in Fig. 4.36. Deciding the proper values of open-loop unity-gain
3. Calculate the time constant T2.
T2 = 1 ω c2
(
T 1 + T 3)
(4.14) 4. Thus we can derive the value of each element.
( )
2 result is as we expect. It proves the above equations are precise enough to estimate PLL parameters.
Fig. 4.37 Bode plot of close loop PLL 4.4.4 Lock detector (LD), Random clock generator
We need a lock detector to switch the current paths and the voltage paths to facilitate the transient behavior. The implementation of lock detector circuit is shown in Fig. 4.38. The concept is very simple: we use two DFFs for Ref and Clk to sample each other. Two delay lines, T and 2T specify the locking window to judge if the two inputs are closed enough. Fig. 4.39 shows the timing diagram for explanation. The first DFF uses CLK as its sampling clock and Ref, which is delayed by T, as input data. Therefore, if the Ref leads Clk by more than T, the transition edge of the delayed Ref will go up earlier than that of Clk and this DFF would output logic 0 forQ. On the other hand, the second DFF adopts Clk, which is delayed by 2T, as sampling clock and Ref, which is delayed by T, as input data.
Hence, if the Ref lags Clk by more than T, logic 0 is generated in Q for the second DFF. After combining the outputs by the NAND gate, LDis low if the absolute value of phase difference for Ref and Clk is less than T and vice versa.
Fig. 4.38 Lock detector
Fig. 4.39 Timing diagram of lock detector
This detecting strategy describe above is quite simple. But now can we determine the delay of locked windows? If we allocate a large value for T, it means the lock detector would send a message, “the loop is locked”, to charge pump and spur-reduction control too early. If we chose T which is smaller than the static phase error, Ref and Clk never have chance to come closely enough and the lock detector always outputs an “unlocked”message to spur-reduction control.
Therefore, by considering the trade-off describe above, T is set to about 1.18ns to ensure stability. Fig 4.40 shows the circuit architecture Random clock generator. It consists D flip-flops and one XOR logic. Fig 4.41 shows simulation in HSPICE.
Fig. 4.40 Timing diagram of Random clock generator
Fig. 4.41 Random clock generator simulation 4.4.5 Three-order Sigma-Delta Modulator
In the actual implementation, the limited precision of the accumulators result in the loss of accuracy and minimum frequency resolution synthesizer can achieve. In general, the higher dynamic range accumulator provides better tracking on the desired mean value but increases the power consumption and chip area. For the other consideration of frequency resolution, the required frequency resolution of the system. To achieve this requirement, the data length of DSM (dynamic range of accumulator) should be as:
2
r a n g e L
f = f ≤ s y s t e m r e s o l u t i o n
(4.18)
Where△f is the frequency resolution, frange is the output frequency range (i.e.
the product of reference frequency and division ratio of prescaler) and L is the data length of DSM. In this design, the reference frequency is 36MHz and 25MHz, the division ratio is 58 and 100 hence, the 10-bits of DSM are derived. Note that, the divide-by-2 prescaler causes a one-bit resolution loss. Therefore, the extra 1-bit should be added to data length of DSM for compensation. Then the frequency detail of circuit design will be discussed in the following two parts.
Fig. 4.42 Pipelined 3rd-order Σ∆ modulator
Fig. 4.43 Noise cancellation network of MASH 1-1-1 DSM
From Fig. 4.43, we can find if we design the circuit intuitively, two 4-bits adders (B, D) and two 4-bits two，s complement adders (A, C) are needed. However, in order to simplify design, we analyze each adder，s logic states and design the decoder for the noise cancellation network instead. First of all, the adder A has three states (-1, 0 and 1), as shown as Table 4-4:
TABLE 4-4 Noise cancellation Network coding (A)
C2 C2-1
Decimal number 2’s complement
0 0 0 000
0 1 -1 111
1 0 1 001
1 1 0 000
Observe the 2’s complement table, we can find that the highest two bits are the same. So, we can simplify the out of adder A as
We check the adder B where C1 is added to the output of adder A. Only three half-adders are used here and adder B’s output is tabulated inTable 4-5. Next, we check the output of adder C in Fig. 4.43. The output of B and it，s 2，s complement value should be added in the last cycle operation. Output of adder B has only four states (001, 000, 111 and 010), and the 2，s complement transformation is tabulated in Table 4-6.
TABLE 4-5 Noise cancellation Network coding (B)
C2 C2-1
TABLE 4-6 Noise cancellation Network coding (C) B，s output 2，s complement
001 111
000 000
111 001
010 110
With cautious supervision, the two MSB are the same and equal to the result of the two LSB of adder B，s output to have XOR operation. And the LSB of 2，s complement is equal to the LSB of adder B，s output. Therefore, the 2，s complement transformation with only one XOR gate and only three adders with one XOR gate are necessary in adder C. The output states of adder C are also tabulated in Table 4-7.
Finally, the adder D can be decoded with a few logic gates. And the control signal
1
corresponding to DSM output is as shown in Table 4-8.
TABLE 4-7 Noise cancellation Network coding (D) Decimal number C，s output
TABLE 4-8 Noise cancellation Network coding (E) DSM output
According to Table 4-7 and Table 4-8, an inverter is connected to the MSB of adder C，s output and the resulting output transmitted with two LSB into a 3-bits adder. And the MSB of control signal is the carry output of the 3-bits adder. From the above analysis the total error cancellation circuit is demonstrated in Fig. 4.44.
Fig. 4.44 Realization of the noise cancellation network
4.5 Fractional-N Frequency Synthesizer System
Fig. 4.2 shows architecture of DTV based on three-order Σ∆ modulator. Fig.
4.45 (a) shows the VCO control voltage. We can obviously find that the control voltage is stability. Fig. 4.45 (b) shows the carrier spectra, the reference spur about 65dbm.
Fig. 4.45 (a) VCO control voltage and (b) Out Spectrum when LO is 2.088GHz Fig. 4.3, Fig. 4.4 shows architecture of WIMAX (mobile) based on three-order Σ∆ modulator. Fig. 4.46 (a), Fig. 4.47 (a) shows the VCO control voltage. We can obviously find that the control voltage is stability. Fig. 4.46 (b), Fig. 4.47 (b) shows the carrier spectra, the reference spur about 71dbm, 70dbm.
The random charge PLL in Fig. 4.5 shows architecture of WIMAX (mobile) based on three-order Σ∆ modulator. Fig. 4.48 (a) shows the VCO control voltage.
We can obviously find that the control voltage is stability. Fig. 4.48 (b) shows the carrier spectra, the reference spur about 80dbm.
Fig. 4.46 (a) VCO control voltage, sample capacitor, lock detector and random clock (b) Out Spectrum is 2.5GHz
Fig. 4.47 (a) VCO control voltage, sample capacitor, lock detector and random clock (b) Out Spectrum is 2.5GHz
Fig. 4.48 (a) VCO control voltage and lock detector (b) Out Spectrum is 2.5GHz
The closed-loop simulation results in Fig. 4.45, Fig. 4.46, Fig. 4.47 and Fig.
4.48, using HSPICE are done. The parameters and performance summaries of the frequency synthesizer are listed in Table 4-9.
TABLE 4-9 Fractional-N PLL performance summaries
Chapter 5
Testing Setup and Experimental Results
5.1 Experimental Results
The proposed Σ∆ frequency synthesizer has been fabricated in a 0.18-µm 1P6M mixed-signal technology. Shown in Fig. 5.1(a), 5.2(a) is the layout and 5.1(b), 5.2(b) is the die photo of the chip. This chip occupies an area of 1.027*1.026mm2, 1.14 X 1.14mm2. Shown in Fig. 5.3(a), Fig. 5.3(b), Fig. 5.3(c), is representation from Fig.
4.3, Fig. 4.4, and Fig. 4.5.
(a) (b) Fig. 5.1 (a) Layout (b) Die photo
(a) (b) Fig. 5.2 (a) Layout (b) Die photo
(a) (b)
(c)
Fig. 5.3 (a) Layout1 (b) Layout2 (c) Layout3
5.2 Test Setup
The fabricated synthesizer was tested to determine its performance.
Measurement was performed with raw dies mounted on the PCB to prevent the parasitic effect of the package. Because the synthesizer is a mixed-mode system, we separate the powers and grounds of digital and analog parts. Then, we connect the ground of analog part and that of digital part with an inductor. The inductor shorts the DC voltage of the digital and analog grounds, while preventing the high-frequency noise in the digital circuit from coupling to the analog circuit by their grounds.
The analog and digital powers are generated by LM317 adjustable regulators as shown in Figure 5.4. The regulator circuit is easy to use and the output voltage could be predicted by equation (5.1)
VO U T = 1 . 2 5 1
(
+ R1 R 2)
+ IA D J iR2 (5.1)The IADJ is the DC current that flows out of the ADJ terminal of the regulator.
Besides, the capacitors C1 and C2 are the bypass capacitors.
Fig. 5.4 LM317 regulator
The outputs of the regulators are bypassed on the PCB with the parallel combination capacitors then connected to the chip. The bypass filter network is combined by 10µF, 1µF, 0.1µF and 0.01µF capacitors as shown in Fig. 5.5. The
arrangement can provide decoupling of both low-frequency noise with large amplitudes and high-frequency noise with small amplitudes [31].
Fig. 5.5 Bypass filter at the regulator output
The measurement setup of the synthesizer is shown in Fig. 5.6. The input clock is produced from the signal generator (Agilent 81110A). The output spectrum is observed by a Spectrum Analyzer (Agilent E4440A).The testing PCB is shown in Fig. 5.7.
Fig. 5.6 Measurement setup of the synthesizer
Fig. 5.7 The testing PCB in the synthesizer
5.3 Measurement Results
Fig. 5.8 shows the measured transfer curve of VCO. The measure tuning range is 2.11GHz~0.732 GHz, 2.86GHz~2.1GHz for VCO. The DTV system has 7 bands
Fig. 5.8 Measure VCO transfer curve
(a) (b)
Fig. 5.9 Measured output spectrum of WIMAX (mobile) synthesizer
(a) 2.5MHz offset (b) 3MHz offset
-36.9-10log (30‧103) =-81.67dBc/Hz -42.56-10log (30‧103) =-87.33dBc/Hz Fig. 5.10 Measured phase noise of lock synthesizer for WIMAX
(a) (b)
Reference spur=-36.76dBc Reference spur=-43.49dBc Fig. 5.11 Measured reference spur of lock synthesize
Fig. 5.12 Measured output spectrum of divide in lock 2.5GHz
Fig. 5.13 Measured output spectrum of DTV synthesizer
(a) 1MHz offset (b) 3MHz offset
-41.62-10log (10‧103) =-81.62dBc/Hz -57.1-10log (10‧103) =-97.1dBc/Hz Fig. 5.14 Measured phase noise of lock synthesizer for DTV
-58.51-10log (100‧103) =-108.51dBc/Hz Reference spur=-69.78dBc
Fig. 5.15 Measured phase noise and reference spur of lock synthesizer for DTV
5.4 Measured Summary
In Fig. 5.9 shows the measured output spectrum of WIMAX (mobile) synthesizer where the PLL is locked. The output frequency is 2.5GHz, 2.7GHz which equals dividing ratio of 100, 108. In Fig. 5.11 the measured value of reference spur, there are 36.76dBc, 43.49dBc.Table 5.1 summarized the measured performance of the propose frequency synthesizer for DTV, WIMAX (mobile) system.
TABLE 5.1 Measure synthesizer performance summaries Technology(TSMC) 0.18-um CMOS 0.18-um CMOS
Carrier Frequency 2.5GHz ~2.7GHz 1.15GHz~2.08GHz
Reference Frequency 25MHz 36MHz
Reference Frequency 25MHz 36MHz