Thesis Overview

Fig. 1.3 Double-Conversion system spectrum

1.4 Thesis Overview

This thesis comprises five chapters of which this introduction is the first.

Chapter 2 begins with basic ideas of phase-locked loops as well as some important characteristics in a frequency synthesizer. The most important part describes the design concepts and every building block in a PLL.

In Chapter 3, we show several techniques to implement fractional-N PLL. The most significant part is the theorems of delta-sigma modulation. We also derive its analytic function to prove the abilities of randomization and noise shaping.

In Chapter 4, a completely integrated delta-sigma frequency synthesizer fabricated in 0.18µm CMOS 1P6M process is presented. We first introduce the architecture of the synthesizer and the behavior simulation in MATLAB. Then, every building block such as the phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator, the programmable divider, and the delta-sigma modulator, are discussed and designed.

In Chapter 5, we present the testing environment, including the instruments and components on the print circuit board (PCB). The experimental results for the Σ∆

frequency synthesizer described in Chapter 4 will be presented.

Chapter 6 gives conclusions to this work, in which a delta-sigma fractional-N frequency synthesizer is designed and verified to be feasible. Suggestions for future works are recommended at the end of this thesis.

Chapter 2

Basic theories of Phase-Locked Loop

2.1 Introduction to PLL

Phase-locked loops are used widely in the modern system such as communications, command, telemetry, radar, time and frequency control, computer, and instrumentation systems. Today, it is rare to find a piece of electronic equipment that does not employ a PLL in some form. Take communications for instance, they can recover the carrier from satellite transmission signals, recover clock from digital data signals, synthesize exact frequencies for receiver tuning, perform frequency and phase modulation and demodulation, and reduce EMI effects.

A PLL circuit can make a particular system to track with another one. More definitely, a PLL synchronizes the output signal of an oscillator with a reference signal in frequency as well as in phase. When PLL is locked, the phase error between the reference signal and the oscillator^，s output signal is zero or remains constant.

Some examples are described as follows [6]:

1. Carrier recovery: In all applications related to coherent telecommunications, it is necessary to reconstruct a carrier reference from a noise-corrupted version of the received signal first. Fig. 2.1 shows a received signal vi consisting of bursts of a

sinusoid. When a burst occurs, a PLL can detect the error and then create a output

2. Clock recovery : A clock signal is need to be synchronized to a digital data signal vi in some application. As shown in Fig. 2.2, vi represents the data sequence which is 1,0,1,1,0,1,1,1,0,0,1. Analyzing this data signal knows that there is a component at ωi, where 2π/ωi is the spacing between logic symbols. A PLL can lock the oscillator frequency ωo to the ωi, producing the clock signal vo.

Fig. 2.2 Clock recovery

3. Frequency demodulation and Phase demodulation: Most FM receivers today adopt a PLL for frequency demodulation. If the bandwidth of the PLL is wide enough, the PLL output frequency ωo can track the input frequency ωi as it varies

according to the modulation. If the control voltage νc of the voltage control oscillator (VCO) is proportional to ωo , it is also proportional to ωi. Consequently, νc is the demodulated signal, as shown in Fig. 2.3. Similar concepts can be used for phase demodulation.

Fig. 2.3 Frequency demodulation

2.2 Architecture of Frequency Synthesizer

Frequency synthesizers play an crucial role in the field of communications. The frequency synthesizer was a system creating a set of frequencies what we need.

Generally speaking, three common frequency synthesizer types can be distinguished:

the direct synthesizer, the indirect or phase-locked synthesizer, and the table-look-up or digital synthesizer. Because the direct synthesizer is too bulky to integrate on a chip and the digital frequency synthesizer can not be used for high output frequencies, most synthesizers used in modern high frequency communication systems are of the phase-locked loop type.

A indirect synthesizer generates multiples of an accurate reference frequency. It is composed of five parts: a phase/frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage-controlled oscillator (VCO) and a programmable frequency divider with a divider ratio N. The simplest form of this synthesizer is

shown in Fig. 2.4.

The operation of the PLL is as follows: the VCO output frequency (Fout) is divided by N. The PFD compares the divided frequency (fdiv) with the reference frequency (Fref), then it gives digital up or down signals, which is equal to the phase difference between them, to control the CP. The CP would change the digital signals to the corresponding analog voltage signals. After that, the voltage signal is low-pass filtered by the loop filter, and is used to control the frequency of VCO. When PLL is locked, the phase of the divided output signal accurately tracks the phase of the reference signal. The phase-lock process forces fdiv and Fref to be equal. Finally, we can obtain

F_out = N．Fref (2.1)

Fig. 2.4 The simplest diagram of frequency synthesizer

2.3 Phase / Frequency Detector

A PFD, which is usually built with a state machine with memory elements such as flip-flops, can monitor the difference between two input signals. Fig. 2.5 illustrates a common linear PFD structure using resettable DFFs and its operation diagram. If the reference signal leads the feedback signal, PFD will output an UP

signal with its pulse width proportional to the phase difference. However, if the reference signal lags the feedback signal, PFD will output a corresponding DN signal.

(a)

(b)

Fig. 2.5 (a) Linear PFD architecture (b) Operation of PFD

We could make a state diagram according to the operation of PFD, as shown in Fig. 2.6. Initially, outputs are both low. When one of the PFD inputs rises, the corresponding output becomes high. The state of the finite-state machine changes from an initial state to an Up or Down state. The state is held until the second input goes high, which in turn resets the circuit and returns the finite-state machine to the initial state. Fig. 2.7 illustrates that the characteristic of the PFD is ideally linear for the entire range of input phase differences form -2π to 2π.

Fig. 2.6 PFD state diagram

∆Φ

Fig. 2.7 Ideal linear characteristic

A conventional CMOS PFD is shown in Fig. 2.8. This PFD has large dead zone, which is shown in Fig. 2.9, in the phase characteristic at the equilibrium point, which generates a large jitter in locked state in PLL. Furthermore, the maximum speed is limited because of the total gate delay [7][8].

.

Fig. 2.8 Conventional PFD

Fig. 2.9 Dead zone problem

2.4 Charge pump

The charge pump (CP) is an analog circuit controlled by the PFD outputs. It generates phase error correction current pulses to the loop filter, in order to pull the control voltage of the VCO up or down to adjust the frequency of the VCO output signal. The conventional CP is shown in Fig. 2.10. Depending on which switch is activated, the CP will either charge or discharge the load-capacitor.

Fig. 2.10 Charge pump

Because these switches consist of MOS transistors, they suffer from several non-ideal effects, such as mismatches, charge injection, clock feedthrough, and

charge sharing, giving rise to clock-skew and reference spurs in the output of PLL.

Fig. 2.11 illustrates those effects on the output voltage.

Fig. 2.11 CP non-ideal effects

Subsequently, we discuss the PFD combined with CP. If the phase error between reference signal and feedback signal is ∆ , the charge or discharge current φ of the CP is Ip, the average error current in a cycle is Ie, then

2.5 Voltage-Controlled Oscillator

The voltage-controlled oscillator (VCO) operates at the highest frequency and usually determines the out-of-band noise of the frequency synthesizer. Different applications usually require different specification for the VCO. These requirements are often in conflict with one another, and therefore a compromise is needed. The most important specifications of the VCO are the tuning range, the power consumption, the phase noise, the tuning linearity, and the frequency

- Tuning range: the VCO must be able to cover the complete required frequency band of the application, taking account of process variations.

- Tuning linearity: to simplify the design of the PLL, the VCO gain Kvco should be constant.

- Frequency pushing: the dependency of the center frequency on the power supply voltage (in [MHz/ V]).

- Frequency pulling: the dependency of the center frequency on the output load impedance.

The output frequency (Fout) of the VCO is dependent on its control voltage (Vcontrol). The relationship between them can be written as

, where Kvco (Vcontrol) is the VCO gain factor in [Hz/V] and ωout is the free running frequency. The relationship of phase θo of the VCO signal with the control voltage Vcontrol can be derived as

Dropping the first term of the integral, which is not dependent on Vtune, results in

After phase and frequency lock is achieved, Vcontrol is nearly constant, so the dependency of Kvco on Vcontrol can be neglected. Taking the Laplace transform of (2.7) yields

We will discuss the most often used oscillator types now.

ω

_out

= ω

_center

+ ( K

_vco

V

_control

) i V

_{control (2.4)}

2.5.1 Crystal Oscillators

The most stable oscillator is the crystal oscillator. The symbol and equivalent circuit is shown in Fig. 2.12. From it, we can derive that a crystal has two resonance modes. At series resonance frequency ωs , the impedance of the crystal becomes almost zero. At parallel resonance frequency ωp , the impedance of the crystal is infinite. The corresponding resonance frequencies ωs and ωp are

Since Cp is much larger than Cs , ωs and ωp are very close together. This is the reason why crystal oscillators achieve very low phase noise. Their low noise and good stability let them the first choice for generating the reference signal in a frequency synthesizer .

Fig. 2.12: An oscillator crystal: (a) Symbol (b) Equivalent circuit

2.5.2 Ring Oscillators

The ring oscillator is one of the most popular oscillators for clock recovery circuits and integrated PLLs because it is simple and easy to integrate. The periodic signal is generated by a ring of inverters. They can be built of three or more inverters,

2 = 1 2 1 1 + 1

is 1 / 2n·Td , where n is the number of inverters in the ring and Td is the delay of one inverter. Fig. 2.13 shows the simplest ring oscillator. The tuning range is large.

However, the phase noise is inferior,impeding its use in high-quality communication systems.

Fig. 2.13 The simplest ring oscillator

2.5.3 LC Oscillators

To improve the phase noise of the ring oscillator, the power consumption will become unacceptably high. The best way to overcome this problem is to utilize the LC oscillator. Since this structure uses high Q passive elements to be their loads, it is expected that it will have a pure spectrum. Generally speaking, the phase noise of LC oscillators is 20dB better than those of ring oscillators. Also high speed operation is achieved because of the simple working principle. Nevertheless, the biggest challenges are how to realize inductors and to reduce needed area.

2.6 Loop Filter

The loop filter provides the current-to-voltage conversion from the charge pump signal to the tuning voltage input of the VCO. The purity of the tuning voltage determines how the spectrum of the VCO output signal is. In consequence, most of the PLL’s specifications will be determined by the loop filter. In the loop filter, extra poles and zeros can be introduced in the open loop transfer function, which are used to set the noise and transient performance of the PLL. The standard second-order

passive loop filter configuration is shown in Fig. 2.14. The shunt capacitor C1 is used to mitigate discrete voltage steps at the control port of the VCO because of the instantaneous changes in the CP current output.

Fig. 2.14 Second order passive loop filter

Then we will discuss its design considerations by adding PFD and CP. The impedance of Fig. 2.14 is

_{1 2}

With this transfer function, we can easily draw the Bode Plot to observe its behavior and use the open loop gain bandwidth and phase margin to determine the component.

Fig. 2.15 shows its Bode plot. Typically, we locate the unity gain frequency ωt

between ωz and ωp to ensure loop stability.

Fig. 2.15 Open loop response Bode Plot

However, additional pole is often necessary for suppressing the reference spur.

For this application, we place a series resistor and a shunt capacitor prior to the VCO for more attenuation of unwanted spurs. The recommended filter configuration is shown in Fig. 2.16. The added attenuation from the low pass filter is:

Besides, it is worthy to notice that the added pole must be lower than the reference frequency, in order to significantly attenuate the spurs, but must be at least 5 times higher than the loop bandwidth to keep system stable.

Fig. 2.16 Third order filter

(

^{3 3}

)

²

Attenuation = 20log^⎡_⎢

ω

_refR C 1^⎤_⎥

⎣ + ⎦ ^(2.12)

R₂

C₂

C₁ C3

R₃

I

cp

V

ctr

2.7 Frequency Divider

Frequency dividers are used to synthesize a high frequency LO from a precise low frequency crystal oscillator. The output frequency fdiv equals the input frequency fin divided by an integer number. From this information we could derive a model for the divider in the phase domain.

The phase θin of the input signal is given by

and the instantaneous frequency of the input signal is

and the phase of the output signal can now be found as

2.8 Noise Analysis of a PLL Synthesizer

Apart from channel selection and frequency accuracy, there are several other aspects of frequency synthesizers which have an influence on the performance of a transceiver, like phase noise and reference spur.

2.8.1 Phase Noise

A frequency synthesizer is expected to provide a pure spectral signal as shown in Fig. 2.17(a). There should be no unwanted frequency/phase modulation or

( ) = 2

_p

sin 2

_m

amplitude in the output spectrum because those undesired effect will reduce the channel selectivity and degrade the bit error rate of the receiver. However, the phase of the oscillation will fluctuate because of some noise at the frequency control input of the oscillator or the thermal noise of the resistors and transistors in the oscillator.

The phase fluctuation forms “skirts” around the carrier in the frequency domain as shown in Fig. 2.17(b). So, the phase noise is developed in order to determine how the performance of a VCO is. The phase noise is characterized as the power ratio of the noise within an unit bandwidth at an offset ∆ω with respect to ωc to the carrier.

{ } ^{f ( dBc Hz / ) = (} X dBm Y dBm ^{) ( ) 10log(} RBW ⁾

L ∆ − −

(2.17)

where ∆f is the offset frequency from carrier and RBW is the resolution bandwidth of spectrum analyzer.

Fig. 2.17 Output spectrum of (a) Ideal (b) Actual oscillator

The phase noise has a great effect upon both the receiver and transmitter. As illustrated in the Fig. 2.18(a), if there is a large interference signal near the small desired signal and the LO exhibits phase noise, both the desired signal and the interference will be mixed down to the IF. However, both signals will suffer from

significant noise which is generated from the LO signal since the down-conversions is actually a convolution in frequency domain. If the powers of the interference signals are large, the signal-to-noise ratio (SNR) of the desired signal will be reduced. This effect is called “reciprocal mixing.” On the other hand, for the receiver, large-power transmitted signals with substantial phase noise will corrupt nearby weak signals. Therefore, the output spectrum of the LO must be extremely sharp to avoid being detected by mistake. Fig. 2.18(b) describes this appearance [13].

Fig. 2.18 Effect of phase noise in the (a) Receiver and (b) Transmitter

2.8.2 Spurs

In addition to phase noise, the oscillator can also be modulated by some fixed frequency noise due to the switching of other circuits in the synthesizer. Take current

switching noise in the divider and the CP at the reference rate for example, they may cause unwanted FM sidebands at the LO. Fig 2.19 illustrates this circumstance that two tones appear at the upper and lower sideband of the carrier. These tones are called “spurs”. It is similar to the case of phase noise that these spurious sidebands will also cause noise in adjacent channels and degrade the SNR of the desired signal.

Fig. 2.19 Spurs

2.8.3 Noise Source at input

Fig. 2.20 shows the linear PLL model to analysis the input noise effect on the PLL output signal. The transfer function from Φin(s)to Φout(s) is derived as

Fig. 2.20 Noise transfer function of the PLL from input to output ( ) 1

For simplicity, we use first-order loop filter to rewrite the above equation as

Fig. 2.21 shows Bode plot of the transfer function. The input phase noise is shaped by the low-pass characteristic of the second-order PLL. For the sake of reducing the phase noise in the output signal because of the input noise, it is expected to let the PLL bandwidth as narrow as possible.

Fig. 2.21 Bode plot of the normalized transfer function

2.8.4 Noise of VCO

The phase noise of the VCO can be modeled as Fig. 2.22. Similar to Eq. 2.19, we also use the first-order filter to derive the transfer function. It can be expressed as

2

Fig. 2.22 Noise transfer function of the PLL from VCO to output

Compared with the input noise, the VCO phase noise is shaped by a high-pass characteristic by the second-order PLL. If we want to reduce the VCO phase noise, we need to make the PLL bandwidth as wide as possible. In view of this, we can know there is a tradeoff in the bandwidth position. The optimum loop bandwidth depends on the application. However, it is common to increase the loop bandwidth since the dominant source of noise is usually the VCO in fully integrated frequency synthesizer. Fig. 2.23 shows the PLL effect on the VCO output spectrum.

Fig. 2.23 Phase noise performance of the VCO

Chapter 3

Principles of Frequency Synthesizers

3.1 Frequency Synthesizer Types and Comparison

Frequency synthesizers can traditionally be considered to be of two main forms.

One is the integer-N frequency synthesizer, and the other is the fractional-N frequency synthesizer. For the integer-N synthesizer, its output frequency is always an integer multiple of the reference frequency. On the other hand, in the fractional-N frequency synthesizer the output frequency can be a fractional ratio of the reference frequency.

The inherent limitation of an integer-N frequency synthesizer is that its frequency resolution is equal to the PLL reference frequency Fref. Fine frequency resolution needs a small Fref and a correspondingly small loop bandwidth. Narrow loop bandwidths are undesired due to inadequate suppression of VCO phase noise, long switching times, and susceptibility to noise. So, the fractional-N frequency synthesizer has been developed to solve this problem [13]. With the same channel spacing, the fractional-N frequency synthesizer can be designed with a higher loop bandwidth than the integer-N frequency synthesizer. Higher loop bandwidth results in faster frequency switching and thereby dynamic bandwidth techniques can be used more efficiently [14][15]. This will also relax the PLL requirements in terms of

synthesis solves the frequency resolution issue, but it also generates other unwanted problems.

3.2 Fractional-N architectures

When designing a fractional-N frequency synthesizer, we suffer from a trade-off between loop bandwidth, tuning bandwidth, frequency switching speed, and power consumption. There are four Fractional-N frequency synthesizer techniques: pulse swallowing, phase interpolation, Wheatly random jittering and Delta-Sigma modulation [16][17].

3.2.1 Pulse swallowing

Let us consider a pulse swallowing fractional-N synthesizer shown in Fig. 3.1.

The condition of overflow in the accumulator is used to shift the divider modulus from n to n+1. For a M-bit accumulator, the average division factor N will be

The condition of overflow in the accumulator is used to shift the divider modulus from n to n+1. For a M-bit accumulator, the average division factor N will be

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