Noise of VCO

The phase noise of the VCO can be modeled as Fig. 2.22. Similar to Eq. 2.19, we also use the first-order filter to derive the transfer function. It can be expressed as

2

Fig. 2.22 Noise transfer function of the PLL from VCO to output

Compared with the input noise, the VCO phase noise is shaped by a high-pass characteristic by the second-order PLL. If we want to reduce the VCO phase noise, we need to make the PLL bandwidth as wide as possible. In view of this, we can know there is a tradeoff in the bandwidth position. The optimum loop bandwidth depends on the application. However, it is common to increase the loop bandwidth since the dominant source of noise is usually the VCO in fully integrated frequency synthesizer. Fig. 2.23 shows the PLL effect on the VCO output spectrum.

Fig. 2.23 Phase noise performance of the VCO

Chapter 3

Principles of Frequency Synthesizers

3.1 Frequency Synthesizer Types and Comparison

Frequency synthesizers can traditionally be considered to be of two main forms.

One is the integer-N frequency synthesizer, and the other is the fractional-N frequency synthesizer. For the integer-N synthesizer, its output frequency is always an integer multiple of the reference frequency. On the other hand, in the fractional-N frequency synthesizer the output frequency can be a fractional ratio of the reference frequency.

The inherent limitation of an integer-N frequency synthesizer is that its frequency resolution is equal to the PLL reference frequency Fref. Fine frequency resolution needs a small Fref and a correspondingly small loop bandwidth. Narrow loop bandwidths are undesired due to inadequate suppression of VCO phase noise, long switching times, and susceptibility to noise. So, the fractional-N frequency synthesizer has been developed to solve this problem [13]. With the same channel spacing, the fractional-N frequency synthesizer can be designed with a higher loop bandwidth than the integer-N frequency synthesizer. Higher loop bandwidth results in faster frequency switching and thereby dynamic bandwidth techniques can be used more efficiently [14][15]. This will also relax the PLL requirements in terms of

synthesis solves the frequency resolution issue, but it also generates other unwanted problems.

3.2 Fractional-N architectures

When designing a fractional-N frequency synthesizer, we suffer from a trade-off between loop bandwidth, tuning bandwidth, frequency switching speed, and power consumption. There are four Fractional-N frequency synthesizer techniques: pulse swallowing, phase interpolation, Wheatly random jittering and Delta-Sigma modulation [16][17].

3.2.1 Pulse swallowing

Let us consider a pulse swallowing fractional-N synthesizer shown in Fig. 3.1.

The condition of overflow in the accumulator is used to shift the divider modulus from n to n+1. For a M-bit accumulator, the average division factor N will be controlled by the accumulator input k as the following formula:

On every cycle of the divider output, k is added to the accumulator content X, so the new accumulator value would be X+k except the accumulator overflows.

Then, the value assigned to accumulator is X+k-2^M. In the condition of overflow, a carry output is generated to switch the divider modulus.

M

N = n + k

2

^(3.1)

PFD Filter VCO

Fig. 3.1 Pulse swallowing fractional-N synthesizer

The main problem of this operation is the phase error between the instantaneous frequency and the wanted frequency, at the phase detector. Although the final phase error over the complete cycle is zero, the periodic peak will arise when the frequency division changes from N to N+1 as shown in Fig. 3.2. If the phase error is unfiltered, it may cause severe spurious signals at the output of the VCO.

3.2.2 Phase interpolating

The phase interpolation is a spur reduction skill to suppress the spurious tones as seen in the pulse swallowing approach. The technique uses amplitude compensation to the PFD output utilizing a digital to analog converter (DAC), as shown in Fig. 3.3. The accumulation of the phase of the fractional part is subtracted from the output of the PFD with that of the DAC. If the two signals exactly match, the phase error signal and output spurious are eliminated because fractional synthesis is reduced. However, the precision of the compensation directly rely on the DAC accuracy. Even if the system is well compensated during the production phase og the design, the compensation does not remain accurate as the characteristics of the analog elements are varied by temperature and aging.

PFD Filter VCO

Fig. 3.3 Amplitude compensation approach

3.2.3 Random jittering

This skill employs a random sequence generator to randomize the division modulus and so converts the output spurs to jitter [18]. Fig. 3.4 illustrates this concept. The comparator output is one bit in order to control the divider module.

This technique brings a main drawback that the output spectrum displays a 1/f ² phase noise near the output frequency.

Fig. 3.4 Random jittering approach

3.2.4 Delta-Sigma modulation

Fig. 3.5 shows a Delta-sigma (Σ∆) modulation frequency synthesizer. The divider operates as the coarse quantizer, as only integer division ratios can be realized. By switching of the division between two or more integers, the average value of the division ratio is generated at the output of the frequency synthesizer. A Σ∆ modulator has the characteristic of noise shaping, so it can shape the phase noise resulting from randomization and quantization to a higher offset frequency. In this way, the SNR and dynamic range at the relevant frequency range is improved and the shaped quantization noise can be eliminated by filtering. However, it has a large power consumption and relatively high complexity.

PFD Filter VCO

Fig. 3.5 Delta-sigma modulation frequency synthesizer

3.2.5 Performance comparison

A brief overview of different fractional-N frequency synthesizers is presented in this section. Each of these structures has advantages and disadvantages as summarized in Table II. As a result of the best performance of the Σ∆ modulation, we choose this architecture to implement our circuit.

TABLE II Total Performance comparison

Technique

Components 1 accumulator DAC

1 accumulator

+ generator 2 accumulator Broad band

noise No No Yes No

3.3 Delta-sigma frequency synthesis

Delta-sigma modulation technique was primarily used in over-sampling converters until Riley used the modulator noise shaping property to improve the random jitter and phase noise.

3.3.1 Fundamental concepts

Fig. 3.6(a) shows that a Σ∆ modulator consists of three components such as the integrator, the quantizer, and the differentiator. Their frequency response and power spectrum is shown in Fig. 3.6(b). In an analog to digital converter, the analog input propagates to an integrator followed by a quantizer working at a high sampling frequency compared to the Nyquist frequency. Then, the output of the quantizer is delivered to the differentiator. Fig. 3.6(c) illustrate the operation of this process, we can find that the Σ∆ modulator noise transfer characteristic is high pass in nature and results in very low in-band noise levels. So, the in-band quantization noise is alleviated and higher out-of-band quantization noise can be suppressed by the low pass loop filter.

In a fractional-N synthesizer, the input of the Σ∆ modulator is usually a digital word representing the wanted fractional value and the output of the modulator is a stream of integer numbers used to control the divider modulus. This stream forces the VCO output frequency to be fractional ratio of the reference frequency. Over time, the average if the Σ∆ modulator output converges to the desired fractional ratio.

1

1

(1−z⁻) (1−z⁻¹)

Fig. 3.6 Σ∆ modulation structure and principle

3.3.2 First-order Σ∆ modulator

The equivalent model of a first-order Σ∆ modulator is shown in Fig. 3.7.

Z⁻1 Z⁻¹

Fig. 3.7 The equivalent model of a first-order Σ∆ modulator

we can get the transfer function as follows:

Now, we consider an accumulator and its equivalent block diagram, as shown in Fig. 3.8.

(1 1) _a

Y = + −X z⁻ q (3.2)

Fig. 3.8 (a) Implementation (b) block diagram of a accumulator

A transfer function of the accumulator can be derived as follows:

From Eq. (3.3), we find the output is a delayed version of the input with shaped quantization noise. Because the input is a constant, Eq. (3.2) and Eq. (3.3) are equal.

We prove that the implementation of Σ∆ modulator can be achieved by a accumulator.

In order to know the effect of noise shaping, we incorporate the Σ∆ modulator in the PLL to control the divider modulus, as shown in Fig. 3.9.

X

A discussion of the effects of quantization noise on the overall output, Fout , follows. Our first step is to evaluate the phase noise in Fdiv supposing an ideal VCO at a fixed frequency. The instantaneous frequency of Fdiv(t), is determined by the VCO frequency, Fout, and the instantaneous of division rate. The instantaneous frequency division rate in the case of Σ-∆ modulated dual-modulus divider is given by n + b(t), where b(t) is the bit stream alternating between 0 and 1; hence

Then, the bit stream can be broke up into the desired dc value, K/M, and an additive quantization noise [19][20]. In the time domain the quantization noise is labeled qe(t), giving

The normalized instantaneous frequency departure is defined as

Then,

If the rms spectral density of the quantization noise is labeled Sqe(f), then the power spectral density of the normalized phase deviation will be given by

( ) ( )

According to Eq. (3.3)

Because the quantizer in first order Σ∆ modulator is one bit,

The power spectral density of the quantization noise through the quantizer can be described as follows:

Combine Eq. (3.12) with Eq. (3.13), we can find its noise shaping ability

( )

^{1 s i n 2 r a d 2} / H z ,

Then from Eq. (3.9), we can get the final power spectral density of quantization noise is

However, from Eq. (3.15), we know that the noise un the output of VCO is flat, not the differential as we expected. In view of this, in order to obtain the noise shaping effectively, we must adopt the higher order Σ∆ modulator.

'

3.3.3 High order Σ∆ modulator

Based on the previous section, it is clear that implementing a fractional-N synthesizer with an accumulator known as a first-order Σ∆ modulator to control the divider is unwise. These shortcomings are greatly alleviated by implementing the division control with higher-order Σ∆ modulators. With this structure, the switching of the divider ratio is randomized, such that the spurious signals are no longer present in the output signal of the synthesizer. Fig. 3.10 (a) shows the second-order Σ∆ modulator and Fig. 3.10 (b) shows the third-order Σ∆ modulator. By principles of the superposition, we can easily know their outputs which the quantization noise is reduced more through noise shaping.

Second-order:

1

Fig. 3.10 Basic structures of (a) second-order modulator (b) third-order modulator

3.4 Mash implementations of Σ∆ modulator

Higher-order delta-sigma modulators improve the noise shaping characteristic, even so, they are not always stable because there are several feedback loops in the system. Fortunately, this problem was solved in the structure referred as Multistage Noise Shaping Technique (MASH) [21][22][23].

The MASH or cascade 1-1-1 Σ∆ modulator is depicted in Fig. 3.11(a). The MASH modulator consists of a cascade of first-order modulators and of a combiner stage. Fig. 3.11(b) shows the block diagram of the MASH 1-1-1. The operation of the modulator is as follows: each subsequent first-order modulator performs a quantization operation on the quantization error from the previous stages; the combiner stage, on its turn, realizes a noise shaping operation on the output signals from the first-order modulators. The math equation description is as follows:

So, the output of third-order modulator is:

1

X

Similar to first-order Σ∆ modulator, we can also change the noise transfer

According to Eq. (3.22), we find that the output power spectral density is now proportional to f ⁴, showing that the quantization noise is suppressed in the signal band. Through the process of the derivation, we can conclude that the for i^th order Σ∆

modulator the power spectral density of the phase noise is [24]

( ) ( )

Chapter 4

Frequency Synthesizers for DTV Tuner

4.1 Introduction

Today^，s high-performance RF frequency synthesizer are often required: (1) to have smooth transition among channel intervals; (2) to have low phase noise and frequency variation; (3) to work over a wide frequency range which can cover the desired range; (4) to have an integrated loop filter on the chip. In the previous chapters we discussed system level design issues of a frequency synthesizer. Based on the knowledge, we will implement a Σ∆ frequency synthesizer for a DTV broadband RF tuner. This synthesizer is fabricated in a 0.18µm standard CMOS technology. Provided a 36MHz input reference signal and several bits digital codes, the circuit can generate a frequency tuning range from 1.27 to 2.08 GHz with 6 MHz channel bandwidth.

4.2 System architecture

Fig. 4.1 shows this Σ∆ frequency synthesizer. It consists of phase frequency detector (PFD), charge pump (CP), voltage controlled oscillator (VCO), loop filter (LP), programmable divider, and Σ∆ modulator. The specification of every component must be designed with extreme care. The PFD must operate correctly to

distinguish phase error and frequency error, the filter must provide an optimum compromise in output noise, switching speed, and frequency settling. In addition to these, the VCO must be of high quality and the programmable divider should work at high speed.

Fig. 4.1 the architecture of Σ∆ frequency synthesizer

In the Fig. 4.1, we choose the second-order Σ∆ modulator to realize modulus control. When the output of the Σ∆ modulator is -1, 0, 1, and 2, we select the modulus of the divider as N+1, N, N-1, and N-2 respectively. Thus, a fractional division ratio from n fref to (n + 1) fref is achieved as known in previous chapters.

We use 7 bits accumulators to construct the modulator due to the minimum frequency resolution.

4.3 Behavior simulation

Due to the tremendous amount of gates counts in a frequency synthesizer, the

simulations can be made with SIMULINK to test and verify transient response and system parameters rapidly. The behavior model of the frequency synthesizer is implemented in SIMULINK as shown in Fig. 4.2. The behavior simulation results of the system are shown in Fig. 4.3 and Fig. 4.4.

Fig. 4.2 Behavior model of the fractional-N frequency synthesizer

(a)

(b)

Fig. 4.3 Simulation results of fractional-N frequency synthesizer (a) Bode plot of open-loop response (b) transient response

20dB/dec

40dB/dec

60dB/dec

Fig. 4.4 PSD of Σ∆ modulator (a) 1^st order (b) 2^nd order (c) 3^rd order

4.4 Circuit Implementation

4.4.1 Phase Frequency Detector

A common drawback for some phase frequency detector is a dead zone in the phase characteristic at the equilibrium point. The dead zone generates phase jitter because the control system does not change the control voltage when the phase error is within the dead zone. This influence can be improved by increasing the precision of the PFD. To reduce the dead zone and to overcome the speed limitation, we choose the dynamic phase frequency detector shown in Fig. 4.5 [25]. Compared with the conventional PFD, the transistor numbers are decreased to 12 and thus possesses smaller parasitic inherently. According to the phase difference between both input signals, UP is used to increase and DN is used to decrease the frequency of the output signal. Fig. 4.6 simulates its operation situation.

Fig. 4.5 Phase frequency detector

Fig. 4.6 The time diagram of the PFD

4.4.2 Charge Pump

As discussed in section 2.4, the non-ideal behavior of MOS switches such as charge injection and clockfeedthrough introduce phase noise and spurious tones in the VCO output. A lot of research has been developed to solve these problems.

Among them, current steering has been usually used due to their fast switching speed and low charge injection errors. Fig. 4.7 (a) shows the basic circuit proposed in [26]. When UP is greater thanUP, IB is steered on M2. The current difference between IB and IS is mirrored by M3 and M4, generating the charge or discharge current. On the contrary, when UP is greater than UP, IB is steered on M1. The pull-up circuit M5 and M6 is used to increase the charge speed of the node A which is the slow path of the structure. If this pull-up circuit is not used, M1 and M3 may produces a temporal current which may modulate the VCO and then cause phase noise. However, it also has several drawbacks. The modified circuit is shown in Fig.

4.7 (b). It employs the current reuse technique to save more power than Fig. 4.7 (a) and to turn off M4 faster. Finally, by adding M7 the slow path – node B- is improved.

The use of positive feedback and current reuse can obtain a faster switching speed without increasing the power consumption. The complete circuit we use is shown in

Fig. 4.8.

Fig. 4.7 (a) Basic charge pump (b) Modification for current reuse

UP UP

DN DN

Fig. 4.8 Charge pump used in this synthesizer

Combine PFD with charge pump, some important simulations which may affect the performance of the overall system are done. Fig. 4.9 shows the charge situation

of the circuit. Fig. 4.10 shows the dead zone simulation. Even very small phase error can be distinguished, so there is no dead zone. By carefully design, we can make the range of Vout as large as possible in order to generate wider tuning frequency, as shown in Fig. 4.11 [27].

ref

fb

up

dn

Vout

Fig. 4.9 The charge situation of the charge pump

Fig. 4.10 Dead zone simulation of PFD with CP

Fig. 4.11 the output voltage range of charge pump

4.4.3 Loop Filter

Loop filter design is chiefly concerned with the order of loop filter, bandwidth, and phase margin. It determines most specifications of the synthesizer and should be carefully designed. In terms of the order of loop filter, the most fundamental one is the second order filter. In the Σ∆ fractional-N PLL, however, the loop filter must equal to or higher than the order of Σ∆ modulator that ensures the extra noise from the modulator being filtered out properly. In view of this, we select the third order loop filter shown in Fig. 4.12 to implement our synthesizer. Besides, the phase margin relates to the stability of a system. Generally speaking, the phase margin is chosen from 45 degrees to 60 degrees.

Fig. 4.12 the third order filter

R₂

C₂

C₁ C3

R₃

I

cp

V

ctr

After deciding the order of the loop filter, we can easily determine the parameters of each element step by step [28]. The basic design considerations are shown in Fig. 4.13.

Fig. 4.13 Basic design considerations of the third order filter

1. Calculate the time constant T1 and T3. Then we can get the new unity-gain bandwidthω because of the added third pole. _C

1

4. As rule of thumb choosesC₃≤C₁ 10, otherwise T3 will interact with the primary poles of the filter.

C ₃ = C₁ 1 0 , R₃ = T₃ C ₃ (4.7) By following these steps, the calculated values of the elements which are all on-chip and some important parameters are listed in the following Table. The Bode diagram of the PLL is shown in Fig. 4.14.

Design parameters

Parameter Value

Fref 36 MHz

PLL BW 900 kHz

Kvco 866 MHz / V

Ip 0.06 mA

C1 7.245 pF

R2 8.05 kΩ

C2 91.88 pF

R3 18.3 kΩ

C3 724.53 fF

Fig. 4.14 Bode diagram simulation of the PLL

4.4.4 Voltage-Controlled Oscillator

A CMOS VCO can be built using ring structures or LC tanks. The LC design has the best noise and frequency performance because of the large quality factor Q achievable with resonant networks [29]. However, the limited tuning range and large area have become serious drawbacks in LC VCOs. On the other hand, ring VCOs have several attractive characteristics such as the ease of integration with standard CMOS process, the small chip area, and the wide frequency tuning range.

Furthermore, they can be used to generate both in-phase and quadrature-phase outputs with an even number of delay cells [30]. Therefore, taking System On Chip (SOC) and other advantages into consideration, we choose the ring oscillator to realize our VCO.

Several techniques have been devised to reduce the smallest achievable delay per stage because of the frequency limitations of a single-loop ring oscillator [31][32][33]. One of them is dual-delay paths method, as shown in Fig.4.15. The key point of the concept is that adding another feedforward loop to make the delay time smaller than that of the single-loop oscillator. The bold lines seen in Fig. 4.15 represent the primary loop and the dotted lines represent the auxiliary loop [34][35].

Fig. 4.15 Block diagram of ring oscillator with dual-delay paths

The design of delay cell is depicted in Fig. 4.16. M1 and M2 are the input pair

The design of delay cell is depicted in Fig. 4.16. M1 and M2 are the input pair

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