Chapter 3 Principles of Frequency Synthesizers
3.4 Mash implementations of Σ∆ modulator
Higher-order delta-sigma modulators improve the noise shaping characteristic, even so, they are not always stable because there are several feedback loops in the system. Fortunately, this problem was solved in the structure referred as Multistage Noise Shaping Technique (MASH) [21][22][23].
The MASH or cascade 1-1-1 Σ∆ modulator is depicted in Fig. 3.11(a). The MASH modulator consists of a cascade of first-order modulators and of a combiner stage. Fig. 3.11(b) shows the block diagram of the MASH 1-1-1. The operation of the modulator is as follows: each subsequent first-order modulator performs a quantization operation on the quantization error from the previous stages; the combiner stage, on its turn, realizes a noise shaping operation on the output signals from the first-order modulators. The math equation description is as follows:
So, the output of third-order modulator is:
1
X
Similar to first-order Σ∆ modulator, we can also change the noise transfer
According to Eq. (3.22), we find that the output power spectral density is now proportional to f 4, showing that the quantization noise is suppressed in the signal band. Through the process of the derivation, we can conclude that the for ith order Σ∆
modulator the power spectral density of the phase noise is [24]
( ) ( )
Chapter 4
Frequency Synthesizers for DTV Tuner
4.1 Introduction
Today，s high-performance RF frequency synthesizer are often required: (1) to have smooth transition among channel intervals; (2) to have low phase noise and frequency variation; (3) to work over a wide frequency range which can cover the desired range; (4) to have an integrated loop filter on the chip. In the previous chapters we discussed system level design issues of a frequency synthesizer. Based on the knowledge, we will implement a Σ∆ frequency synthesizer for a DTV broadband RF tuner. This synthesizer is fabricated in a 0.18µm standard CMOS technology. Provided a 36MHz input reference signal and several bits digital codes, the circuit can generate a frequency tuning range from 1.27 to 2.08 GHz with 6 MHz channel bandwidth.
4.2 System architecture
Fig. 4.1 shows this Σ∆ frequency synthesizer. It consists of phase frequency detector (PFD), charge pump (CP), voltage controlled oscillator (VCO), loop filter (LP), programmable divider, and Σ∆ modulator. The specification of every component must be designed with extreme care. The PFD must operate correctly to
distinguish phase error and frequency error, the filter must provide an optimum compromise in output noise, switching speed, and frequency settling. In addition to these, the VCO must be of high quality and the programmable divider should work at high speed.
Fig. 4.1 the architecture of Σ∆ frequency synthesizer
In the Fig. 4.1, we choose the second-order Σ∆ modulator to realize modulus control. When the output of the Σ∆ modulator is -1, 0, 1, and 2, we select the modulus of the divider as N+1, N, N-1, and N-2 respectively. Thus, a fractional division ratio from n fref to (n + 1) fref is achieved as known in previous chapters.
We use 7 bits accumulators to construct the modulator due to the minimum frequency resolution.
4.3 Behavior simulation
Due to the tremendous amount of gates counts in a frequency synthesizer, the
simulations can be made with SIMULINK to test and verify transient response and system parameters rapidly. The behavior model of the frequency synthesizer is implemented in SIMULINK as shown in Fig. 4.2. The behavior simulation results of the system are shown in Fig. 4.3 and Fig. 4.4.
Fig. 4.2 Behavior model of the fractional-N frequency synthesizer
(a)
(b)
Fig. 4.3 Simulation results of fractional-N frequency synthesizer (a) Bode plot of open-loop response (b) transient response
20dB/dec
40dB/dec
60dB/dec
Fig. 4.4 PSD of Σ∆ modulator (a) 1st order (b) 2nd order (c) 3rd order
4.4 Circuit Implementation
4.4.1 Phase Frequency Detector
A common drawback for some phase frequency detector is a dead zone in the phase characteristic at the equilibrium point. The dead zone generates phase jitter because the control system does not change the control voltage when the phase error is within the dead zone. This influence can be improved by increasing the precision of the PFD. To reduce the dead zone and to overcome the speed limitation, we choose the dynamic phase frequency detector shown in Fig. 4.5 [25]. Compared with the conventional PFD, the transistor numbers are decreased to 12 and thus possesses smaller parasitic inherently. According to the phase difference between both input signals, UP is used to increase and DN is used to decrease the frequency of the output signal. Fig. 4.6 simulates its operation situation.
Fig. 4.5 Phase frequency detector
Fig. 4.6 The time diagram of the PFD
4.4.2 Charge Pump
As discussed in section 2.4, the non-ideal behavior of MOS switches such as charge injection and clockfeedthrough introduce phase noise and spurious tones in the VCO output. A lot of research has been developed to solve these problems.
Among them, current steering has been usually used due to their fast switching speed and low charge injection errors. Fig. 4.7 (a) shows the basic circuit proposed in [26]. When UP is greater thanUP, IB is steered on M2. The current difference between IB and IS is mirrored by M3 and M4, generating the charge or discharge current. On the contrary, when UP is greater than UP, IB is steered on M1. The pull-up circuit M5 and M6 is used to increase the charge speed of the node A which is the slow path of the structure. If this pull-up circuit is not used, M1 and M3 may produces a temporal current which may modulate the VCO and then cause phase noise. However, it also has several drawbacks. The modified circuit is shown in Fig.
4.7 (b). It employs the current reuse technique to save more power than Fig. 4.7 (a) and to turn off M4 faster. Finally, by adding M7 the slow path – node B- is improved.
The use of positive feedback and current reuse can obtain a faster switching speed without increasing the power consumption. The complete circuit we use is shown in
Fig. 4.8.
Fig. 4.7 (a) Basic charge pump (b) Modification for current reuse
UP UP
DN DN
Fig. 4.8 Charge pump used in this synthesizer
Combine PFD with charge pump, some important simulations which may affect the performance of the overall system are done. Fig. 4.9 shows the charge situation
of the circuit. Fig. 4.10 shows the dead zone simulation. Even very small phase error can be distinguished, so there is no dead zone. By carefully design, we can make the range of Vout as large as possible in order to generate wider tuning frequency, as shown in Fig. 4.11 [27].
ref
fb
up
dn
Vout
Fig. 4.9 The charge situation of the charge pump
Fig. 4.10 Dead zone simulation of PFD with CP
Fig. 4.11 the output voltage range of charge pump
4.4.3 Loop Filter
Loop filter design is chiefly concerned with the order of loop filter, bandwidth, and phase margin. It determines most specifications of the synthesizer and should be carefully designed. In terms of the order of loop filter, the most fundamental one is the second order filter. In the Σ∆ fractional-N PLL, however, the loop filter must equal to or higher than the order of Σ∆ modulator that ensures the extra noise from the modulator being filtered out properly. In view of this, we select the third order loop filter shown in Fig. 4.12 to implement our synthesizer. Besides, the phase margin relates to the stability of a system. Generally speaking, the phase margin is chosen from 45 degrees to 60 degrees.
Fig. 4.12 the third order filter
R2
C2
C1 C3
R3
I
cpV
ctrAfter deciding the order of the loop filter, we can easily determine the parameters of each element step by step [28]. The basic design considerations are shown in Fig. 4.13.
Fig. 4.13 Basic design considerations of the third order filter
1. Calculate the time constant T1 and T3. Then we can get the new unity-gain bandwidthω because of the added third pole. C
1
4. As rule of thumb choosesC3≤C1 10, otherwise T3 will interact with the primary poles of the filter.
C 3 = C1 1 0 , R3 = T3 C 3 (4.7) By following these steps, the calculated values of the elements which are all on-chip and some important parameters are listed in the following Table. The Bode diagram of the PLL is shown in Fig. 4.14.
Design parameters
Parameter Value
Fref 36 MHz
PLL BW 900 kHz
Kvco 866 MHz / V
Ip 0.06 mA
C1 7.245 pF
R2 8.05 kΩ
C2 91.88 pF
R3 18.3 kΩ
C3 724.53 fF
Fig. 4.14 Bode diagram simulation of the PLL
4.4.4 Voltage-Controlled Oscillator
A CMOS VCO can be built using ring structures or LC tanks. The LC design has the best noise and frequency performance because of the large quality factor Q achievable with resonant networks [29]. However, the limited tuning range and large area have become serious drawbacks in LC VCOs. On the other hand, ring VCOs have several attractive characteristics such as the ease of integration with standard CMOS process, the small chip area, and the wide frequency tuning range.
Furthermore, they can be used to generate both in-phase and quadrature-phase outputs with an even number of delay cells [30]. Therefore, taking System On Chip (SOC) and other advantages into consideration, we choose the ring oscillator to realize our VCO.
Several techniques have been devised to reduce the smallest achievable delay per stage because of the frequency limitations of a single-loop ring oscillator [31][32][33]. One of them is dual-delay paths method, as shown in Fig.4.15. The key point of the concept is that adding another feedforward loop to make the delay time smaller than that of the single-loop oscillator. The bold lines seen in Fig. 4.15 represent the primary loop and the dotted lines represent the auxiliary loop [34][35].
Fig. 4.15 Block diagram of ring oscillator with dual-delay paths
The design of delay cell is depicted in Fig. 4.16. M1 and M2 are the input pair of the primary loop, while M5 and M6 form the input pair of the second loop. M3 and M4 serve as variable resistances which are controlled by tuning the gate voltage of them in order to change the operating frequency. The cross-coupled NMOS, M7 and M8, can boost the operating frequency and reduce the transition time of the output signal. In the end, M9 and M10 are added as the load to prevent the oscillator from failing to oscillator when the control voltage approaches 1.8V [36]. Fig. 4.17 shows the simulation for the frequency-voltage characteristic of the three stage ring oscillator.
Fig. 4.16 Original delay cell of the ring oscillator
Fig. 4.17 Tuning characteristic of the original ring oscillator
According to Fig. 4.17, we find that the output frequency of the VCO changes barely when the control voltage is above 1.2V. This is because that at this time M3 and M4 tend to turn off, only leaving load resistance M9 and M10 biased at a constant voltage. In view of this, we propose a improved circuit minutely working when the control voltage is above 1.2V, as shown in Fig. 4.18. In the Fig. 4.18, by adding M11 and M12 the control voltage will be level shift and is used to bias the gate voltage of M9 and M10. At this time, the operation of M9 and M10 are so like variable resistances that they will also affect the output frequency of the VCO.
Consequently, the ideal is obviously known that M3 and M4 dominate the output frequency with the control voltage from 0V to 1.2V , on the contrary, M9 and M10 dominate the output frequency with the control voltage from 1.2V to 1.8V. So, the VCO can work normally with the control voltage from 0V to 1.8V. With careful design, we can find the frequency tuning range of the VCO is extended and has good linearity over the control voltage being 0V~1.8V. The VCO provides a frequency tuning range from 770 MHz to 2330 MHz and fits in with the desired output frequency. Take measurements into account, we use the open drain structure as the output buffer due to its high driving ability, as shown in Fig. 4.19. Fig. 4.20 shows the frequency-voltage characteristic of our VCO. Fig. 4.21 shows its phase noise performance. Fig. 4.22 shows the out swing is approach 190mV considering the PAD effect.
Fig. 4.18 The proposed delay cell
Fig. 4.19 The open drain structure
Fig. 4.20 Tuning characteristic of the proposed ring oscillator
Fig. 4.21 Phase noise of the VCO
Fig. 4.22 The output swing with the PAD effect
Finally, we simulate the VCO tuning range in the different corner conditions shown in Fig. 4.23 and summarize the results in the Table III. According to Table III, results illustrate that the VCO with the different corner conditions can all cover the wanted frequency range.
Fig. 4.23 Tuning range of the VCO with corner model variation
TABLE III Process corners simulation
Process Corners TT FF FS SS SF
Frequency(MHz) 770~2330 1020~2590 817~2340 576~2110 742~2340
4.4.5 Programmable Frequency Divider
Programmable dividers have to operate at the highest VCO frequency.
Therefore, the choice of the divider architecture is essential for achieving low power dissipation and high design flexibility. Fig. 4.24 depicts the programmable frequency divider. These feedback lines enable simple optimization of power dissipation. Another advantage is that the topology of the different cells in the divider is the same, therefore facilitating layout work.
Fig. 4.24 The architecture of programmable frequency divider FF
SS TT
The programmable divider can provide an output signal with a period of
Tout =
(
25+ p4⋅ +24 p3⋅ +23 p2⋅ + ⋅ +22 p1 21 p0)
×Tin (4.8)Therefore, this equation shows that the division ratios from 32 (if all pn=0) to 63 (if all pn=1) is achieved. The circuit of the 2/3 divider is shown in Fig. 4.25. The logic functions of the 2/3 cells are implemented with the Source Coupled Logic (SCL) structure presented in Fig. 4.26. The logic tree combines a latch function with an AND gate [37]. Fig. 4.27 shows the simulation of divide-by-62 frequency divider.
LATCH
Fig. 4.25 Functional blocks and logic implementation of a 2/3 divider cell
Fig. 4.26 SCL implementation of an AND gate combined with a latch function
Fig. 4.27 The simulation of divide-by-62 frequency divider
4.4.6 Sigma-Delta Modulator
The sigma-delta modulator can randomize the feedback division ratio and result in a helpful noise shaping of the phase noise introduced by fractional-N division.
The digital realization of a 7-bits pipelined second order Σ∆ modulator is shown in Fig. 4.28. It is composed of two accumulators and a noise cancellation network.
Each accumulator only employs a 7-bits adder and several registers. However, the noise cancellation network is more complex. The detail of the noise cancellation network design will be discussed in the following.
Fig. 4.28 Second order Σ∆ modulator
Fig. 4.29 shows the noise cancellation network of the second order Σ∆
modulator. In order to simply design, we analyze each adder’s logics states and design the decoder for it. First of all, the adder A has three states such as -1, 0, and 1, as shown in Table IV.
A
-Fig. 4.29 Noise cancellation network
TABLE IV Noise cancellation Network coding (A)
Observe the 2’s complement table, we can find that the highest two bits are the same.
So, we can simplify the out of adder A as
Then, we check the adder B where C1 is added to the output of adder A. Only three half-adders are used here and adder B’s output is tabulated inTable V. According to Table V, we can conclude that the output of adder B has only four states (000, 001, 010, 111) and can control the division modulus as N, N+1, N+2, N-1. From the above analysis, the total error cancellation network is shown in Fig. 4.30 [38].
Finally, a simplified flow chart of the modulation is illustrated in Fig. 4.31.
1
TABLE V Noise cancellation Network coding (B)
Fig. 4.30 Realization of the noise cancellation network
Modulator
4.5 Fractional-N Frequency Synthesizer System
By providing external digital control codes, the synthesizer can generate any desired frequency. Two extreme conditions are considered. Fig. 4.32 shows the transient response of the control voltage of the VCO and its output spectrum when 1.27 GHz LO is needed. On the other hand, Fig. 4.33 shows the simulation results when 2.08 GHz LO is needed.
(a)
(b)
Fig. 4.32 (a) VCO control voltage and (b) Out Spectrum when LO is 1.27GHz
(a)
(b)
Fig. 4.33 (a) VCO control voltage and (b) Out Spectrum when LO is 2.08 GHz
With Fig. 4.32 and Fig. 4.33, we prove that the frequency synthesizer can meet all the frequency range which we expect through the change of the control voltage of the VCO. The parameters and performance summaries of the frequency synthesizer are listed in Table VI.
TABLE VI Performance of the Σ∆ frequency synthesizer
Technology TSMC 0.18-um 1P6M CMOS
Chip area 0.92mm × 0.92mm
Supply voltage 1.8V
Reference frequency 36 MHz
Output frequency 1.27 GHz ~ 2.08 GHz
VCO gain 866 MHz / V
VCO output swing 190 mV
Phase noise@1 MHz offset -100 dB / Hz
Phase margin 56degree
Loop bandwidth 900 kHz
Channel bandwidth 6 MHz
Setting time < 3us
Maximum power consumption 13.08 mW
The overall synthesizer layout is shown in Fig. 4.34 and the PCB layout is shown in Fig. 4.35.
Fig. 4.34 Physical layout of the Σ∆ frequency synthesizer
Fig. 4.35 The PCB layout
Chapter 5
Testing Setup and Experimental Results
5.1 Introduction
In this Chapter, we present the testing environment, including the instruments and components on the print circuit board (PCB). The experimental results for the Σ∆ frequency synthesizer described in Chapter 4 will be presented.
5.2 Experimental Results
5.2.1 Prototype
The proposed Σ∆ frequency synthesizer has been implemented in a single IC that has been fabricated in a 0.18-µm 1P6M CMOS process. Fig. 5.1 shows the microphotograph of the synthesizer. This chip uses a total of 24 pads including reference clock input, VCO differential outputs, digital control signals, and bias voltages. The total area of the chip is 0.92 × 0.92 mm2 .
Fig. 5.1 Die microphotograph
5.2.2 Test Setup
The fabricated synthesizer was tested to determine its performance.
Measurement was performed with raw dies mounted on the PCB to prevent the parasitic effect of the package. Because the synthesizer is a mixed-mode system, we separate the powers and grounds of digital and analog parts. Then, we connect the ground of analog part and that of digital part with an inductor. The inductor shorts the DC voltage of the digital and analog grounds, while preventing the high-frequency noise in the digital circuit from coupling to the analog circuit by their grounds.
The analog and digital powers are generated by LM317 adjustable regulators as shown in Figure 5.2. The regulator circuit is easy to use and the output voltage could be predicted by equation (5.1)
VO U T = 1 . 2 5 1
(
+ R1 R 2)
+ I A D J iR 2 (5.1) The IADJ is the DC current that flows out of the ADJ terminal of the regulator.Besides, the capacitors C1 and C2 are the bypass capacitors.
Fig. 5.2 LM317 regulator
The outputs of the regulators are bypassed on the PCB with the parallel combination capacitors then connected to the chip. The bypass filter network is combined by 10µF, 1µF, 0.1µF and 0.01µF capacitors as shown in Fig. 5.3. The arrangement can provide decoupling of both low-frequency noise with large amplitudes and high-frequency noise with small amplitudes [39].
Fig. 5.3 Bypass filter at the regulator output
The measurement setup of the synthesizer is shown in Fig. 5.4. The input clock is produced from the signal generator (Agilent 33250A). The output spectrum is observed by a Spectrum Analyzer (Agilent E4440A). Fig. 5.5 shows the photograph of the related instruments. The testing PCB is shown in Fig. 5.6.
Fig. 5.4 Measurement setup of the synthesizer
(a)
(b)
Fig. 5.5 Photograph of (a) Waveform generator (b) Spectrum analyzer
Fig. 5.6 The testing PCB in the synthesizer
5.2.3 Measurement Results
In this section, we will discuss the measurement results of the synthesizer.
Firstly, we test the VCO’s free running frequency and tuning range. The measured VCO transfer curve is shown in Fig. 5.7. The free running frequency for the VCO is within the process corner and has a tuning range between 844 MHz and 2340 MHz.
Table VII compares the simulation results with the measurement results
Secondly, we test the overall system of the frequency synthesizer. By changing the digital control bits, we can synthesize different output frequency. Fig. 5.8 displays the output signal spectrum of 2.28 GHz with the phase noise -66.79 dBc/Hz at 1-MHz offset. Fig. 5.9 shows the measured phase noise. Table VIII summarizes the measured performance of the synthesizer.
Fig. 5.7 The measured VCO transfer curve
TABLE VII Comparisons between simulation and measurement
Spec Simulation Measurement
fmax ( MHz) 2330 2340
fmin ( MHz) 770 844
tuning range 1560 1496
KVCO (MHz / V) 867 831
(b)
Fig. 5.8 The output spectrum of the synthesizer at 2.28 GHz with
Fig. 5.8 The output spectrum of the synthesizer at 2.28 GHz with