Chapter 4 Frequency Synthesizers for DTV Tuner
4.5 Fractional-N Frequency Synthesizer System
By providing external digital control codes, the synthesizer can generate any desired frequency. Two extreme conditions are considered. Fig. 4.32 shows the transient response of the control voltage of the VCO and its output spectrum when 1.27 GHz LO is needed. On the other hand, Fig. 4.33 shows the simulation results when 2.08 GHz LO is needed.
(a)
(b)
Fig. 4.32 (a) VCO control voltage and (b) Out Spectrum when LO is 1.27GHz
(a)
(b)
Fig. 4.33 (a) VCO control voltage and (b) Out Spectrum when LO is 2.08 GHz
With Fig. 4.32 and Fig. 4.33, we prove that the frequency synthesizer can meet all the frequency range which we expect through the change of the control voltage of the VCO. The parameters and performance summaries of the frequency synthesizer are listed in Table VI.
TABLE VI Performance of the Σ∆ frequency synthesizer
Technology TSMC 0.18-um 1P6M CMOS
Chip area 0.92mm × 0.92mm
Supply voltage 1.8V
Reference frequency 36 MHz
Output frequency 1.27 GHz ~ 2.08 GHz
VCO gain 866 MHz / V
VCO output swing 190 mV
Phase noise@1 MHz offset -100 dB / Hz
Phase margin 56degree
Loop bandwidth 900 kHz
Channel bandwidth 6 MHz
Setting time < 3us
Maximum power consumption 13.08 mW
The overall synthesizer layout is shown in Fig. 4.34 and the PCB layout is shown in Fig. 4.35.
Fig. 4.34 Physical layout of the Σ∆ frequency synthesizer
Fig. 4.35 The PCB layout
Chapter 5
Testing Setup and Experimental Results
5.1 Introduction
In this Chapter, we present the testing environment, including the instruments and components on the print circuit board (PCB). The experimental results for the Σ∆ frequency synthesizer described in Chapter 4 will be presented.
5.2 Experimental Results
5.2.1 Prototype
The proposed Σ∆ frequency synthesizer has been implemented in a single IC that has been fabricated in a 0.18-µm 1P6M CMOS process. Fig. 5.1 shows the microphotograph of the synthesizer. This chip uses a total of 24 pads including reference clock input, VCO differential outputs, digital control signals, and bias voltages. The total area of the chip is 0.92 × 0.92 mm2 .
Fig. 5.1 Die microphotograph
5.2.2 Test Setup
The fabricated synthesizer was tested to determine its performance.
Measurement was performed with raw dies mounted on the PCB to prevent the parasitic effect of the package. Because the synthesizer is a mixed-mode system, we separate the powers and grounds of digital and analog parts. Then, we connect the ground of analog part and that of digital part with an inductor. The inductor shorts the DC voltage of the digital and analog grounds, while preventing the high-frequency noise in the digital circuit from coupling to the analog circuit by their grounds.
The analog and digital powers are generated by LM317 adjustable regulators as shown in Figure 5.2. The regulator circuit is easy to use and the output voltage could be predicted by equation (5.1)
VO U T = 1 . 2 5 1
(
+ R1 R 2)
+ I A D J iR 2 (5.1) The IADJ is the DC current that flows out of the ADJ terminal of the regulator.Besides, the capacitors C1 and C2 are the bypass capacitors.
Fig. 5.2 LM317 regulator
The outputs of the regulators are bypassed on the PCB with the parallel combination capacitors then connected to the chip. The bypass filter network is combined by 10µF, 1µF, 0.1µF and 0.01µF capacitors as shown in Fig. 5.3. The arrangement can provide decoupling of both low-frequency noise with large amplitudes and high-frequency noise with small amplitudes [39].
Fig. 5.3 Bypass filter at the regulator output
The measurement setup of the synthesizer is shown in Fig. 5.4. The input clock is produced from the signal generator (Agilent 33250A). The output spectrum is observed by a Spectrum Analyzer (Agilent E4440A). Fig. 5.5 shows the photograph of the related instruments. The testing PCB is shown in Fig. 5.6.
Fig. 5.4 Measurement setup of the synthesizer
(a)
(b)
Fig. 5.5 Photograph of (a) Waveform generator (b) Spectrum analyzer
Fig. 5.6 The testing PCB in the synthesizer
5.2.3 Measurement Results
In this section, we will discuss the measurement results of the synthesizer.
Firstly, we test the VCO’s free running frequency and tuning range. The measured VCO transfer curve is shown in Fig. 5.7. The free running frequency for the VCO is within the process corner and has a tuning range between 844 MHz and 2340 MHz.
Table VII compares the simulation results with the measurement results
Secondly, we test the overall system of the frequency synthesizer. By changing the digital control bits, we can synthesize different output frequency. Fig. 5.8 displays the output signal spectrum of 2.28 GHz with the phase noise -66.79 dBc/Hz at 1-MHz offset. Fig. 5.9 shows the measured phase noise. Table VIII summarizes the measured performance of the synthesizer.
Fig. 5.7 The measured VCO transfer curve
TABLE VII Comparisons between simulation and measurement
Spec Simulation Measurement
fmax ( MHz) 2330 2340
fmin ( MHz) 770 844
tuning range 1560 1496
KVCO (MHz / V) 867 831
(b)
Fig. 5.8 The output spectrum of the synthesizer at 2.28 GHz with (a) Span = 131.1 MHz and (b) Span = 76.53 MHz
Fig. 5.9 The measured phase noise
TABLE VIII Performance summary
Technology TSMC 0.18-um 1P6M CMOS
Chip area 0.92mm × 0.92mm
Supply voltage 1.8V
Reference frequency 36 MHz
Output frequency 1.69 GHz ~ 2.28 GHz Synthesizer output swing 30 mV
Phase noise@1 MHz offset -66.79 dB / Hz
Channel bandwidth 6 MHz
Maximum power consumption 20.3 mW
5.3 Conclusion and Discussion
From the measurement, the function of the synthesizer is verified but the output power is small. We guess that the phenomenon results from the improper operation voltage at the open drain buffer. The loading effect of the divider causes the large size NMOS to operate in the linear region. So, the out signal is not amplified. The way to improve the problem is that we make the output of the VCO to feed a coupling capacitor, and then connects to the open-drain buffer with a resistor biasing its gate terminal, as shown in Fig. 5.10.
Another problem is that the synthesizer can not cover the full frequency band of interest. Besides, the phase noise is not good as we expected. Trace the reason carefully, we find that the defect might come from the process variation and un-prefect layout skill. It affects the linearity of the VCO and the designed loop filter parameters. These factors may cause the PLL to be unlocked in some region. In view of this, we should get more insight into the layout skill and process variation.
Chapter 6
Conclusions and Future Work
A fractional-N synthesizer is presented in this thesis including the history, the simulation and the fabrication to the measurement. Basically, the PLL synthesizer is composed of five building blocks: the phase detector, the charge pump, the loop filter, the VCO and the programmable divider. A lot of design challenges can be found in each block, but this work has tackled the problems of the VCO tuning range. We proposed a improved VCO circuit to widen its frequency tuning range and then to integrate in the frequency synthesizer.
Another interesting study is the delta-sigma modulator. The all-digital DSM is widely used in the fractional-N synthesizer because of many good properties. One major advantage is the reduction of the reference spur by randomizing the feedback division ratio such that the quantization noise of the fractional-N divider is transferred to higher frequency. Researches on all-digital DSM could be another topic for the fractional-N synthesizer.
In order to optimize the synthesizer performance, some features should be taken care of. Firstly, the divider should be designed more cagily because it is another component in the synthesizer to operate at radio-frequency. Secondly, the layout of the whole synthesizer, especially the VCO, should be considered carefully.
Finally, the analog and digital supplies should be separated for reducing the noise
coupling.
Some suggestions for the future work are given as follows. Firstly, the ESD protection should be considered in the circuit design and physical layout to avoid the instantaneous high voltage breaking down the circuit. Secondly, the voltage supplies of different functional blocks of the synthesizer should be separated for debugging.
Finally, parallel control bits of the modulator can be designed as serial input scheme to reduce the large number of PAD, which will save the area.
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