Phase Frequency Detector

A common drawback for some phase frequency detector is a dead zone in the phase characteristic at the equilibrium point. The dead zone generates phase jitter because the control system does not change the control voltage when the phase error is within the dead zone. This influence can be improved by increasing the precision of the PFD. To reduce the dead zone and to overcome the speed limitation, we choose the dynamic phase frequency detector shown in Fig. 4.5 [25]. Compared with the conventional PFD, the transistor numbers are decreased to 12 and thus possesses smaller parasitic inherently. According to the phase difference between both input signals, UP is used to increase and DN is used to decrease the frequency of the output signal. Fig. 4.6 simulates its operation situation.

Fig. 4.5 Phase frequency detector

Fig. 4.6 The time diagram of the PFD

4.4.2 Charge Pump

As discussed in section 2.4, the non-ideal behavior of MOS switches such as charge injection and clockfeedthrough introduce phase noise and spurious tones in the VCO output. A lot of research has been developed to solve these problems.

Among them, current steering has been usually used due to their fast switching speed and low charge injection errors. Fig. 4.7 (a) shows the basic circuit proposed in [26]. When UP is greater thanUP, IB is steered on M2. The current difference between IB and IS is mirrored by M3 and M4, generating the charge or discharge current. On the contrary, when UP is greater than UP, IB is steered on M1. The pull-up circuit M5 and M6 is used to increase the charge speed of the node A which is the slow path of the structure. If this pull-up circuit is not used, M1 and M3 may produces a temporal current which may modulate the VCO and then cause phase noise. However, it also has several drawbacks. The modified circuit is shown in Fig.

4.7 (b). It employs the current reuse technique to save more power than Fig. 4.7 (a) and to turn off M4 faster. Finally, by adding M7 the slow path – node B- is improved.

The use of positive feedback and current reuse can obtain a faster switching speed without increasing the power consumption. The complete circuit we use is shown in

Fig. 4.8.

Fig. 4.7 (a) Basic charge pump (b) Modification for current reuse

UP UP

DN DN

Fig. 4.8 Charge pump used in this synthesizer

Combine PFD with charge pump, some important simulations which may affect the performance of the overall system are done. Fig. 4.9 shows the charge situation

of the circuit. Fig. 4.10 shows the dead zone simulation. Even very small phase error can be distinguished, so there is no dead zone. By carefully design, we can make the range of Vout as large as possible in order to generate wider tuning frequency, as shown in Fig. 4.11 [27].

ref

fb

up

dn

Vout

Fig. 4.9 The charge situation of the charge pump

Fig. 4.10 Dead zone simulation of PFD with CP

Fig. 4.11 the output voltage range of charge pump

4.4.3 Loop Filter

Loop filter design is chiefly concerned with the order of loop filter, bandwidth, and phase margin. It determines most specifications of the synthesizer and should be carefully designed. In terms of the order of loop filter, the most fundamental one is the second order filter. In the Σ∆ fractional-N PLL, however, the loop filter must equal to or higher than the order of Σ∆ modulator that ensures the extra noise from the modulator being filtered out properly. In view of this, we select the third order loop filter shown in Fig. 4.12 to implement our synthesizer. Besides, the phase margin relates to the stability of a system. Generally speaking, the phase margin is chosen from 45 degrees to 60 degrees.

Fig. 4.12 the third order filter

R₂

C₂

C₁ C3

R₃

I

V

After deciding the order of the loop filter, we can easily determine the parameters of each element step by step [28]. The basic design considerations are shown in Fig. 4.13.

Fig. 4.13 Basic design considerations of the third order filter

1. Calculate the time constant T1 and T3. Then we can get the new unity-gain bandwidthω because of the added third pole. _C

1

4. As rule of thumb choosesC₃≤C₁ 10, otherwise T3 will interact with the primary poles of the filter.

C ₃ = C₁ 1 0 , R₃ = T₃ C ₃ (4.7) By following these steps, the calculated values of the elements which are all on-chip and some important parameters are listed in the following Table. The Bode diagram of the PLL is shown in Fig. 4.14.

Design parameters

Parameter Value

Fref 36 MHz

PLL BW 900 kHz

Kvco 866 MHz / V

Ip 0.06 mA

C1 7.245 pF

R2 8.05 kΩ

C2 91.88 pF

R3 18.3 kΩ

C3 724.53 fF

Fig. 4.14 Bode diagram simulation of the PLL

4.4.4 Voltage-Controlled Oscillator

A CMOS VCO can be built using ring structures or LC tanks. The LC design has the best noise and frequency performance because of the large quality factor Q achievable with resonant networks [29]. However, the limited tuning range and large area have become serious drawbacks in LC VCOs. On the other hand, ring VCOs have several attractive characteristics such as the ease of integration with standard CMOS process, the small chip area, and the wide frequency tuning range.

Furthermore, they can be used to generate both in-phase and quadrature-phase outputs with an even number of delay cells [30]. Therefore, taking System On Chip (SOC) and other advantages into consideration, we choose the ring oscillator to realize our VCO.

Several techniques have been devised to reduce the smallest achievable delay per stage because of the frequency limitations of a single-loop ring oscillator [31][32][33]. One of them is dual-delay paths method, as shown in Fig.4.15. The key point of the concept is that adding another feedforward loop to make the delay time smaller than that of the single-loop oscillator. The bold lines seen in Fig. 4.15 represent the primary loop and the dotted lines represent the auxiliary loop [34][35].

Fig. 4.15 Block diagram of ring oscillator with dual-delay paths

The design of delay cell is depicted in Fig. 4.16. M1 and M2 are the input pair of the primary loop, while M5 and M6 form the input pair of the second loop. M3 and M4 serve as variable resistances which are controlled by tuning the gate voltage of them in order to change the operating frequency. The cross-coupled NMOS, M7 and M8, can boost the operating frequency and reduce the transition time of the output signal. In the end, M9 and M10 are added as the load to prevent the oscillator from failing to oscillator when the control voltage approaches 1.8V [36]. Fig. 4.17 shows the simulation for the frequency-voltage characteristic of the three stage ring oscillator.

Fig. 4.16 Original delay cell of the ring oscillator

Fig. 4.17 Tuning characteristic of the original ring oscillator

According to Fig. 4.17, we find that the output frequency of the VCO changes barely when the control voltage is above 1.2V. This is because that at this time M3 and M4 tend to turn off, only leaving load resistance M9 and M10 biased at a constant voltage. In view of this, we propose a improved circuit minutely working when the control voltage is above 1.2V, as shown in Fig. 4.18. In the Fig. 4.18, by adding M11 and M12 the control voltage will be level shift and is used to bias the gate voltage of M9 and M10. At this time, the operation of M9 and M10 are so like variable resistances that they will also affect the output frequency of the VCO.

Consequently, the ideal is obviously known that M3 and M4 dominate the output frequency with the control voltage from 0V to 1.2V , on the contrary, M9 and M10 dominate the output frequency with the control voltage from 1.2V to 1.8V. So, the VCO can work normally with the control voltage from 0V to 1.8V. With careful design, we can find the frequency tuning range of the VCO is extended and has good linearity over the control voltage being 0V~1.8V. The VCO provides a frequency tuning range from 770 MHz to 2330 MHz and fits in with the desired output frequency. Take measurements into account, we use the open drain structure as the output buffer due to its high driving ability, as shown in Fig. 4.19. Fig. 4.20 shows the frequency-voltage characteristic of our VCO. Fig. 4.21 shows its phase noise performance. Fig. 4.22 shows the out swing is approach 190mV considering the PAD effect.

Fig. 4.18 The proposed delay cell

Fig. 4.19 The open drain structure

Fig. 4.20 Tuning characteristic of the proposed ring oscillator

Fig. 4.21 Phase noise of the VCO

Fig. 4.22 The output swing with the PAD effect

Finally, we simulate the VCO tuning range in the different corner conditions shown in Fig. 4.23 and summarize the results in the Table III. According to Table III, results illustrate that the VCO with the different corner conditions can all cover the wanted frequency range.

Fig. 4.23 Tuning range of the VCO with corner model variation

TABLE III Process corners simulation

Process Corners TT FF FS SS SF

Frequency(MHz) 770~2330 1020~2590 817~2340 576~2110 742~2340