Procedure Calls, Interrupts, and
CHAPTER 6 PROCEDURE CALLS, INTERRUPTS, AND
6.4 INTERRUPTS AND EXCEPTIONS
6.4.1 Call and Return Operation for Interrupt or Exception Handling Procedures
A call to an interrupt or exception handler procedure is similar to a procedure call to another protection level (see Section 6.3.6, “CALL and RET Operation Between Privilege Levels”).
Here, the interrupt vector references one of two kinds of gates: an interrupt gate or a trap gate.
Interrupt and trap gates are similar to call gates in that they provide the following information:
•
Access rights information•
The segment selector for the code segment that contains the handler procedure•
An offset into the code segment to the first instruction of the handler procedureThe difference between an interrupt gate and a trap gate is as follows. If an interrupt or exception handler is called through an interrupt gate, the processor clears the interrupt enable (IF) flag in the EFLAGS register to prevent subsequent interrupts from interfering with the execution of the handler. When a handler is called through a trap gate, the state of the IF flag is not changed.
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NOTES:
1. The UD2 instruction was introduced in the Pentium Pro processor.
2. IA-32 processors after the Intel386 processor do not generate this exception.
3. This exception was introduced in the Intel486 processor.
4. This exception was introduced in the Pentium processor and enhanced in the P6 family processors.
5. This exception was introduced in the Pentium III processor.
Table 6-1. Exceptions and Interrupts
Vector No. Mnemonic Description Source
0 #DE Divide Error DIV and IDIV instructions.
1 #DB Debug Any code or data reference.
2 NMI Interrupt Non-maskable external interrupt.
3 #BP Breakpoint INT 3 instruction.
4 #OF Overflow INTO instruction.
5 #BR BOUND Range Exceeded BOUND instruction.
6 #UD Invalid Opcode (UnDefined
Opcode) UD2 instruction or reserved opcode.1 7 #NM Device Not Available (No Math
Coprocessor) Floating-point or WAIT/FWAIT instruction.
8 #DF Double Fault Any instruction that can generate an
exception, an NMI, or an INTR.
9 #MF CoProcessor Segment Overrun
(reserved) Floating-point instruction.2
10 #TS Invalid TSS Task switch or TSS access.
11 #NP Segment Not Present Loading segment registers or accessing system segments.
12 #SS Stack Segment Fault Stack operations and SS register loads.
13 #GP General Protection Any memory reference and other protection checks.
14 #PF Page Fault Any memory reference.
15 Reserved
16 #MF Floating-Point Error (Math Fault) Floating-point or WAIT/FWAIT instruction.
17 #AC Alignment Check Any data reference in memory.3
18 #MC Machine Check Error codes (if any) and source are model dependent.4
19 #XF SIMD Floating-Point Exception SIMD Floating-Point Instruction5
20-31 Reserved
32-255 Maskable Interrupts External interrupt from INTR pin or INT n instruction.
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If the code segment for the handler procedure has the same privilege level as the currently executing program or task, the handler procedure uses the current stack; if the handler executes at a more privileged level, the processor switches to the stack for the handler’s privilege level.
If no stack switch occurs, the processor does the following when calling an interrupt or excep-tion handler (see Figure 6-5):
1. Pushes the current contents of the EFLAGS, CS, and EIP registers (in that order) on the stack.
2. Pushes an error code (if appropriate) on the stack.
3. Loads the segment selector for the new code segment and the new instruction pointer (from the interrupt gate or trap gate) into the CS and EIP registers, respectively.
4. If the call is through an interrupt gate, clears the IF flag in the EFLAGS register.
5. Begins execution of the handler procedure.
Figure 6-5. Stack Usage on Transfers to Interrupt and Exception Handling Routines CS
Error Code EFLAGS
CS EIP
ESP After Transfer to Handler
Error Code ESP Before
Transfer to Handler
EFLAGS
EIP SS ESP Stack Usage with No
Privilege-Level Change
Stack Usage with Privilege-Level Change Interrupted Procedure’s
Interrupted Procedure’s and Handler’s Stack
Handler’s Stack
ESP After Transfer to Handler Transfer to HandlerESP Before
Stack
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If a stack switch does occur, the processor does the following:
1. Temporarily saves (internally) the current contents of the SS, ESP, EFLAGS, CS, and EIP registers.
2. Loads the segment selector and stack pointer for the new stack (that is, the stack for the privilege level being called) from the TSS into the SS and ESP registers and switches to the new stack.
3. Pushes the temporarily saved SS, ESP, EFLAGS, CS, and EIP values for the interrupted procedure’s stack onto the new stack.
4. Pushes an error code on the new stack (if appropriate).
5. Loads the segment selector for the new code segment and the new instruction pointer (from the interrupt gate or trap gate) into the CS and EIP registers, respectively.
6. If the call is through an interrupt gate, clears the IF flag in the EFLAGS register.
7. Begins execution of the handler procedure at the new privilege level.
A return from an interrupt or exception handler is initiated with the IRET instruction. The IRET instruction is similar to the far RET instruction, except that it also restores the contents of the EFLAGS register for the interrupted procedure. When executing a return from an interrupt or exception handler from the same privilege level as the interrupted procedure, the processor performs these actions:
1. Restores the CS and EIP registers to their values prior to the interrupt or exception.
2. Restores the EFLAGS register.
3. Increments the stack pointer appropriately.
4. Resumes execution of the interrupted procedure.
When executing a return from an interrupt or exception handler from a different privilege level than the interrupted procedure, the processor performs these actions:
1. Performs a privilege check.
2. Restores the CS and EIP registers to their values prior to the interrupt or exception.
3. Restores the EFLAGS register.
4. Restores the SS and ESP registers to their values prior to the interrupt or exception, resulting in a stack switch back to the stack of the interrupted procedure.
5. Resumes execution of the interrupted procedure.
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