CIRCUIT REALIZATION

2.2.1 The Circuit Design of Injection-locked Frequency Triplers

Based on the model developed in Section 2.1, the K-band and V-band CMOS ILFTs are designed. The proposed CMOS ILFT circuit is shown in Fig. 2.3. The off-chip transformer T1 is designed to generate the differential input signal. The function of the frequency pre-generator is implemented by M1 and M2. The design guideline of M1 and M2 is the same as for the conventional frequency multipliers in [71]. The gate bias VBIAS of M1 and M2 is fed from the input off-chip transformer T1 and the conversion gain of the frequency pre-generator can be maximized with an appropriate VBIAS value. The tripled-frequency signal generated by the frequency pre-generator is injected into the ILO formed by M3, M4, C1, C2, L1, and L2. The selected values of inductors L1/L2 and varactors C1/C2 are chosen so that their resonant frequency is close to the third-order harmonic frequency of the input signal.

According to the design guideline in Section 2.1, the quality factor of the LC-tank is maximized for a large output swing and low power consumption. VTUNE is the external controlled signal used to increase the locking range. M3 and M4 are used to generate the negative resistance to compensate for the loss of the LC-tank. R1 is designed for the improvement of the harmonic rejection-ratios (HRRs). Finally, the

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output signals are taken from the open-drain buffers for test purposes. The proposed ILFT has a current-reuse structure between the frequency pre-generator and the ILO for low power operation.

Fig. 2.4 shows the HSPICE simulated normalized third-order harmonic currents Id3/Idmax of the frequency pre-generator M1/M2 as a function of conduction angle (θCON) where Id3 is the output amplitude of the drain current at the third-order harmonic frequency, Idmax is defined as the maximum peak-to-peak output drain current, and conduction angle is the device turn-on angle within one period of input signal. The simulation condition involves an 8-GHz input signal with 4-dBm input power and a MOS device with dimensions of W/L = 18 μm/0.18 μm with gate-source bias voltage changing from 0.03 V to 1.03 V. Because of the parasitic capacitance of the device, the ac current between the gate and drain is included in the output drain current Idmax. Thus, the normalized harmonic current curve in Fig. 2.4 is not the same as the ideal switch condition in [71]. The maximum output third-order harmonic current occurs when the conduction angle is 100°. With this conduction angle, the devices M1/M2 must be biased at the weak-inversion region. Under this condition, the ILO circuits may not satisfy the oscillation condition with such a small dc current. In the proposed ILFT, the frequency tripled function devices (M1 and M2) are biased at a conduction angle of 250° for higher frequency conversion efficiency while maintaining oscillation. The VBIAS can be calculated by a given input power, a device threshold voltage, and a suitable conduction angle [71].

Because the even harmonic signals are common-mode signals, an appropriate value for resistor R1 is set to eliminate the undesired even harmonic signals. To verify the effect of R1, Fig. 2.5 shows the HSPICE simulation results of the second-order and forth-order HRRs for various values of R1 in the K-band ILFT design. It can be

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seen that the HRR can be improved with a small R1 value. When the R1 value is 90 ohm, the HRRs improve with only a small voltage drop for the K-band ILFT.

However, for the V-band ILFT, the R1 value needs only to be 55 ohm because of the low nominal power supply voltage in 0.13-μm CMOS technology.

2.2.2 The Simulation Results of Injection-locked Frequency Triplers 2.2.2.1 K-band ILFT

Based on the model development in Section 2.1 and the circuit description in Section 2.2.1, the device dimension for K-band ILFT in 0.18-μm CMOS technology is shown in Table 2.1 (a). The locking range as a function of input bias VBIAS is shown in Fig.2.6. Small dc current is allowed through M3/M4 as the input bias VBIAS is decreased, the negative-resistance generated by M3/M4 becomes weaker. Therefore, the locking range is increased due to the small effective quality factor of LC tank. Due to a large third-order harmonic current is generated by M1/M2 at the VBIAS of 0.65 V, it exists a peak locking range. As a results, the input bias value VBIAS of 0.65 V is suggested in the K-band ILFT.

The simulated power consumption of the K-band ILFT is 2.95 mW at a power supply of 1.5 V. The SPECTRE RF simulated free-running K-band ILFT output after output buffer at time-domain and frequency-domain analysis are shown in Figs. 2.7 and 2.8, respectively. The free-running K-band ILFT provides the output amplitude of 250 mV as can be seen from transient simulation and output power of –2.04 dBm at 25.39 GHz as shown in the Fast-Fourier Transform (FFT) results. The simulated locked K-band ILFT output after output buffer with input power of 4 dBm, input frequency of 8.48 GHz, and VBIAS of 0.65 at time-domain and frequency-domain are shown in Figs. 2.9 and 2.10, respectively. It can be seen from Fig. 2.9 that the fundamental signal is existed in the output waveform. The simulated output spectrum

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of locked K-band ILFT is shown in Fig. 2.10 where the HRRs compared to the desired third-order harmonic are 24.21, 16.56, 25.49, 40.40 dBc for the first, second, forth, and fifth harmonics, respectively. Due to the parasitic capacitance of resistor R1, the HRRs can not reach to the ideal case in Fig. 2.5.

The SPECTRE RF simulated output frequency under locked condition as the varactors tuning voltage VTUNE varies from 0 to 1.5 V is shown in Fig. 2.11. Because the quality factor of the varactor decreases as the tuning voltage VTUNE decreases, the locking range at lower tuning voltage is larger than that at higher tuning voltage. The output frequency range of the K-band ILFT under free-running condition is from 22.98 GHz to 25.39 GHz. With a 4-dBm input signal, the output frequency range of the K-band ILFT under locked condition is from 21.54 GHz to 25.71 GHz. Therefore, the output frequency range extends from 2410 MHz to 4170 MHz. The simulated input power versus the output frequency when the input bias VBIAS is set at 0.65 V is shown in Fig. 2.12. The upper and lower locking ranges are labeled as the maximum and minimum output frequencies under locked condition, respectively. The locking range is from 30 to 690 MHz while the input power varies from –7 to 4 dBm.

2.2.2.2 V-band ILFT

The V-band ILFT is also designed in 0.13-μm CMOS technology. Due to the poor performance of varactor in V-band frequency, the varactors C1/C2 are not included in the V-band ILFT. Hence, the selected value of inductors L1/L2 is chosen so that they can resonate with the total parasitic capacitances at the drain of M3/M4 at the third-order harmonic frequency of input signal. The threshold voltage Vth in 0.13-μm CMOS technology is smaller than that in 0.18-μm CMOS technology so the input bias VBIAS for maximization of third-order harmonic current is 0.55 V. The device dimension for V-band ILFT is shown in Table 2.1 (b). The simulated power

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consumption of the V-band ILFT is 2.09 mW at a power supply of 1.2 V.

The SPECTRE RF simulated free-running V-band ILFT output after output buffer at time-domain and frequency-domain analysis are shown in Figs. 2.13 and 2.14, respectively. The free-running V-band ILFT provides the output amplitude of 127 mV as shown from transient simulation and output power of –8.9 dBm at 60.10 GHz as shown from FFT results. The simulated locked V-band ILFT output after output buffer with input power of 6 dBm, input frequency of 20.3 GHz, and VBIAS of 0.55 V at time-domain and frequency-domain are shown in Figs. 2.15 and 2.16, respectively. The simulated output spectrum of locked V-band ILFT is shown in Fig.

2.16 where the HRRs compared to the desired third-order harmonic are 19.08, 18.92, 29.47, 39.31 dBc for the first, second, forth, and fifth harmonics, respectively.

The SPECTRE RF simulated input power versus the output frequency with input bias VBIAS of 0.55 V is shown in Fig. 2.17. The locking ranges are 870 MHz, 1200 MHz, and 1590 MHz at the input power are 4dBm, 6dBm, and 9dBm, respectively. To simulate the phase noise relation between V-band ILFT input and output, a low-frequency VCO operated at the one-third of the V-band ILFT output frequency is designed and the VCO output is directly injected into the ILFT input. The SPECTRE RF simulated phase noise of V-band ILFT input and output with the offset frequency from 100 kHz to 100 MHz is shown in Fig. 2.18. The phase noise difference between input and output of V-band ILFT are 9.55, 9.6, and 12.5 dB at the frequency offset of 1 MHz, 10 MHz, and 100 MHz, respectively. At small frequency offset, these values are close to the theoretical limit 9.54 dB (=10log(3²)) as can be seen from (2.22).

2.2.3 Layout Consideration

Layout is an important issue in the millimeter-wave circuit design. There is a

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reason for explanation that the conventional layout parameter extractions (LPE) method is not suitable for such high frequency application. The interconnection inductance can not be extracted by LPE command. The interconnection inductance should be taken into consideration if the length of the metal line is longer than one-tenth of the wavelength. In the millimeter-wave frequency range, the wavelength is the order of hundreds μm. Therefore, the characteristics of those interconnection metal lines are simulated by the 3D EM CAD tool High-Frequency Simulation Software (HFSS).