Simulation Results of Phase-locked Loop

The simulated locked ILFM output waveform after output buffer is shown in Fig.

3.15(a). The simulated output power at the fifth-order harmonic is -12 dBm with frequency of 59.5 GHz as can be seen from Fig. 3.15 (b). The simulated phase noises of VCO output and ILFM output with the frequency offset from 10 kHz to 100 MHz are shown in Fig. 3.16. The phase noise differences between VCO output and ILFM output at 10 kHz, 1 MHz, and 100 MHz offset are 14.01 dB, 14.03 dB, and 16.5 dB, respectively. If the noise contribution from the frequency pre-generator is negligible, the output phase noise is 13.98 dB [=10log (5²)] higher than that from the input signal with a small frequency offset (3.7). Therefore, the noise contributions from the frequency pre-generator to the output phase noise at 10 kHz and 1 MHz are 0.03 dB and 0.05 dB, respectively.

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The tuning range of VCO is from 10.79 to 12.17 GHz with the control voltage VC form 0 to 1.5 volt as shown Fig. 3.17. The simulated VCO output waveform and output power spectrum with control voltage of 1.3 V are shown in Figs. 3.18(a) and 3.18(b) respectively. The output amplitude of VCO is around 573 mV.

The simulated waveforms of charge pump in charging mode in shown in Fig.

3.19. It can be seen from Figs. 3.19(a) and (b) that the rising edge of the reference clock is before that of the divider output. Therefore, charge pump charges the control voltage VC as shown in Fig. 3.19(c) for increasing the frequency of divider output until the rising edge of the divider output is the same as that of reference clock. On the other hand, the simulated waveforms of charge pump in discharging mode in shown in Fig. 3.20. Because the rising edge of the divider output is before that of the reference clock, charge pump discharges the control voltage VC to decrease the frequency of the divider output.

The simulated timing diagrams of the VCO and four stage CML divide-by-two frequency dividers are shown in Fig. 3.21. The amplitude of each divide-by-two frequency divider is increased with the decrease of the operational frequency. The timing diagram of the digital divide-by-two frequency divider is shown in Fig. 3.22.

The output amplitude is reached to full-swing for PFD operation.

Finally, the simulated settling time of the close-loop PLL with reference frequency fref of 360 MHz is shown in Fig. 3.23. The settling time is around 1.2 us for stable output control voltage VC. The overall circuit of the proposed PLL is shown in Fig. 3.24 where the dummy MOS in CML frequency divider block is designed for balance output waveform. In Table 3.3, the summary the post-simulation of the PLL is listed.

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3.4 EXPERIMENTAL RESULTS

The proposed 60-GHz PLL is designed and fabricated by using 0.18-μm Al 1P6M standard CMOS technology with ultra-thick metal of 2 μm. The chip microphotograph of the proposed PLL is shown in Fig. 3.25 where the chip area including all the test pads and dummy metal is 0.96 mm × 0.84 mm. An on-wafer measurement system incorporating a probe station, GSG coplanar probes, and high-speed cables is used to measure chip performance. Because the VCO output load including the ILFM and the frequency divider is large, the output signal from VCO is not directly connected to the testing pad. In order to check the function of the low-frequency PLL, the output signal from the first divide-by-two divider is connected to the testing pad. The measurement setup for 60-GHz PLL testing is shown in Fig. 3.26.

Due to the inaccuracy extraction of parasitic resistance and long cable line from power supply to test chip, the fabricated 60-GHz PLL can not worked under the supply voltage of 1.5 V. As the supply voltage is increased to 1.6 V, the function of the PLL is worked. Thus, the supply voltage is shift to nominal voltage 1.8 V of the 0.18-μm CMOS technology.

The total power dissipation of the fabricated 60-GHz PLL is 35.7 mW at a power supply of 1.8 V. The measured output spectrum of the locked ILFM is shown in Fig.

3.27 where all the losses from probe, cable, adaptors, and external harmonic mixer have been de-embedded. It can be seen from Fig. 3.27 that the proposed PLL structure provides the output power of –37.85 dBm with the output frequency of 58.0 GHz and 362.5-MHz reference frequency fref which is higher than the transition frequency fT. The output phase noises marked at 1 MHz and 10 MHz are measured as shown in Fig.

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3.28. The measured output phase noises at 1 MHz and 10 MHz offset from the carrier are –85.2 and –90.9 dBc/Hz, respectively.

Because of the large conversion loss from the external harmonic mixer and the small output power from the fabricated chip, the high-resolution setup for the spectrum analyzer is required in the reference spur measurement [22]. To reduce the time-cost of the high-resolution setup, a V-band (low-noise amplifier) LNA is added before the external harmonic mixer. The output power to the spectrum analyzer is therefore large enough to reduce the resolution requirement. The measurement setup for output reference spur testing is shown in Fig. 3.29. As can be seen from the measurement results in Fig. 3.30, the measured reference spur level is –40.16 dBc.

Because of the cross-product between output frequency and reference spurs in the frequency pre-generator stage, the frequency offset between the carrier and the spur tone is therefore the same as the reference frequency.

The performance of the first divide-by-two frequency divider is also measured.

The measured output power of –16.55 dBm at 5.8 GHz output frequency is shown in Fig. 3.31. The measured phase noise of the first divide-by-two frequency divider output from 100 Hz to 100 MHz is shown in Fig. 3.32. The measured output phase noises at 100 kHz, 1 MHz, and 10 MHz offset from the carrier are –102, –108, and –121 dBc/Hz, respectively. The phase noise difference between the ILFM output and the first divide-by-two frequency divider output at 1 MHz offset is 22.8 dB which is 2.8 dB higher than the theoretical limit 20 dB [=10log(10²)] as can be seen from Fig.

3.28 and Fig. 3.32. The output waveform of the divider is tested by the high-speed oscillator. It can be seen from Fig. 3.33 that the output amplitude is around 50 mV with cable and adaptor losses.

Because the measured output power is much lower than that in the simulation

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result and the output frequency range is larger then that in the simulation result, the measurement for only ILFM is executed. To further discuss the performance of the ILFM, a laser cut is executed to turn off VCO shown in Fig. 3.34. Without the input signal from VCO, the performance of the free-running ILFM can be measured. It can be seen from Fig. 3.35 that there is no free-running output signal of ILFM. Therefore, the performance of ILFM is like the conventional frequency multiplier with high quality factor LC-tank as a load. Because the operational frequency of ILFM is higher than device transition frequency and the valid frequency of device model is not covered the entire frequency of interest, the models for active devices are not accurate.

In Table 3.4, the recently-published CMOS FS’s and PLLs worked at the V-band are compared with the proposed PLL. It can also be seen that the proposed PLL can operate with lower dc power consumption and better phase noise. Because the CP is not current-match structure and larger VCO gain in this work, the reference spur is not as good as in the pervious work. In addition, due to the operational frequency is higher than the device transition frequency of 180-nm device in the output buffer, the output power level is only –37.85 dBm. Finally, this design is the first CMOS PLL integrated with the ILFM in the millimeter-wave band.

3.5 SUMMARY

The proposed PLL integrated with the novel CMOS ILFM for 60-GHz applications is designed and fabricated using 180-nm standard CMOS technology.

The proposed ILFM circuit is introduced to multiply the frequency by five times and successfully co-designed with a low-frequency PLL. As can be seen from the

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measurement results, the ILFM has a great potential in the applications of LO signal generators for high-frequency PLL design. In addition, the maximum operational frequency of the frequency divider in a PLL can be reduced to only one-fifth by use of the proposed ILFM.

The recently published CMOS FS’s and PLLs [81]–[91] are shown in Fig. 3.36.

The total power consumption is increased as the operational frequency is increased.

The proposed PLL can be operated with lower power consumption and higher operational frequency. The output powers for recently published CMOS FS’s and PLLs are shown in Fig. 3.37. Due to the poor device performance and without free-running output, the proposed PLL provides smaller output power as compared to the expected output power. Finally, since it is feasible to design a high-performance VCO at low frequency and to save the large power consumption from full-speed frequency dividers, the proposed PLL structure provides a solution to the low-power and high-performance PLL for 60-GHz applications.

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Table 3.1

Dimensions of devices in VCO and ILFM.

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Table 3.2

Dimensions of devices in four stage CML divide-by-two frequency dividers.

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Table 3.3

Summary of the post-simulation results.

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Table 3.4

Comparison with recently published V-band CMOS FS’s and PLLs.

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Fig. 3.1 The general model of ILFM.

Fig. 3.2 Simplified noise source model for ILFM.

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Fig. 3.3 Block diagram of a typical PLL.

Fig. 3.4 The linear phase-domain PLL model.

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Fig. 3.5 Loop filter in a third-order PLL.

Fig. 3.6 PLL noise model.

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Fig. 3.7 Block diagram of the proposed 60-GHz PLL.

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Fig. 3.8 Circuit diagram of both VCO and ILFM.

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Fig. 3.9 Simulated output buffer loss.

Fig. 3.10 HSPICE simulated coefficient of output harmonic current as a function of conduction angle.

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(a)

(b)

Fig. 3.11 Simplified schematic of (a) CML static divider and (b) digital static divider.

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(a)

(b)

Fig. 3.12 PFD (a) state diagram and (b) timing diagram.

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Fig. 3.13 Simplified schematic of the PFD.

Fig. 3.14 Circuit diagram of the charge pump and loop filter.

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(a)

(b)

Fig. 3.15 Simulated ILFM output (a) waveform and (b) power spectrum.

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Fig. 3.16 Simulated output phase of VCO and ILFM.

Fig. 3.17 Simulated VCO control voltage VC versus output frequency.

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(a)

(b)

Fig. 3.18 Simulated VCO output (a) waveform and (b) power spectrum.

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(a)

(b)

(c)

Fig. 3.19 Simulated waveforms of (a) reference clock, (b) divider output, and (c) control voltage of VCO with charging mode of charge pump.

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(a)

(b)

(c)

Fig. 3.20 Simulated waveforms of (a) reference clock, (b) divider output, and (c) control voltage of VCO with discharging mode of charge pump.

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Fig. 3.21 Timing diagrams of VCO, first stage divider, second stage divider, third stage divider, and fourth stage divider.

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Fig. 3.22 Timing diagrams of the last digital frequency divider output waveform.

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Fig. 3.23 Simulated waveform of control voltage VC in close-loop simulation.

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Fig. 3.24 Circuit diagram of the overall PLL.

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Fig. 3.25 Chip microphotograph of the proposed 60-GHz PLL (0.96 mm × 0.84 mm).

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Fig. 3.26 Measurement setup for 60-GHz PLL testing.

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Fig. 3.27 Measured Output spectrum of the 60-GHz PLL with 362.5-MHz reference frequency fref.

Fig. 3.28 Measured output phase noise marked at the offset frequency of 1MHz and 10 MHz.

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Fig. 3.29 Measurement setup for the reference spurs testing.

Fig. 3.30 Measured reference spurs as the reference frequency of 359.7 MHz.

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Fig. 3.31 Measured output spectrum of the first divide-by-two frequency divider.

Fig. 3.32 Measured phase noise of the first divide-by-two frequency divider.

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Fig. 3.33 Measured output waveform of the first divide-by-two frequency divider.

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Fig. 3.34 The microphotograph of the laser cut position.

Fig. 3.35 Measured the output spectrum of the free-running ILFM.

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Fig. 3.36 Power consumption as a function of output frequency.

Fig. 3.37 Output power as a function of output frequency.

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CHAPTER 4

60-GHZ CMOS DIRECT-CONVERSION