1.2.1 Frequency multiplier
There are two methods to generate local oscillator (LO) signals. In the first method, LO signals are generated directly by using fundamental frequency oscillators [6]–[10]. In the second one, they are generated by using lower frequency oscillators cascaded with frequency multipliers to obtain signals at the desired frequencies [11]–[19]. Because of the limited performance of active and passive devices at high frequency, it is easier to design high-performance voltage-controlled oscillators (VCOs) at low frequency rather than at high frequency. Moreover, high frequency dividers operated at the carrier frequency with a significant amount of power dissipation are not needed when using a low frequency VCO. Therefore, the second method is advantageous in low-power CMOS circuit implementation in the millimeter-wave band.
In general, a frequency multiplier can be divided into two stages: the harmonic generation stage and the LO amplification stage. The harmonic generation stage is designed to generate the signal at the desired harmonic and the LO amplification stage
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is designed to amplify the output amplitude at the desired frequency. Because large output amplitude is provided by the LO amplification stage, a large power consumption is required for driving output swing. Thus, a frequency multiplier with a significant amount of power dissipation is the main drawback [11]–[18]. It can be seen from Fig. 1.3, the power consumption of frequency multiplier is increased as the increase of output frequency of frequency multiplier. As a result, the key design requirement of the second method is to increase the frequency conversion gain of the frequency multipliers. In order to achieve this requirement, low input power and low dc power consumption are necessary to obtain the desired output power level.
Frequency multipliers integrated with injection-locked oscillators (ILOs) [20]–[25] can efficiently increase the conversion gain because ILOs have the superior properties of frequency stabilization and high conversion gain with a narrow bandwidth [26]. Such a frequency multiplier with ILO is called the subharmonic injection-locked frequency multiplier (ILFM). It offers great potential use with millimeter-wave frequency synthesizers because of its low input power and low dc power consumption. Even with low input power, the subharmonic ILFM [20]–[25]
can provide the same performance as a conventional frequency multiplier [27].
1.2.2 Phase-locked Loop and Frequency Synthesizer
Frequency synthesizer (FS) is a key building block of the radio-frequency integrated circuits (RFICs), which generates the carrier signal to convert transmission data up to the desired frequency band. The transmission and reception qualities in the wireless communication system are determined by the performance of LO that is generated by the FS.
In the conventional FS [28]–[31], VCO is always operated at the highest
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frequency to generate the LO signal as shown in Fig. 1.4. The output frequency fout of VCO is M-times of input reference frequency fref under locked condition. Owing to the limited performance of the active and passive devices, the performance of the VCO is mainly determined by the device technology.
The implementation of the high-frequency divider is another important design issue in the conventional FS structure. The injection-locked frequency dividers (ILFDs) [32]–[39] or Miller divider [40]–[42] are the popular options for the high-frequency divider design. It can be seen from Fig. 1.5 that ILFDs can be operated under small power consumption but they are of narrow band characteristics.
Any frequency shift in these dividers can cause the failure of the whole FS. Another high-speed frequency divider is current-mode logic (CML) divider [43]–[52]. The CMOS CML divider has been demonstrated to have high-speed operation with low power dissipation because the full swing for internal operation is not required. As can be seen from Fig. 1.6, the operational frequency of recently published CMOS CML divider without inductor is still lower than 60 GHz. Therefore, ILFD is the only one solution for 60-GHz frequency divider. Overdesign for locking range to avoid frequency shift is required. As a result, the output frequency range of conventional FS operated around 60 GHz can not be too large.
The other FS structure is composed of a low-frequency FS cascaded with a frequency multiplier to generate the desired output frequency as shown in Fig. 1.7. So far, there is no prior design with this FS structure in CMOS technology. In this FS structure, the low-frequency FS is operated at the subharmonic of the desired frequency and the target frequency is generated by the frequency multiplier after the low-frequency FS [53]–[55]. Obviously, it has the advantages of smaller division ratio and low power dissipation from the frequency divider. Therefore, the second FS
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structure can be attractive for CMOS design in the millimeter-wave band if the high-frequency and low-power CMOS frequency multiplier can be developed.
The comparison of FS architectures is listed in Table 1.2. A high-performance and wide tuning range VCO can be designed in the subharmonic FS integrated with frequency multiplier due to lower operational frequency. Moreover, the division ratio of frequency divider can be lower than that of fundamental FS to reduce the power consumption. However, large power consumption is required as the operational frequency of frequency multiplier is high such as millimeter-wave band. Finally, because the last stage of the subharmonic FS structure is frequency multiplier, the output signal is usually mixed with the total harmonics of VCO output frequency.
Hence, extra effort to suppress undesired harmonics is required.
As described in Section 1.2.1, the large power consumption from frequency multiplier can be reduced significantly by using ILO. ILO chain can become a possible solution to millimeter-wave MMIC synthesizers [53].
1.2.3 Receiver
So far, some 60-GHz receivers have been demonstrated in CMOS technology [18]–[19], [56]–[64]. The homodyne receiver architecture is firstly implemented in the millimeter-wave receivers [56]–[59] because of its advantages of high integration and low system complication. The block diagram of the homodyne receiver is shown in Fig. 1.8. The radio-frequency (RF) signal is directly mixed with the local oscillator (LO) at the carrier frequency. Since the intermediate frequency (IF) is zero, the homodyne receiver is also called as zero-IF receiver or direct-conversion receiver.
Because the frequency of LO signal must be the same as the received frequency, the dc offset effect from the LO leakage by capacitive and substrate coupling [65] is
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serious. Two main sources of dc offsets are shown in Figs. 1.9 (a) and (b). The first source is the LO leaking to the low-noise amplifier (LNA) input and mixing with itself at the MIXERRF. The second source is the large nearby interferers leaking into VCO and then self-mixing.
Recently, a novel dc offset cancellation circuit has been proposed with simple Miller capacitor filter [66]. However, high-frequency synthesizer and high-frequency dividers with large power consumption are required. Due to large power consumption, the homodyne receiver structure is not suitable for consumer mobile applications.
The heterodyne receiver architecture is the one solution for the high-frequency synthesizer because the frequency of LO signals can be lower than received frequency as shown in Fig. 1.10 [60]–[64]. However, twice frequency translations make that the architecture of the receiver more complicated and image signal rejection is required for better signal-to-noise ratio (SNR). As compared with Fig. 1.8, the extra filters for frequency selection, BPFRF and BPFIF, are required. Therefore, the system complication is increased. Moreover, more inductors are required for system integration. Hence, total chip area is increased as compared with direct-conversion receiver.
Another solution for the high-frequency synthesizer is the frequency multiplier as shown in Fig. 1.11 [18]–[19]. The new CMOS frequency doubler [18] and frequency tripler [19] for the LO generation is proposed. Because of the even order frequency multiplier, the differential output can not be provided for the mixer operation. Thus, the extra effort is required for single to differential converter [18].
The first millimeter-wave CMOS frequency tripler is introduced in [19]. Due to its fully differential structure of frequency tripler, it is suitable for complex modulation schemes.
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The comparison of receiver architectures is listed in Table 1.3. The homodyne receiver can achieve high-integration and low-power consumption, but the operational frequency of frequency synthesizer is the highest. The heterodyne receiver can be operated with lower operational frequency synthesizer but its system is too complex for millimeter-wave circuits. Finally, the homodyne receiver integrated with frequency multiplier is the best choice for high-frequency receiver design it has the advantages of homodyne receiver and the lower operational frequency of frequency synthesizer.