Overall Circuits

The overall circuit of the proposed direct-conversion receiver is shown in Fig.

4.10 where the output buffer is not drawn. The device parameters of the whole receiver are listed in Table 4.2.

The RF input signal VRF is applied to the input nodes of the LNA. The LNA amplifies the RF signal to provide reasonable gain to suppress the noise contribution from the subsequent stages. The LNA output is connected to I/Q down-conversion mixers. By mixing with LO signals (LOI and LOQ) provided by the ILFTs and the

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QVCO, the frequency at mixer output is translated to zero-IF. The extra gain is given by the IFAs, and the output buffers are designed for test purposes to drive the 50-ohm loads.

LO signals (LOI and LOQ) are generated by I/Q ILFTs by taking the third-order harmonic frequency of QVCO output. The performance of ILFTs outputs are, therefore, determined by the performance of QVCO. To get the better QVCO performance, the ratio of better ratio of the cross-couple pairs (MVCO1–MVCO4) and ring oscillator (MVCO5–MVCO8) is chosen [101].

4.4 EXPERIMENTAL RESULTS

The proposed 60-GHz direct-conversion receiver front-end is designed and fabricated using 0.13-μm 1P8M Cu CMOS technology with ultra thick metal of 3.3 μm. The chip microphotograph of the proposed direct-conversion receiver is shown in Fig. 4.11; the chip area including all the test pads and dummy metals is 1.21 mm × 1.03 mm. An on-wafer measurement system incorporating a probe station, GSG coplanar probes, GSGSG differential coplanar probes, high-speed cables is used to measure chip performance. The measurement setup for 60-GHz direct-conversion chip testing is shown in Fig. 4.12.

The total power dissipation of the fabricated direct-conversion receiver is 31.0 mW under a 1.2-V supply voltage. The simulated and measured input return loss (S11) at the RF port with the frequency range from 54 to 66 GHz is shown in Fig. 4.13. It can be seen from Fig. 4.13 that the measured S11 is lower than –10 dB as RF frequency is close to 60 GHz. The measured S11 is better than –8 dB with the frequency range from 57 to 66 GHz.

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The measured output frequency of QVCO versus control voltage VC from 0 to 1.2 V is measured by the observation of the QVCO leakage from IF port. It can be seen from Fig. 4.14 that the measured QVCO output frequency is shifted to lower frequency around 2.5-GHz as compared with the simulated results. Because the model of the two-turn symmetric inductor is calculated by the interpolation from one-turn and three-turn symmetric inductors, the accuracy of the interpolation method is verified by the 3D EM CAD tool HFSS. The 3D-view of the inductors and interconnection metals are shown in Fig. 4.15. All active devices are removed and replaced as a grounded metal. The HFSS EM simulation and measurement results of QVCO output frequency versus control voltage VC from 0 to 1.2 V are shown in Fig.

4.16. The whole EM simulation result can be closer to measurement result with frequency offset around 1 GHz. The 1-GHz frequency offset can be explained as the process variations.

The simulated and measured whole receiver power gain and single-side band (SSB) NF with RF frequency range of 51.5 GHz to 55.03 GHz and inter-mediate (IF) frequency of 100 MHz are shown in Fig. 4.17. Due to modeling inaccuracies of the inductor and transmission line characteristic and possibly transistor capacitances from QVCO, the measured frequency range is not the same as expected frequency range.

The maximum receiver power gain is 18.2 dB and the minimum SSB NF is 16.96 dB at 55.03-GHz RF frequency. The measured RF frequency range is limited by the tuning range of QVCO.

The measured 3-dB channel bandwidth with fixed LO frequency of 55.02 GHz is shown in Fig. 4.18. The measured channel bandwidth of 2 GHz is achieved for high-speed data transmission. In addition, the measured bandwidth is only 160 MHz smaller than the possible specifications for full-rate data transmission shown in

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Chapter 1. The asymmetric frequency response can be explained that the magnitude response of LNA is asymmetric. Thus, the power gain provided by LNA is larger at higher frequency.

The linearity performance of the proposed receiver is shown in Figs. 4.19 and 4.20. The measured input-referred 1-dB compression point (P1dB) is about –17.0 dBm with RF frequency of 55.03 GHz and IF frequency of 100 MHz. The two tone test for the input third order inter-modulation intercept point (IIP3) with the RF frequency of 55.04 and 55.03 GHz is also measured. The measured IIP3 is around –7.6 dBm as can be seen from Fig. 4.20.

The output waveforms of I- and Q- channel IF signals are measured by real-time oscilloscope. The output waveforms with IF frequencies of 500 MHz, 100 MHz, and 50 MHz are shown in Fig. 4.21, 4.22, and 4.23, respectively. The amplitude and phase imbalance between I- and Q- channels at 100-MHz IF frequency are around 1.58 dB and 17°, respectively.

The amplitude imbalance of I- and O-channel can be minimized by using an automatic gain control (AGC) circuits. However, the effect of phase imbalance can not be reduced by using extra calibration circuits. The signal constellations of QPSK with ideal I/Q phase and non-ideal I/Q phase are shown in Figs. 4.24 (a) and (b), respectively. In Fig. 4.24 (a), ideal I- and Q-channel are performed. The BER PE1 is calculated by using a normal distribution function. In Fig. 4.24 (b), a phase imbalance is existed and the BER PE2 is larger than ideal case PE1 in Fig. 4.24 (a). In order to maintain the required BER in digital section, the minimum required SNR at the baseband should be increased. Therefore, the sensitivity of whole receiver system is decreased.

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To further discuss the phase mismatches of IF signals, the QVCO output phase imbalance versus control voltage VC from –0.2 to 1.4 V is shown in Fig. 4.25 where the model for passive inductors and interconnection metals are simulated from Fig.

4.15 and the phase imbalance is defined as the phase difference between I- and Q- channel output. It can be seen from Fig. 4.25 that phase imbalance is introduced by asymmetric two-turn inductors and interconnection metals. However, the asymmetric performance of inductors can not be found from HSPICE models. The phase mismatch is from –0.57° to 3.44° with the control voltage VC from –0.2 to 1.4 V.

Therefore, the phase imbalance at the output of ILFTs is –1.71° to 10.32°. These values are close to the measurement results.

Because the control voltage VC is not controlled by a close-loop phase-locked loop, the control voltage node is directly fed by a power supply. The measured VCO gain is very large, 5000 MHz/Volt. It is very difficult to measure the IF signal with frequency lower than 1 MHz as the dc output of a power supply is not very clear.

Therefore, the performances of dc offset and flicker noise cannot be measured in the current receiver version.

Finally, the single carrier modulation scheme is specified in the 60-GHz communication system. The distance between each carrier is 2160 MHz which is larger then required IF bandwidth. Thus, second-order input intercept point (IIP2) is not measured.

In Table 4.3, the recently published CMOS receivers worked at the V-band are compared with the proposed receiver. It can be seen that the proposed receiver can be operated with lower dc power consumption and small chip area. In [102], QVCO and Q-path modulator are not included so its chip area and power consumption is small.

Additionally, the proposed receiver can provide an IF bandwidth of 1 GHz that is

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close to the specification frequency plan. The proposed receiver provides a high-integration and low power choice for 60-GHz receiver design. The NF is highest because the gain which is provided by LNA is not large enough. Probably RF frequency is not in the LNA bandwidth. In summary, the main drawback of the proposed receiver is large NF as compared with receiver integrated with conventional frequency multiplier. However, high NF problem can be solved by increasing the gain of LNA. This design is the first CMOS receiver integrated with the ILFTs in the millimeter-wave band.

4.5 SUMMARY

The 60-GHz direct-conversion receiver front-end integrated with ILFTs is designed, fabricated, and measured. Because the output frequency of QVCO is shift to 18.3-GHz, the maximum operational frequency of the direct-conversion receiver is only 55-GHz. The reason of frequency offset is verified by 3-D EM simulator HFSS.

The modeling inaccuracies of the inductors and transmission lines characteristics are main reasons for the output frequency shift. Thus, the measured RF frequencies are not the same as expected frequency range.

In addition, the phase imbalance of I- and Q-channel outputs is discussed due to the asymmetric two-turn inductors and interconnection metals. Because I/Q ILFTs are designed after QVCO, the phase imbalance from QVCO is amplified three-times at the ILFTs outputs. Therefore, the phase mismatch is large at the IF outputs. The solution to phase mismatch is to add a ring oscillator between I/Q ILFTs [23]. The ILFTs output phases can be forced to quadrature phase by the additional ring oscillator. The phase imbalance can be also reduced by using careful layout for

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QVCO.

Finally, because the rejection ability to fundamental signal is around 20 dB in the post-simulation of IFLT, the 20-GHz signal from ILFT is also injected into switching stage of mixer. Due to the nonlinear characteristic of switching stage, the RF signal is also translated to IF section by mixing with 20 GHz signal. The NF is increased by the undesired signal. In the post-simulation results, the 20-GHz signal at the switching stage input is very small. The nonlinear characteristic generated by the signal can be neglected. Therefore, the effects of undesired harmonics in the ILFT output are not important as a direct-conversion receiver integrated with ILFT.

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Table 4.1

Link budget analysis for 60-GHz wireless communication.

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Table 4.2

Design target of receiver front-end.

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Table 4.3

Dimensions of devices in 60-GHz direct-conversion receiver.

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Table 4.4

Comparison with Recently published V-band CMOS receivers.

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Fig. 4.1 The equivalent system for multi-stage system.

Fig. 4.2 The property and definition of IIP3.

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Fig. 4.3 Block diagram of the proposed direct-conversion receiver.

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Fig. 4.4 Circuit diagram of the two-stage 60-GHz LNA.

Fig. 4.5 Simplified schematic of down-conversion mixer.

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Fig. 4.6 Circuit diagram of the QVCO.

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Fig. 4.7 Simulated I/Q phase imbalance with 10-% channel width mismatch of the transistor in the even-stage ring oscillator.

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Fig. 4.8 Circuit diagram of the ILFT.

Fig. 4.9 Circuit diagram of the IF amplifiers and output buffers for I-channel.

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Fig. 4.10 Complete circuit diagram of the proposed 60-GHz direct-conversion receiver.

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Fig. 4.11 Chip microphotograph of the 60-GHz direct-conversion receiver (1.21 mm

× 1.03 mm).

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Fig. 4.12 Measurement setup for 60-GHz direct-conversion receiver testing.

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Fig. 4.13 Simulated and measured input matching (S11) with frequency range from 54 to 66 GHz.

Fig. 4.14 Simulated and measured QVCO output frequency versus control voltage VC.

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Fig. 4.15 3D-view of the inductors and interconnection metals for EM simulation.

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Fig. 4.16 Measured and EM simulated LO frequency versus control voltage VC.

Fig. 4.17 Simulated and measured receiver gain and SSB NF with IF frequency of 100 MHz.

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Fig. 4.18 Measured 3-dB channel bandwidth with LO frequency of 55.02 GHz.

Fig. 4.19 Measured P1dB with RF frequency of 55.03 GHz and IF frequency of 100 MHz.

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Fig. 4.20 Measured IIP3 with RF frequency of 55.03 and 55.04 GHz.

Fig. 4.21 Measured output waveforms with RF frequency of 55.07 GHz and IF frequency of 500 MHz.

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Fig. 4.22 Measured output waveforms with RF frequency of 55.03 GHz and IF frequency of 100 MHz.

Fig. 4.23 Measured output waveforms with RF frequency of 55.025 GHz and IF frequency of 50 MHz.

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(a) (b)

Fig. 4.24 The signal constellation and probability distribution of QPSK with (a) an ideal phase of I/Q channel and (b) a phase imbalance of I/Q channel.

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Fig. 4.25 EM simulated phase imbalance of QVCO outputs.

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CHAPTER 5