Chapter 3 Low-Power UWB LNA Design using Forward Body Biasing
3.4 Chip Circuit Design and Simulation
3.4.2 RF Circuit Simulation for UWB LNA Design
The whole circuit schematics for the proposed UWB LNA is illustrated in Fig. 3.22 in which three major blocks such as input matching network, amplifying stage (cascode), and output buffer are included and the layout dimensions for active transistors and parasitic elements (R, L, C) are remarked for simulation. Note that all the components in this design, including spiral inductors, metal-insulator-metal (MIM) capacitors and resistors, are realized on chip. Fig. 3.23 depicts the chip layout of the proposed UWB LNA. The chip area occupied by the core circuits of LNA and probing pads in peripheral region is 0.637x0.892 mm2. The details of circuit topology analysis and operation principles have been introduced in sections 3.2~3.3. The proposed UWB LNA is simulated with Agilent ADS simulator using TSMC 0.13μm mixed-signal 1.2/2.5V RF CMOS Model. In the following, the simulation results will be presented, including pre-layout and post-layout under typical (TT) and corner conditions (FF, SS). For this UWB LNA design, the key performance parameters, such as power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S12), noise figure (NF), stability, and third-order intercept point (IIP3) have been calculated by ADS simulation. Fig.
3.24 ~ 28 show pre-layout simulation results, under the typical condition of VDD=0.9V, VG=0.4V, and a wide range of frequencies in 2~11 GHz. Note that the third-order intercept point (IIP3) shown in Fig. 3.28 is determined by two-tone test with tone space of 10MHz, and fundamental frequency at 4GHz and 10GHz. Fig. 3.29 ~ 33 indicate the pre-layout simulation for mentioned performance parameters, with a comparison under typical (TT) and corner conditions (FF, SS). The comparison is summarized in Table 3.2. As for the differences from post-layout, Fig. 3.34 ~ 38 present a comparison for all of the performance parameters, between pre-layout and post-layout simulation. Fig. 3.39 shows the Post-simulated stability.
Fig. 3.40 shows the Post-simulated IIP3 at 4 GHz and 10 GHz. Table 3.3 shows the post-simulation results summary of typical and corner case. The performance of the proposed
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UWB LNA is summarized in Table 3.4.
RF Input
RF Output VDD
Vbias RF_PAD
RF_PAD M2
DC_PAD
DC_PAD
C4
C5
(1.4p)
(1.4p)
(0.4V)
(0.9V)
mimcapC1
lt=27um wt=25um C=711fF
M1
M3
Fig. 3. 22 Circuit schematic of the UWB LNA with three core circuit blocks in which the active and passive devices dimensions are provided
Fig. 3. 23 Chip layout of the UWB LNA
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Fig. 3. 25 Pre-layout simulation for reverse isolation (S12) VDD=0.9V, VG=0.4V, frequency=2~11 GHz.
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2 3 4 5 6 7 8 9 10 11
0 2 4 6 8 10
Pre-sim
NF ( d B)
Frequency (GHz)
Fig. 3. 26 Pre-layout simulation for noise figure (NF). VDD=0.9V, VG=0.4V, frequency=2~11 GHz.
2 3 4 5 6 7 8 9 10 11
0 1 2 3 4 5 6 7 8 9 10
μ ( S tabi lit y )
Pre-sim
Frequency (GHz)
Fig. 3. 27 Pre-layout simulation for stability. VDD=0.9V, VG=0.4V, frequency=2~11 GHz.
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Fig. 3. 28 Pre-layout simulation for third-order intercept point (IIP3) (a) 4GHz : IIP3 =-10dBm (b) 10GHz IIP3=-11dBm. Two-tone test with tone spacing of 1MHz.
VDD=0.9V, VG=0.4V.
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Fig. 3. 29 Pre-layout simulation for power gain (S21), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz.
Fig. 3. 30 Pre-layout simulation for input return loss (S11), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz
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Fig. 3. 31 Pre-layout simulation for output return loss (S22), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz
Fig. 3. 32 Pre-layout simulation for reverse isolation (S12), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz
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Fig. 3. 33 Pre-layout simulation for noise figure (NF), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz.
Table 3. 2 Pre-layout simulation results, under typical and corner conditions
Pre-layout simulation
RF Corner Unit TT FF SS
Frequency GHz 3.1 ~ 10.6 3.1 ~ 10.6 3.1 ~ 10.6
Power (only core LNA) mW 4.7 7.9 2.5
Power (total) mW 8.3 11.1 6.6
Supply Volatge (VDD) V 0.9 0.9 0.9
Bias current (only core LNA) mA 5.23 8.75 2.80
Bias current (total) mA 9.18 12.30 7.36
Gain(S21)max / Gain(S21)min dB 17.3 / 11.2 16.3 / 9.6 16.5 / 10.2
NF - min / max dB 2.7 / 4.1 2.4 / 4.0 3.3 / 5.1
Input Return Loss (S11) dB < -8.6 < -8.5 < -7.6 Output Return Loss (S22) dB < -10.1 < -9.4 < -10.8
IIP3 dBm -10@4GHz,-11@10GHz -11@4GHz,-11@10GHz -7@4GHz,-6@10GHz
Reverse isolation (S12) dB < -43.6 < -41.1 < -45.8
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0 2 4 6 8 10 12
-10 -5 0 5 10 15 20
S2 1 ( dB)
Frequency (GHz)
Pre-sim Post-sim
Fig. 3. 34 Comparison between pre-layout and post-layout simulation results for the power gain(S21). VDD=0.9V, VG=0.4V, frequency=2~11 GHz.
0 2 4 6 8 10 12
-25 -20 -15 -10 -5 0
Frequency (GHz)
Pre-sim Post-sim
S11 (d B)
Fig. 3. 35 Comparison between pre-layout and post-layout simulation results for the input return loss (S11). VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.
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0 2 4 6 8 10 12
-30 -25 -20 -15 -10 -5 0
S22 ( d B )
Frequency (GHz)
Pre-sim Post-sim
Fig. 3. 36 Comparison between pre-layout and post-layout simulation results for the output return loss (S22). VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.
0 2 4 6 8 10 12
-100 -90 -80 -70 -60 -50 -40
Pre-sim Post-sim
S1 2 ( d B)
Frequency (GHz)
Fig. 3. 37 Comparison between pre-layout and post-layout simulation results for the reverse isolation (S12). VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.
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Fig. 3. 38 Comparison between pre-layout and post-layout simulation results for noise figure (NF). VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.
Fig. 3. 39 Comparison between pre-layout and post-layout simulation results for stability.
VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.
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Fig. 3. 40 Post-layout simulation for third-order intercept point (IIP3) (a) 4GHz : IIP3 = -11dBm (b) 10GHz IIP3= -10dBm. Two-tone test with tone spacing of 1MHz.
VDD=0.9V, VG=0.4V.
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Table 3. 3 Post-layout simulation results, under typical and corner conditions
Post-layout simulation
RF Corner Unit TT FF SS
Frequency GHz 3.1 ~ 10.6 3.1 ~ 10.6 3.1 ~ 10.6
Power (only core LNA) mW 4.7 7.9 2.5
Power (total) mW 8.2 11.0 6.6
Supply Volatge (VDD) V 0.9 0.9 0.9
Bias current (only core LNA) mA 5.23 8.74 2.80
Bias current (total) mA 9.10 12.20 7.31
Gain(S21)max / Gain(S21)min dB 17.2 / 8.4 16.1 / 8.0 16.2 / 5.7
NF - min / max dB 2.8 / 6.5 2.5 / 5.0 3.4 / 8.8
Input Return Loss (S11) dB < -8.3 < -8.2 < -7.5 Output Return Loss (S22) dB < -10.3 < -9.7 < -10.9
IIP3 dBm -11@4GHz,-10@10GHz -12@4GHz,-11@10GHz -7@4GHz,-4@10GHz
Reverse isolation (S12) dB < -46.1 < -43.7 < -47.4
Table 3. 4 Comparison of pre-layout and post-layout simulation results (typical condition)
Specification Unit Pre-sim Post-sim
Frequency GHz
Power (only core LNA) mW 4.7 4.7
Power (total) mW 8.3 8.2
Supply Volatge (VDD) V 0.9 0.9
Bias current (only core LNA) mA 5.23 5.23
Bias current (total) mA 9.18 9.10
Gain(S21)max / Gain(S21)min dB 17.3 / 11.2 17.2 / 8.4
NF - min / max dB 2.7 / 4.1 2.8 / 6.5
Input Return Loss (S11) dB < -8.6 < -8.3 Output Return Loss (S22) dB < -10.1 < -10.3
IIP3 dBm -10@4GHz,-11@10GHz -11@4GHz,-10@10GHz
Reverse isolation (S12) dB < -43.6 < -46.1
Chip size mm2
3.1 ~ 10.6
0.637x0.892
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