Measurement Results and Discussion - Low-Power UWB LNA Design using Forward Body Biasing

Chapter 3 Low-Power UWB LNA Design using Forward Body Biasing

3.5 Measurement

3.5.2 Measurement Results and Discussion

Fig. 3.43 presents the performance measured from this UWB LNA fabricated in 0.13μm 1.2V RF CMOS process. The comparisons between the measurement and post-layout simulation are demonstrated for power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S12), noise figure (NF) and stability, shown in Fig. 3.43(a)~(f). Fig.

3.44 indicates the measured third-order intercept point (IIP3) in which the IIP3 can reach 12dBm and 5dBm at 4GHz and 10GHz, respectively. Table 3.5 summarizes all of the performance parameters from our designed UWB LNA, and the comparison with post-layout simulation. The one-to-one comparison between measured data and simulation reveals an obvious degradation in the power gain (S21) while a significant improvement on the linearity in terms of IIP3. The power gain achievable from this UWB LNA is S21=5.0~10.8 dB over the bandwidth of 3.1 ~ 8.1 GHz, which are around 6/3.4 dB lower than the maximum/minimum gain predicted by simulation. As for the linearity, the measured IIP3 are as high as 12/5 dBm at 4/10 GHz, which are much better than the simulated IIP3 of –11/-10 dBm. The degradation of power gain, particularly worse in higher frequencies suggests that shunt peaking method cannot exactly meet the design target from simulation. The process variation induced shift in inductance (Ld) and resistance (Rd) is considered as one major root cause responsible for S21

degradation, and the power loss through the parasitic capacitance to the lossy Si substrate is proposed as the underlying mechanism. This kind of power loss generally increases dramatically when increasing frequency. Referring to (3-8), Cout representing the sum of junction and gate capacitances given as C_out =C_db₂+C_gd₃+C_dg₂+C_gs₃(1−K) in (3-11) becomes a critical coupling path for power loss. Besides, Cgs of M2 (Fig.3.1) offers one more path for power loss at high frequency. The input matching circuits are justified by the acceptable match in S11 but somewhat more deviation is revealed in output matching in terms of S22. The measured NF is close to the simulated performance over the broadband of

frequencies. This is an important achievement for LNA design and suggests the success of noise shielding technique using guard rings and ground shielding under the pads and transmission lines. Finally, an extensive performance benchmark with the state-of-the-art techniques in latest publications [5, 24, 35, 42, 43] has been done and summarized in Table 3.6. This benchmark indicates that our designed UWB LNA demonstrates the advantages of lower power, lower NF, and higher linearity (IIP3) under comparable gain and bandwidth.

These advantages prove that the proposed UWB LNA can be realized by standard RF CMOS process and applied to UWB system applications.

0 1 2 3 4 5 6 7 8 9 10 11 12

Fig. 3. 43 UWB LNA chip measured results and comparison with post-layout simulation for (a) power gain (S21) (b) input return loss (S11) (c) output return loss (S22) (d) reverse isolation (S12) (e) noise figure (NF) (f) stability

Fig. 3. 44 UWB LNA chip measured third-order intercept point (IIP3) (a) IIP3 =12dBm at 4GHz (b) IIP3= 5dBm at 10GHz

Table 3. 5 UWB LNA chip measured performance and comparison with post-layout simulation

Specification Unit Post-sim measure

Frequency GHz 3.1 ~ 10.6 3.3 ~ 8.1

Power (only core LNA) mW 4.7

--Power (total) mW 8.2 8.4

Supply Volatge (V_DD) V 0.9 0.9

Bias current (only core LNA) mA 5.23

--Bias current (total) mA 9.10 9.30

Gain(S₂₁)max / Gain(S₂₁)min dB 17.2 / 8.4 10.8 / 5.0

NF- min / max dB 2.8 / 6.5 3.9 / 4.1

Input Return Loss (S₁₁) dB < -8.3 < -6.7 Output Return Loss (S₂₂) dB < -10.3 < -5.8

IIP3 dBm -11@4GHz,-10@10GHz 12@4GHz,5@10GHz

Reverse isolation (S₁₂) dB < -46.1 < -27.3

Chip size mm² 0.637x0.892

Table 3. 6 UWB LNA Performance Benchmark

RF Corner Unit This work This work This work [43]

IIP3 dBm 12@4G,5@10G -11@4G,-10@10G -10@4G,-11@10G 7.25 @6G Reverse isolation (S12) dB < -27.3 < -46.1 < -43.6 --

Topology -- LC-filter based +

Topology -- Feedback Common Gate LC-filter based

Chapter 4 Sub-0.2mW Ultra-low Power LNA Design using Forward Body Biasing Technique

4.1 Introduction

In recent decade facing the stringent problems of energy sources draining and carbon emission induced global warming, clean energy and ultra-low power techniques have attracted an extensive research effort in all areas, such as materials, processes, devices, circuits, and systems. Ultra-low power wireless communication has been recognized as one of the most important domains, which match the right direction of clean energy and low emission. In the area of wireless communications, wireless sensor networks (WSN) emerges as a key component in a widely spread applications. Furthermore, the advent of WSN stimulates a strong demand for ultra-low power radio frequency integrated circuits (RFICs) to extend the battery life to reach the requirement of long time monitoring without replacement.

Therefore, it is important to substantially reduce DC power consumption of CMOS RFICs with all other key performances properly maintained.

Among the published low-power techniques in CMOS platform, subthreshold region operation becomes an attractive technique in advanced CMOS processes to nanoscale regime where sufficient transconductance (gm) can be achieved when using an optimized matching network. Theoretically, lowering the gate overdrive (VGS-VT) can improves the gm to drain current (IDS) ratio, i.e. gm/IDS. It is because that IDS has an exponential dependence on the gate-source voltage (VGS) in subthreshold region [44]. Adopting this comments for LNA design, its gain to power consumption ratio can be increased in subthreshold region as compared to that of strong inversion region. However, to meet the required gm, large input

transistors are usually needed. By increasing the width of the transistors operating in subthreshold region, the gain can be maintained sufficiently high, while DC power consumption is substantially reduced [45]. Furthermore, it is feasible to keep the minimum noise figure (NFmin) sufficiently low in subthreshold region for the nanoscale MOS transistors provided that gm is increased to sufficiently high by increasing the width [46]. As a result, the noise figure of the amplifier with CMOS transistors biased in subthreshold does not degrade drastically as DC power dissipation is reduced.

This chapter presents a fully monolithic micro-power LNA using subthreshold MOS devices with forward body biasing (FBB) technique and on-chip inductors at 1.4 GHz to lower the DC power dissipation. The LNA is fabricated in UMC 90nm Logic & Mixed-Mode 1P9M Low-K Process.

4.2 Circuit Architectures for ULP LNA

Fig.4.1 illustrates the circuit architecture for our proposed ultra-low power (ULP) LNA.

This ULP LNA is composed of an input matching network, an amplifying stage with cascode topology, and an output matching network. The cascode amplifier consists of an input transistor M1 and a cascade transistor M2.

Fig. 4. 1 Circuit architecture of the proposed ultra-low power (ULP) LNA

As it is well know that cascade amplifier has the advantages of higher gain and better isolation. However, the cascade structure consisting of two stacked transistors generally leads to the penalty of higher supply voltage and then higher power. To overcome the mentioned drawbacks, forward body biasing (FBB) technique is proposed to achieve low-voltage LNA design by reducing transistor’s threshold voltage (VT). According to the mentioned argument, the input transistor M1 (NMOS) in the cascade structure is biased in subthreshold region to realize superior gain per current and achieve low power performance. Besides, the gate width over length ratio (W/L) of the two transistors (M1 and M2) have to be increased and optimized to increase the gain of the amplifier and realize an input impedance matching to 50-Ω. A source degeneration inductor (LS) serves as another critical element to facilitate input matching to 50-Ω, and also enables good linearity and high reverse-isolation, which can facilitate amplifier stability. As for the output stage, an inductive load (Ld) as opposed to a resistive load, is preferred. An inductive load has the added benefit of boosting the gain by resonating with the capacitances associated with the output node. In this design, the output matching network is composed of Ld and Lo.

4.3 LNA Circuit Analysis

In this section, a small signal equivalent circuit analysis will be carried out for our proposed ULP LNA, with the circuit schematics illustrated in Fig. 4.2

VDD

VG2

Lg VB1

Ls M1 M2

VB2

RF_PAD

Rs Vin

Vout Vout＇

Fig. 4. 2 The circuit schematic of ULP LNA

4.3.1 Gain Analysis

As mentioned previously, a cascode topology with source inductive degeneration is used for improving the reverse isolation, frequency response, better noise figure and lower Miller effect. Input impedance matching by inductive source degeneration had been discussed previously in Chapter 2. In the following, circuit performance will be analyzed based on the small signal equivalent circuit for the proposed ULP LNA, shown in Fig.4.3. First, voltage gain is derived as follows.

Fig. 4. 3 Small signal equivalent circuit analysis for the ULP LNA

78 where the capacitance Cout may be taken to represent all the loading on the drain node of M2, Cgs is the gate-source capacitance of M1, RS is the impedance of the input signal source, and RO represent the output load impedance. The derived voltage gain in (4-1) indicates that the increase of parasitic resistances (RS, RO) and capacitances (Cgs, Cout) will degrade the gain available for the LNA, and the degradation becomes worse under higher frequencies.

4.3.2 Noise Analysis [4]

For LNA design, an appropriate selection of circuit topology at the first stage is critically important, not only for a good input matching but also for lower noise. Fig. 4.4(a) depicts a simple common source (CS) cascade structure, which has been adopted as a amplifying stage, i.e. the first stage in our proposed ULP LNA. An on-chip inductor LS is employed for inductive source degeneration. Fig. 4.4(b) shows a small signal equivalent circuit for noise model of the mentioned input stage in LNA.

(a)

(b)

Fig. 4. 4 (a) a simple cascade structure used as a common source input stage of LNA (b) a small signal equivalent circuit for the noise model of input stage in LNA

According to Fig. 4.4 (a), the input impedance of the cascade amplifier is represented by

The derived equation (4-2) indicates that the input impedance Zin becomes purely real and proportional to Ls when operating at the resonance frequency determined by the series LC (Lg, LS, and Cgs) at the input stage. By choosing Ls appropriately, this real term can be made equal to 50 Ω. In Fig. 4.4 (b), Rg represents the series resistance of the inductor as well as the gate resistance of the NMOS device (M1 in Fig.4.4(a)), and i represents the channel thermal _nd²

noise of M1, while the i_ngc² and i_ngu² are the gate noise from correlated and uncorrelated term. Here, analysis based on this equivalent circuit neglects the contribution of subsequent stages to the amplifier noise figure. This simplification is justifiable provided that the first stage possesses sufficient gain and allows us to examine in detail the salient features of this

architecture.

In order to find the output noise, we first evaluate the transconductance Gm of the input stage. With the output current proportional to the voltage on Cgs and nothing that the input circuit takes the form of series-resonant network, the transconductance at the resonant frequency is given by

0 0

From this equation, the output noise power density due to the source is

2 2

In a similar way, the output noise power density due to Rg can be expressed as

2 2

Next, the noise power density associated with the correlated portion of the gate noise and drain noise can be expressed as [4]

The last noise term is the contribution of the uncorrelated portion of the gate noise. This contributor has the following power spectral density

We observe that (4-6) and (4-7) can all proportional to the power spectral density of drain current noise, then the two equations can be combined as a simplified form:

According to (4-4), (4-5) and (4-8), the noise factor at the resonant frequency can be written by the following equation:

0 F Noise power output due to source only

R Q

(4-10)

To understand the implications of this new expression for the noise factor (F), we observe that χ given by (4-9) includes one term proportional to QL and another term proportional to QL2. It follows that the noise factor in (4-10) will contain terms which are proportional to QL as well as inversely proportional to QL. Therefore, a minimum F exits for a particular QL. Besides, we observe that gm is inversely proportional to F.

4.4 Chip Circuit Design and Simulation

UMC 90nm RF CMOS Spice Model was employed for this ULP LNA circuit simulation and design. This RF CMOS Spice Model includes passive elements, such as resistors,

inductors, capacitors, and RF MOSFETs as the major active devices. Also, on-chip circuit layout will be introduced.

4.4.1 Models for LNA Circuit Simulation

In RF circuits design, an accurate and scalable model is strongly demanded to assure circuit simulation accuracy and facilitate the success of circuit design. For active devices, the intrinsic MOSFET model suitable for logic circuit simulation is no longer valid for RF circuit design. Parasitic and coupling effects from interconnection, substrate, and pads should be considered and taken into the model. As for passive devices, such as inductors, capacitors, and resistors, substrate loss and conductor loss become important effects required for accurate modeling. In the following, RF device models will be introduced for active devices like MOSFETs and passive elements, such as spiral inductors and MiM capacitors.

4.4.2 ULP LNA Simulation Results

The whole circuit schematics for the proposed ULP LNA is illustrated in Fig. 4.5, in which three major blocks such as input matching network, cascade amplifying stage, and output matching network are included and the layout dimensions for active transistors and parasitic elements (R, L, C) are remarked for simulation. Note that all the components in this design, including spiral inductors and metal-insulator-metal (MIM) capacitors, are realized on a single chip. Fig. 4.6 depicts the chip layout of the proposed ULP LNA. The chip area including all of probing pads is 0.778×0.669 mm². This proposed ULP LNA is simulated with Agilent ADS simulator using UMC 90nm RFCMOS Spice Model. In the following, the simulation results will be presented, including pre-layout and post-layout under typical (TT) and corner conditions (FF, SS). For this ULP LNA design, the key performance parameters, such as power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S12), noise figure (NF), stability (μ), and third-order intercept point (IIP3) have been calculated by ADS simulation. Fig. 4.7 show the pre-layout simulation results, under the typical condition

of VDD=0.18V, VG=0.45V, VG2=0.8V, and frequencies in 0.8~2 GHz. Note that the third-order intercept point (IIP3) shown in Fig. 4.7(d) is determined by two-tone test with tone space of 10MHz, and fundamental frequency at 1.4GHz. Fig. 4.8 presents a comparison for all of the performance parameters, between pre-layout and post-layout simulation.

Table 4.1 and Table 4.2 summarizes the pre-layout and post-layout simulation for all of the performance parameters, with a comparison between typical (TT) and corner conditions (FF, SS). For mentioned simulation, the bias conditions are fixed at VDD=0.18V, VG=0.45V, VG2=0.8V, VB1=0.4V,.and VB2=0V. Note that VB1=0.4V is the forward body bias (FBB) applied to amplifier transistor M1, which enables VG scaling to 0.45V, approaching subthreshold region for ultra-low power operation. The results indicate that RF CMOS devices in 90 nm process, operating under the specified biases with FBB can achieve ultra-low power consumption to 0.19 mW for typical condition, and low NF of 2.1 dB. The performance looks very promising in both power and noise. As for the fast corner conditions (FF), the power dissipation is increased to 0.56 mW but NF can be improved to 1.8 dB. On the other hand, for slow corner condition (SS), the power consumption is pushed to extremely low to 0.05mW, but paying the penalty of significantly higher NF, up to 4.2 dB. The post-layout simulation indicates similar results with very minor difference from that of pre-layout simulation. The variations of the RF performance parameters between typical (TT) and corner models (FF, SS), under fixed biases condition can be eliminated by using tunable biases adapted to corner models. The principle of biases tuning is lowering VG and VG2 for fast corner (FF) while raising those for slow corner (SS). Tables 4.3 and table 4.4 present the pre-layout and post-layout simulation results, under tunable biases exactly adapted to FF and SS. In this way, the RF performance, particularly the power dissipation and NF of major concern, can be tuned to be similar for all three conditions (TT, FF, SS). The ultra-low power to sub-0.2 mW can be realized for TT and corner models.

Fig. 4. 5 Circuit schematic of the ULP LNA with three core circuit blocks in which the active and passive devices dimensions are provided

Fig. 4. 6 Chip layout of the designed ULP LNA

Fig. 4. 7 Pre-layout simulation for ULP LNA (a) power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S22) (b) noise figure (NF) (c) stability (d) third-order intercept point (IIP3), two tones space=10MHz, center frequency

=1.4GHz. VDD=0.18V, VG=0.45V, VG2=0.8V, VB1=0.4V, VB2=0.

Fig. 4. 8 Comparison between pre-layout and post-layout simulation results for the ULP LAN (a) power gain(S21) (b) input return loss (S11) (c)output return loss (S22) (d) reverse isolation (S21) (e) noise figure (NF) (f) stability (g) third-order intercept point (IIP3). VDD=0.18V, VG=0.45V, VG2=0.8V, VB1=0.4V, VB2=0.

Table 4. 1 Pre-layout simulation for ULP LNA under fixed biases condition for typical (TT) and corner cases (FF, SS). VDD=0.18V, VG=0.45V, VG2=0.8V. VB1=0.4V, and

Table 4. 2 Post-layout simulation for ULP LNA under fixed biases condition for typical (TT) and corner cases (FF, SS). VDD=0.18V, VG=0.45V, VG2=0.8V. VB1=0.4V, and VB2=0V.

RF CORNER UNIT TT FF SS

Process technology nm 90 90 90

Frequency GHz 1.4 1.4 1.4

VDD V 0.18 0.18 0.18 VG V 0.45 0.45 0.45 VG2 V 0.80 0.80 0.80 VB1 V 0.40 0.40 0.40 VB2 V 0 0 0

Power dissipation mW 0.19 0.54 0.05

Bias current mA 1.05 2.98 0.26

Gain (S21) dB 10.3 11.3 1.1

NF dB 2.3 1.9 4.3

IIP3 dBm -13.3 -17.5 -16.0

Pin,-1dB dBm -28.0 -30.0 -28.0

Input Return Loss (S11) dB -12.1 -14.9 -4.2

Output Return Loss (S22) dB -10.6 -5.6 -18.1

Reverse isolation (S12) dB -15.6 -18.5 -15.7

Table 4. 3 Pre-layout simulation for ULP LNA under tunable biases condition for typical (TT) and corner cases (FF, SS).

RF CORNER UNIT TT FF SS

Process technology nm 90 90 90

Frequency GHz 1.4 1.4 1.4

VDD V 0.18 0.18 0.18

VG V 0.45 0.38 0.52

VG2 V 0.80 0.74 0.85

VB1 V 0.40 0.40 0.40 VB2 V 0 0 0

Power dissipation mW 0.19 0.20 0.19

Bias current mA 1.06 1.09 1.03

Gain (S21) dB 11.0 10.9 11.0

NF dB 2.1 2.1 2.1

IIP3 dBm -14.1 -14.2 -14.3

Pin,-1dB dBm -29.0 -29.0 -29.0

Input Return Loss (S11) dB -10.4 -9.3 -11.0

Output Return Loss (S22) dB -10.5 -10.8 -11.2

Reverse isolation (S12) dB -15.2 -14.3 -16.1

Table 4. 4 Post-layout simulation for ULP LNA under tunable biases condition for typical (TT) and corner cases (FF, SS).

RF CORNER UNIT TT FF SS

Power dissipation mW 0.19 0.19 0.18

Bias current mA 1.05 1.07 1.01

For this ULP LNA design, the test chip characterization will be performed through on-wafer measurement. To meet this purpose, the probing pads layout must follow the rule issued by NDL RF Lab. to match the RF probe station configuration. This LNA chip needs two 3-pin DC PGP probes and two RF GSG probes for on-wafer measurement. The measurement setup is shown in Fig. 4.9, where two DC PGP probes are located at the top and bottom, and two RF GSG probes are place at two sides, in parallel to each other. Note that the DC PGP probe is used to provide the DC supply voltages to the drain and biasing voltage to the gate.

Fig. 4. 9 On-wafer measurement of LNA test diagram

The measurement equipments to support this LNA chip test include a network analyzer (Agilent PNA-X N5242A), a spectrum analyzer (Agilent E4448A) with options for NF measurement, and dc power supply (Agilent 6623A & Keithley Model 236 Source-Measure Unit). The measurement setups are shown in Fig.4.10(a) for S-parameter, IIP3, and 1-dB compression point (P1dB), and Fig.4.10(b) for noise figure. In the following, we will present the ULP LNA chip characterization results for the key performance parameters and a comparison with what predicted by post-layout simulation.

Agilent PNA-X N5242A Agilent E4448A

Agilent 6623A Keithley Model 236 Source-Measure Unit

(a) (b)

Fig. 4. 10 Measurement setups for (a) S-parameter & IIP3 & P1dB (b) noise figure

4.5.2 Measurement Results and Discussion

Fig. 4.11 presents the performance measured from this ULP LNA fabricated in 90nm 1.2V RF CMOS process. The results are demonstrated for power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S12), and noise figure (NF), shown in Fig.

4.11(a)~(c). As compared to post-layout simulation shown previously, the measured performance reveals a distinct difference from the prediction by simulation under ultra-low VDD (0.18V) and VG=0.45V to subthreshold region. The first problem is that the power gain (S21) measured from the real chips under the specified biases is abnormally low. It was considered that the on-chip inductors performance may deviate from the ideal values predicted by simulation, assuming thick top metal (3.25μm). Thus, on-wafer S-parameters measurement was carried to explore the root causes responsible for this unexpected degradation. Table 4.5 makes a comparison between the measured and simulated characteristics and reveals a close match in inductance but distinct deviation in series resistance RS=Re(1/Y11). The measured RS is around 3~5 times larger than the simulated values for larger inductors with L=10~22 nH. The deviation becomes even worse to more than one order for the smallest inductor with L=0.8~0.9 nH. Through this analysis, it is identified that extra-ordinarily high RS due to thin metal for the spiral conductors is the major

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