Dynamic Threshold Voltage CMOS - Basic Concepts of Low Noise Amplifier Design

Chapter 2 Basic Concepts of Low Noise Amplifier Design

2.7 Dynamic Threshold Voltage CMOS

i

^C

_gs

g V

m gs

r

i

_nd²

Fig. 2. 15 MOSFET noise model

2.7 Dynamic Threshold Voltage CMOS

The threshold voltage (Vth) of a MOSFET is expressed as

( )

0 2 2

th th f bs f

V =V +γ ϕ −V − ϕ (2-46) where V_th₀ is the threshold voltage when V_bs = , 0 γ is the body-effect coefficient, ϕ is _f the bulk Fermi potential. Note that V_bs is the voltage between body and source. Thus,

changing V_bs can modify V_th, which can achieve a dynamic threshold voltage MOSFET (DTMOS). Threshold voltage is decreased as the external bias Vbs is increased toward the forward direction for the substrate. Usually, the junction between body and source is zero-biased or reverse-biased. To further improve performance under continuously scaled supply voltage (VDD), forward body bias (FBB) method becomes attractive for reducing V_th, according to (2-46). Here, we introduce this concept into low voltage LNA design. To implement forward body bias scheme in NMOSFET, a deep N-well process is needed as shown in Fig.2.16, which can provide separate body region for each NMOS transistor and allow the freedom of body biases. In addition, a deep N-well process can reduce noise cross-talk through the substrate. In this thesis, FBB method has been extensively used in low-power UWB LNA and ultra-low power narrow band LNA design.

Fig. 2. 16 Cross-sectional view of the DTMOS device with deep N-well structure

Chapter 3 Low-Power UWB LNA Design using Forward Body Biasing Technique for 3.1~10.6 GHz Wireless Receivers

3.1 Introduction

Wideband systems have recently gained much attention due to their capability of high data rate transmission. The so called ultra-wide band (UWB) technology can pave the way for a wide range of applications, which use the frequency bands in 3.1 ~ 10.6 GHz and can co-exist with the already licensed spectrum users. To interface with the antenna and pre-select filter in a receiver system, the low-noise amplifier (LNA) input impedance should be close to 50-Ω across the band from 3.1 to 10.6 GHz.

There are several existing solutions for wideband amplifiers in CMOS technology. The distributed amplifier (DA) is widely used for wideband application due to its intrinsic broadband frequency response going all the way down to dc along with good input and output impedance matching. Yet, so far, high power consumption and large die area have hampered its widespread applications [32-34]. Recently, the RC feedback topology is widely used for wideband application. It can provide good wideband matching and flat gain but it can’t provide sufficient gain and lower noise figure with low power consumption [35, 36]. Another efficient way to achieve a broadband matching is the common-gate input topology [24].

However, the mentioned weaknesses in terms of gain, noise, and power consumption cannot be solved. For the UWB technology to be widely employed in the hand-held wireless applications, it cannot be avoided that power consumption is one of the main challenges. In this chapter, we present a UWB LNA with broadband impedance matching, low noise figure (NF), low power consumption, and small chip-area. We focus on the design and

implementation of UWB LNA with very low power consumption in a 0.13um CMOS technology.

3.2 Circuit Architectures

Fig. 3.1 illustrates the circuit architecture of our proposed UWB LNA which is composed of an input matching network, cascode topology, shunt peaking circuit and output buffer. For a circuit analysis, this UWB LNA can be divided into three blocks – input matching stage, amplifying stage and source-follower buffer stage.

Fig. 3. 1 Circuit architecture of the UWB LNA

In the following, the function of each element in the circuit architecture will be interpreted to explain the UWB LNA design concept. First for the input matching stage, a three-section Chebyshev filter was used, combining the gate-source capacitance (Cgs) of M1 and the source degeneration inductance Ls. This input matching circuit is aimed at a broadband matching from 3.1 to 10.6 GHz.

Secondly for the amplifying stage, a cascode topology with forward body biasing (FBB)

scheme was adopted to reduce the supply voltage and power consumption. The cascade structure can offer the advantages, such as less Miller effect, better reverse isolation, wider frequency response, and lower noise figure [28, 29]. FBB technique can facilitate low-voltage UWB LNA design by reducing transistor’s threshold voltage (VT). Shunt peaking method can improve the gain at low frequency and extend the usable bandwidth.

Finally for source-follower buffer stage, an output matching buffer composed of M1, L3, and C3 shown in Fig.3.1 was designed to achieve flat gain over the entire bandwidth and improve the gain at high frequency. Note that the dimensions of M3, L3 and C3 will determine the high-frequency characteristic of UWB LNA and an appropriate selection of the layout dimensions is indispensable to achieve a wideband output matching from 3.1 to 10.6 GHz.

3.3 Circuit Topology Analysis

3.3.1 Input Matching Circuit and Analysis [37-39]

Fig. 3.2 illustrates an input impedance matching circuit in the form of multi-section LC networks proposed for UWB LNA in this thesis. The implemented matching network is built and operates based on the LC resonance matching technique. In the following, the theory and circuit operation principle of this matching network will be described to detail.

RF Input

Fig. 3. 2 The circuit schematics of input matching network for UWB LNA

a. Series LC resonance method:

First, a series LC resonance network is depicted in Fig. 3.3 and the impedance corresponding to this LC network can be derived as shown in (3-1).

C L

Z_S

Fig. 3. 3 Series LC resonance circuit

1 1 inductive mode impedance at lower frequency ω₁ <ω₀and becomes a capacitive mode at higher frequencyω₂ >ω₀.

(a) (b)

Fig. 3. 4 (a) Load ZL (b) The impedance modes of load ZL under varying frequencies, drawn in the Z-Smith chart

Then, we can add a series LC resonance circuit to the load ZL, as shown in Fig. 3.5.

Z

C

L

Z_in

Fig. 3. 5 Add a series LC resonance circuit to the load ZL

The above analysis provide us a guideline to select suitable L and C to generate capacitive mode impedance (–jX2) at lower frequency and inductive mode impedance(jX1) at higher frequency. In the way, the created series LC network can offer the required impedances to just cancel out that of load ZL, i.e. the inductive mode jX1 at lower frequency and capacitive mode -jX2 at higher frequency. As a result, the equivalent impedance of the input Zin can approach the real axis, shown in Fig. 3.6.

Fig. 3. 6 Effect of adding a series LC resonance circuit to the load in the Z-Smith chart b. Parallel LC resonance method:

Fig. 3.7 illustrates a parallel LC resonance network. The admittance corresponding to this parallel LC network can be derived as shown in (3-2).

L C

Y_S

Fig. 3. 7 Parallel LC resonance circuit

Following what has been done for series LC network, set a load Z illustrated in Fig. 3.8 (a) _L and the impedance of Z under varying frequencies is shown in the Z-Smith chart in Fig. _L 3.8 (b). It shows that Z is a kind of capacitive mode impedance at lower frequency _L

1 0 frequencies, drawn in the Z-Smith chart

(a) (b)

Fig. 3. 9 (a) Load admittance YL (b) The admittance modes of load YL under varying frequencies, drawn in the Y-Smith chart

Then, we can add a parallel LC resonance circuit to the load YL, as shown in Fig. 3.10.

Y

L C

Y

_in

Fig. 3. 10 Add a parallel LC resonance circuit to the load

Again, the above analysis provide us a guideline to select suitable L and C to generate capacitive mode admittance (jB1) at lower frequency and inductive mode admittance (-jB2) at higher frequency. In the way, the created parallel LC network can offer the required admittance to just cancel out that of load YL, i.e. the capacitive mode jB1 at lower frequency and the inductive mode -jB2 at higher frequency. As a result, the equivalent admittance of the input Yin can approach the real axis, shown in Fig. 3.11.

Fig. 3. 11 Effect of adding a parallel LC resonance circuit to the load in the Y-Smith chart

Based on the analysis on both series and parallel LC resonance circuits, an input matching circucit containing three-section LC networks, as shown in Fig.12 was implemented for ultra-wide band impedance matching in UWB LNA design. The first section of LC network is composed of Lg and Cgs appearing at the gate of MOSFET (Ls for source degeneration). As shown in Fig.13 (b), adding the first section LC network makes the S11

going from the lower half plane through the real axis to the upper half plane, which means an impedance shift from capacitive mode to inductive mode. Following the first series LC

network (Lg and Cgs), a parallel LC network consisting of L2 and C2 is added as the second section and the resulted S11 movement is shown in Fig.13(c). Finally, the third section of LC network in form of series L1 and C1 drives S11 reaching the center of Smith-chart, i.e. the targeted standard impedance 50 Ω for matching over the wide bandwidth 3.1 ~ 10.6GHz.

L2 C2

C1 Cgs

(gm/Cgd)Ls Rs

Band pass filter (T-network) Be chosen to be equal to 50 Resonate over the whole band from 3.1 to 10.6 GHz

(b) S11 (c) S11

(d) S11 (a) S11

Fig. 3. 12 An input matching circuit with three-section LC networks for ultra-wide band input impedance matching

(a) (b)

(c) (d)

Fig. 3. 13 The input matching network effect on S11 (a) original nMOSFET without external LC network (b) adding the first section of LC network : Lg and Cgs (c) adding the second

section of LC network : L2 and C2 (d) adding the third section of LC network :L1 and C1

3.3.2 Shunt Peaking Circuit and Analysis

Ld Iin Cout

Cout Ld

V_in

Vout

V_out

(a) (b) Fig. 3. 14 (a) Inductive-peaking configuration (b) Small-signal equivalent circuit

A model of shunt peaking amplifier is shown in Fig. 3.14. The capacitance Cout may be taken to represent all the loading on the output node, including that of a subsequent stage. The resistance Rd is the effective load resistance at that node and the inductor Ld is employed to extend the usable bandwidth. From Fig. 3.14, the transfer function H(s) without Ld is expressed in (3-3) and that with Ld is written in (3-4). As shown in (3-4), the addition of an inductor Ld in series with the load resistor Rd provides an impedance component that increases with frequency, which helps offset the decreasing impedance of the capacitance, leaving net impedance that remains roughly constant over a broader frequency range than that of the original RC network. This technique, so called as shunt peaking method is suitable for broadband design. Note that Ld must be optimized in the dimensions to have large gain, and to be sufficiently small so that it can keep the resonance from LdCout out of the working band. Rd is chosen to place the zero-node frequency (ωz=Rd/Ld) as close as to the lower edge of the bandwidth to improve the power gain. Fig. 3.15 demonstrates the shunt output inductance Ld effect on the ULW LNA performance, such as power gain (S21), noise figure (NF), input return loss (S11), output return loss (S22), calculated by ADS simulation. Note that the adoption of Ld, constituting the shunt peaking circuit can effectively improve the UWB performance with higher S21 and lower NF.

Fig. 3. 15 The output inductance Ld effect on UWB LNA performance from ADS simulation for power gain (S21), noise figure (NF), input return loss (S11), output return loss (S22).

3.3.3 Output Matching Circuit and Analysis

For an amplifier design, output matching circuit is indispensable to drive an external load, which is generally a low impedance. Source-follower buffer illustrated in Fig. 3.16 has been widely used as a typical output matching circuit for the purpose of ensuring sufficient power gain, even with an external load of low impedance.

(1/gm3)//ro3 L3

(a) (b)

Fig. 3. 16 The output matching circuit for UWB LNA (a) the circuit schematic of a Source-follower buffer (b) the Small-signal equivalent circuit for the source-follower

In the following, an equivalent circuit analysis based on Fig. 3.16(b) was performed to derive and compare the output characteristics like the external and internal output voltages.

The external output voltage Vout’ is related to the output voltage of the amplifier by

K low frequency voltage gain

V sL r

(3-7)

In this work for UWB LNA implementation, the source-follower buffer is designed to improve the power gain of the amplifier at high frequency and over wide bandwidth. In order to achieve wideband output matching from 3.1 to 10.6 GHz, we made an appropriate selection on the transistor M3 dimension (width) and biasing current to achieve (1/gm)//ro3= 50 Ω.

Furthermore, L3 and C3 were designed with a careful consideration of layout and dimensions

to enable an LC resonance at required high frequency. Note that the inductance L3, acts as a current source biasing the source-follower buffer, and also as a matching element for achieving high gain at the upper bound of bandwidth.

3.3.4 Forward Body Biasing Technique

The cascade topology has been widely used in amplifier design like LNA; however, the structure employing stacked transistors generally requires higher supply voltage (VDD). For the stacked transistors M1 and M2 under zero body bias (VBS=0V), the simulated output characteristics IDS –VDS shown in Fig. 3.17(a) indicates that voltage swing of 0.8V is required to make M2 operate in saturation, reaching the specified current, IDS =5mA. As for the same structure operating with forward body bias (FBB), e.g. VBS=0.4V applied to both M1 and M2, the IDS –VDS characteristics shown in Fig. 3.17(b) reveals that the required voltage swing can be reduced by 0.1V to 0.7V for the specified current in saturation region. This simulation predicts that FBB can facilitate VDD scaling, attributed to lower threshold voltage (Vth).

(a)

VDD

VGS

(W4N15)

(W4N60)

0.4V

(b)

Fig. 3. 17 Simulated IDS –VDS characteristics for stacked transistors structure (M1 and M2), under (a) zero body bias (VBS=0V) (b) forward body bias (VBS=0.4V).

In the following, the FBB effect on the proposed UWB LNA performance was verified by ADS circuit simulation. Referring to circuit schematics of our UWB LNA in Fig.3.1, ZBB at VBS=0V or FBB at VBS=0.4V were simultaneously applied to the body node of M1 and M2 for this evaluation. First, the supply voltages to the drain and gate, such as VDD=0.9V and VG=0.4V were fixed the same for different body biases like ZBB and FBB. The simulation results shown in Fig. 3.18(a) indicate that FBB (VBS=0.4V) can improve LNA performance in terms of higher power gain (S21), lower noise (NF), and lower return loss in both input and output (S11, S22). Then, the supply voltages were increased for ZBB to verify VDD and VG

required to reach the performance achieved under FBB. The simulation results shown in Fig.

3.18(b) suggest that VDD increased by 0.1V to 1.0V and VG raised by 0.09V to 0.49V can make the performance comparable with that under FBB. The results manifest the fact that FBB technique can facilitate lower power design, attributed to lower supply voltages as required. The Table 3.1 summarizes the performance under FBB and ZBB for a comparison.

Note that FBB can help reduce the supply voltage VDD from 1.0V (for ZBB) to 0.9V and reduce DC power consumption by 2.8 mW, from 11.1 mW (for ZBB) to 8.3 mW, that is around 34% power saving for keeping all other performance parameters the same.

Fig. 3. 18 UWB LNA performance : power gain (S21), lower noise (NF), input return loss (S11), and output return loss (S22) from ADS simulation (a) VDD=0.9V, VG=0.4V fixed for ZBB (VBS=0) and FBB (VBS=0.4) (b) VDD=0.9V, VG=0.4V FBB (VBS=0.4), VDD=1.0V, VG=0.45V for ZBB (VBS=0).

Table 3. 1 UWB LNA performance and supply voltages VDD comparison from ADS simulation, under zero body bias (ZBB) and forward body bias (FBB)

RF Corner Unit TT_forward body TT_zero body

Frequency GHz 3.1 ~ 10.6 3.1 ~ 10.6

Power (only core LNA) mW 4.7 6.9

Power (total) mW 8.3 11.1

Supply Volatge (V_DD) V 0.9 1.0

Bias current (only core LNA) mA 5.23 6.85

Bias current (total) mA 9.18 11.10

Gain(S₂₁)max / Gain(S₂₁)min dB 17.3/11.2 17.5/11.4

NF - min / max dB 2.7/4.1 2.7/4.1

Input Return Loss (S₁₁) dB < -8.6 < -8.6

Output Return Loss (S₂₂) dB < -10.1 < -10.1

IIP3 dBm -10@4G,-11@10G -9.75@4G,-11.36@10G

Reverse isolation (S₁₂) dB < -43.6 < -42.5

Chip size mm² 0.637 x 0.892 0.637 x 0.892

FOM(Figure of Merit) W^-1 53.7 40.7

FOM/Size (W^-1)/(mm²) 94.4 71.6

3.3.5 Gain Analysis

In the following, a complete circuit schematic incorporating input matching, amplifying stage, and output buffer, for the UWB LNA is illustrated in Fig. 3.19.

Fig. 3. 19 A complete circuit schematic of the UWB LNA

At high frequency, the MOS transistor acts as a current amplifier. The current gain is

45 ( )s g_m/sC_gs

β = , and the current into M1 is V W s_in⋅ ( ) /R_s, where W(s) is the Chebyshev filter transfer function. Note that |W(s)| in band is approximately unity and that out of band tends to be zero. The impedance looking into the amplifier is therefore equal to Rs when operating in band, and it becomes very high when working out of band. Therefore, the voltage gain can be derived as drain-gate capacitance of M2 and C_gs₃ is the gate-source capacitance of M3.

3.3.6 Noise Analysis [5]

The noise performance of the proposed topology is determined by two main contributors [5], such as the losses of the input network and the noise of M1 in the cascade amplifier. The noise introduced from the input network is due to the limited quality factor (Q) of the inductors integrated on bulk Si chip. To overcome this penalty, extensive research works have been carried out to improve Q of on-Si-chip inductor. The higher Q realized in an inductor can help reduce the noise but may trade off with wideband performance. Regarding the thermal

noise contributed from the transistor M1, layout optimization is generally done using multi-finger structure. For a fixed total width (Wtot), the smaller unit finger width (WF) and larger finger number (N) can help reduce gate resistance Rg and then suppress thermal noise, i.e. the lower NF. Again, a trade-off between the power and noise has to be considered in determining transistor dimension. The larger Wtot (WF*N) can reduce noise resistance Rn, attributed to larger gm; however, the associated higher current leads to higher power consumption. Fig. 3.20(a) presents a conventionally used thermal noise model for MOSFET, in which drain current noise ( S_id =i_nd²/Δf ) and induced gate noise ( S_ig =i_ng²/Δf ) are two primary noise sources. Fig.3.20(b) indicates an equivalent model for input referred noise generator with two correlated noise sources.

Fig. 3. 20 Noise model for the amplifying transistor M1. (a) noise sources from drain and gate (b) Input-referred equivalent noise generators.

In the following, noise model equations are derived for MOSFETs based on Fig. 3.20 [5]

= + ω ^gs

The power spectral density of drain current noise and induced gate noise are expressed in (3-14) and (3-15), respectively

By using the introduced parameters, the noise factor F can be expressed by

( ) (

)

According to noise optimization theory [3, 29], the minimum noise figure (NFmin) is achieved if the source impedance Z_s = Z_opt =R_opt + jX_opt is chosen such that (3-16) and (3-27) show that the optimum source impedanceX_opt is roughly the one that

resonates the series combination of C_gs and L . As a consequence, nearly minimum NF can _s be achieved over the entire bandwidth by using the proposed input matching network, which produces X_optover the required wide bandwidth. As a result of the foregoing discussion, the noise factor (F) of the LNA is

where

2 2 2

2 2 2 2 2

2 2

(1 )

( ) ( 2 1)

( 2 1)

ω α χ ω α χ αχ

α χ αχ

= − + + +

+ + ^gs ^s

p c C R c

c (3-29)

(3-28) and (3-29) show that increasing the transconductance g or reducing C_m gs can improve the noise performance, with all of the other parameters being the same.

The noise factor (F) described by (3-28) depends on three of the following four quantities: the drain current I , the over-drive voltage _D V , the transistor width W, and the _od frequency. In order to perform an optimization over the entire band of interest, we consider the average noise figure (NF). Thus, we reduce the number of independent variables by one.

Fig. 3.21 shows the contour plots of the average NF as a function of I and W. For each _D value of the bias current, the device width can be chosen to minimize the NF.

Fig. 3. 21 Contour plots of the average NF [5]

In order to minimize the average NF, the larger drain current I has the better NF _D performance, but it consumes more power. Therefore, under a specified power consumption, decreasing the supply voltage and increasing the current can improve NF performance.

Therefore, the supply voltage in this design is set a low voltage of 0.9V. In particular, for

ID mA , the best noise performance is achieved in the region 200μm W< <400μm. Note that Fig. 3.21 only refer to the noise contribution of M1. In a real circuit like LNA, additional noise besides that of transistors may come from the following sources.

1. the losses of the input network, i.e., the limited quality factor of the integrated inductors;

2. the cascode device (M2) noise contribution, particularly significant at higher frequencies;

3. the load resistance (Rd) noise contribution;

4. the output buffer (M3) noise contribution.

Due to the mentioned fact, the measured NF is generally worse than what is calculated for the MOSFETs themselves.

3.4 Chip Circuit Design and Simulation

TSMC 0.13μm 1.2V RF CMOS process [41] was employed for this UWB LNA circuit simulation and design. This RF SPICE model includes passive elements such as resistors, inductors, capacitors, and RF MOSFETs as the major active devices. Also, on-chip circuit

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