Output Matching Circuit and Analysis

For an amplifier design, output matching circuit is indispensable to drive an external load, which is generally a low impedance. Source-follower buffer illustrated in Fig. 3.16 has been widely used as a typical output matching circuit for the purpose of ensuring sufficient power gain, even with an external load of low impedance.

40

(1/gm3)//ro3 L3

C3

(a) (b)

Fig. 3. 16 The output matching circuit for UWB LNA (a) the circuit schematic of a Source-follower buffer (b) the Small-signal equivalent circuit for the source-follower

In the following, an equivalent circuit analysis based on Fig. 3.16(b) was performed to derive and compare the output characteristics like the external and internal output voltages.

The external output voltage Vout’ is related to the output voltage of the amplifier by

3

K low frequency voltage gain

V sL r

g

(3-7)

In this work for UWB LNA implementation, the source-follower buffer is designed to improve the power gain of the amplifier at high frequency and over wide bandwidth. In order to achieve wideband output matching from 3.1 to 10.6 GHz, we made an appropriate selection on the transistor M3 dimension (width) and biasing current to achieve (1/gm)//ro3= 50 Ω.

Furthermore, L3 and C3 were designed with a careful consideration of layout and dimensions

41

to enable an LC resonance at required high frequency. Note that the inductance L3, acts as a current source biasing the source-follower buffer, and also as a matching element for achieving high gain at the upper bound of bandwidth.

3.3.4 Forward Body Biasing Technique

The cascade topology has been widely used in amplifier design like LNA; however, the structure employing stacked transistors generally requires higher supply voltage (VDD). For the stacked transistors M1 and M2 under zero body bias (VBS=0V), the simulated output characteristics IDS –VDS shown in Fig. 3.17(a) indicates that voltage swing of 0.8V is required to make M2 operate in saturation, reaching the specified current, IDS =5mA. As for the same structure operating with forward body bias (FBB), e.g. VBS=0.4V applied to both M1 and M2, the IDS –VDS characteristics shown in Fig. 3.17(b) reveals that the required voltage swing can be reduced by 0.1V to 0.7V for the specified current in saturation region. This simulation predicts that FBB can facilitate VDD scaling, attributed to lower threshold voltage (Vth).

(a)

42

VDD

VGS

M2

M1

(W4N15)

(W4N60)

0.4V

(b)

Fig. 3. 17 Simulated IDS –VDS characteristics for stacked transistors structure (M1 and M2), under (a) zero body bias (VBS=0V) (b) forward body bias (VBS=0.4V).

In the following, the FBB effect on the proposed UWB LNA performance was verified by ADS circuit simulation. Referring to circuit schematics of our UWB LNA in Fig.3.1, ZBB at VBS=0V or FBB at VBS=0.4V were simultaneously applied to the body node of M1 and M2 for this evaluation. First, the supply voltages to the drain and gate, such as VDD=0.9V and VG=0.4V were fixed the same for different body biases like ZBB and FBB. The simulation results shown in Fig. 3.18(a) indicate that FBB (VBS=0.4V) can improve LNA performance in terms of higher power gain (S21), lower noise (NF), and lower return loss in both input and output (S11, S22). Then, the supply voltages were increased for ZBB to verify VDD and VG

required to reach the performance achieved under FBB. The simulation results shown in Fig.

3.18(b) suggest that VDD increased by 0.1V to 1.0V and VG raised by 0.09V to 0.49V can make the performance comparable with that under FBB. The results manifest the fact that FBB technique can facilitate lower power design, attributed to lower supply voltages as required. The Table 3.1 summarizes the performance under FBB and ZBB for a comparison.

Note that FBB can help reduce the supply voltage VDD from 1.0V (for ZBB) to 0.9V and reduce DC power consumption by 2.8 mW, from 11.1 mW (for ZBB) to 8.3 mW, that is around 34% power saving for keeping all other performance parameters the same.

43

Fig. 3. 18 UWB LNA performance : power gain (S21), lower noise (NF), input return loss (S11), and output return loss (S22) from ADS simulation (a) VDD=0.9V, VG=0.4V fixed for ZBB (VBS=0) and FBB (VBS=0.4) (b) VDD=0.9V, VG=0.4V FBB (VBS=0.4), VDD=1.0V, VG=0.45V for ZBB (VBS=0).

44

Table 3. 1 UWB LNA performance and supply voltages VDD comparison from ADS simulation, under zero body bias (ZBB) and forward body bias (FBB)

RF Corner Unit TT_forward body TT_zero body

Frequency GHz 3.1 ~ 10.6 3.1 ~ 10.6

Power (only core LNA) mW 4.7 6.9

Power (total) mW 8.3 11.1

Supply Volatge (V_DD) V 0.9 1.0

Bias current (only core LNA) mA 5.23 6.85

Bias current (total) mA 9.18 11.10

Gain(S₂₁)max / Gain(S₂₁)min dB 17.3/11.2 17.5/11.4

NF - min / max dB 2.7/4.1 2.7/4.1

Input Return Loss (S₁₁) dB < -8.6 < -8.6

Output Return Loss (S₂₂) dB < -10.1 < -10.1

IIP3 dBm -10@4G,-11@10G -9.75@4G,-11.36@10G

Reverse isolation (S₁₂) dB < -43.6 < -42.5

Chip size mm² 0.637 x 0.892 0.637 x 0.892

FOM(Figure of Merit) W^-1 53.7 40.7

FOM/Size (W^-1)/(mm²) 94.4 71.6

3.3.5 Gain Analysis

In the following, a complete circuit schematic incorporating input matching, amplifying stage, and output buffer, for the UWB LNA is illustrated in Fig. 3.19.

Fig. 3. 19 A complete circuit schematic of the UWB LNA

At high frequency, the MOS transistor acts as a current amplifier. The current gain is

45 ( )s g_m/sC_gs

β = , and the current into M1 is V W s_in⋅ ( ) /R_s, where W(s) is the Chebyshev filter transfer function. Note that |W(s)| in band is approximately unity and that out of band tends to be zero. The impedance looking into the amplifier is therefore equal to Rs when operating in band, and it becomes very high when working out of band. Therefore, the voltage gain can be derived as drain-gate capacitance of M2 and C_gs3 is the gate-source capacitance of M3.

3.3.6 Noise Analysis [5]

The noise performance of the proposed topology is determined by two main contributors [5], such as the losses of the input network and the noise of M1 in the cascade amplifier. The noise introduced from the input network is due to the limited quality factor (Q) of the inductors integrated on bulk Si chip. To overcome this penalty, extensive research works have been carried out to improve Q of on-Si-chip inductor. The higher Q realized in an inductor can help reduce the noise but may trade off with wideband performance. Regarding the thermal

46

noise contributed from the transistor M1, layout optimization is generally done using multi-finger structure. For a fixed total width (Wtot), the smaller unit finger width (WF) and larger finger number (N) can help reduce gate resistance Rg and then suppress thermal noise, i.e. the lower NF. Again, a trade-off between the power and noise has to be considered in determining transistor dimension. The larger Wtot (WF*N) can reduce noise resistance Rn, attributed to larger gm; however, the associated higher current leads to higher power consumption. Fig. 3.20(a) presents a conventionally used thermal noise model for MOSFET, in which drain current noise ( S_id =i_nd²/Δf ) and induced gate noise ( S_ig =i_ng²/Δf ) are two primary noise sources. Fig.3.20(b) indicates an equivalent model for input referred noise generator with two correlated noise sources.

2

Fig. 3. 20 Noise model for the amplifying transistor M1. (a) noise sources from drain and gate (b) Input-referred equivalent noise generators.

In the following, noise model equations are derived for MOSFETs based on Fig. 3.20 [5]

= + ω ^gs

47

The power spectral density of drain current noise and induced gate noise are expressed in (3-14) and (3-15), respectively

2

48

By using the introduced parameters, the noise factor F can be expressed by

( ) (

²

)

²

According to noise optimization theory [3, 29], the minimum noise figure (NFmin) is achieved if the source impedance Z_s = Z_opt =R_opt + jX_opt is chosen such that (3-16) and (3-27) show that the optimum source impedanceX_opt is roughly the one that

resonates the series combination of C_gs and L . As a consequence, nearly minimum NF can _s be achieved over the entire bandwidth by using the proposed input matching network, which produces X_optover the required wide bandwidth. As a result of the foregoing discussion, the noise factor (F) of the LNA is

49

where

2 2 2

2 2 2 2 2

2 2

(1 )

( ) ( 2 1)

( 2 1)

ω α χ ω α χ αχ

α χ αχ

= − + + +

+ + ^{gs s}

p c C R c

c (3-29)

(3-28) and (3-29) show that increasing the transconductance g or reducing C_m gs can improve the noise performance, with all of the other parameters being the same.

The noise factor (F) described by (3-28) depends on three of the following four quantities: the drain current I , the over-drive voltage _D V , the transistor width W, and the _od frequency. In order to perform an optimization over the entire band of interest, we consider the average noise figure (NF). Thus, we reduce the number of independent variables by one.

Fig. 3.21 shows the contour plots of the average NF as a function of I and W. For each _D value of the bias current, the device width can be chosen to minimize the NF.

Fig. 3. 21 Contour plots of the average NF [5]

In order to minimize the average NF, the larger drain current I has the better NF _D performance, but it consumes more power. Therefore, under a specified power consumption, decreasing the supply voltage and increasing the current can improve NF performance.

50

Therefore, the supply voltage in this design is set a low voltage of 0.9V. In particular, for

=5

ID mA , the best noise performance is achieved in the region 200μm W< <400μm. Note that Fig. 3.21 only refer to the noise contribution of M1. In a real circuit like LNA, additional noise besides that of transistors may come from the following sources.

1. the losses of the input network, i.e., the limited quality factor of the integrated inductors;

2. the cascode device (M2) noise contribution, particularly significant at higher frequencies;

3. the load resistance (Rd) noise contribution;

4. the output buffer (M3) noise contribution.

Due to the mentioned fact, the measured NF is generally worse than what is calculated for the MOSFETs themselves.

3.4 Chip Circuit Design and Simulation

TSMC 0.13μm 1.2V RF CMOS process [41] was employed for this UWB LNA circuit simulation and design. This RF SPICE model includes passive elements such as resistors, inductors, capacitors, and RF MOSFETs as the major active devices. Also, on-chip circuit layout will be introduced.

3.4.1 Model for Circuit Simulation

In mixed signal and RF circuit design, an accurate and scalable model is strongly demanded to assure circuit simulation accuracy and facilitate the success of circuit design. For active devices, the intrinsic MOSFET model suitable for logic circuit simulation is no longer valid for RF circuit design. Parasitic and coupling effects from interconnection, substrate, and pads should be considered and taken into the model. As for passive devices, such as inductors, capacitors, and resistors, substrate lossy and conductor loss become important effects required for accurate modeling.

51

3.4.2 RF Circuit Simulation for UWB LNA Design

The whole circuit schematics for the proposed UWB LNA is illustrated in Fig. 3.22 in which three major blocks such as input matching network, amplifying stage (cascode), and output buffer are included and the layout dimensions for active transistors and parasitic elements (R, L, C) are remarked for simulation. Note that all the components in this design, including spiral inductors, metal-insulator-metal (MIM) capacitors and resistors, are realized on chip. Fig. 3.23 depicts the chip layout of the proposed UWB LNA. The chip area occupied by the core circuits of LNA and probing pads in peripheral region is 0.637x0.892 mm². The details of circuit topology analysis and operation principles have been introduced in sections 3.2~3.3. The proposed UWB LNA is simulated with Agilent ADS simulator using TSMC 0.13μm mixed-signal 1.2/2.5V RF CMOS Model. In the following, the simulation results will be presented, including pre-layout and post-layout under typical (TT) and corner conditions (FF, SS). For this UWB LNA design, the key performance parameters, such as power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S12), noise figure (NF), stability, and third-order intercept point (IIP3) have been calculated by ADS simulation. Fig.

3.24 ~ 28 show pre-layout simulation results, under the typical condition of VDD=0.9V, VG=0.4V, and a wide range of frequencies in 2~11 GHz. Note that the third-order intercept point (IIP3) shown in Fig. 3.28 is determined by two-tone test with tone space of 10MHz, and fundamental frequency at 4GHz and 10GHz. Fig. 3.29 ~ 33 indicate the pre-layout simulation for mentioned performance parameters, with a comparison under typical (TT) and corner conditions (FF, SS). The comparison is summarized in Table 3.2. As for the differences from post-layout, Fig. 3.34 ~ 38 present a comparison for all of the performance parameters, between pre-layout and post-layout simulation. Fig. 3.39 shows the Post-simulated stability.

Fig. 3.40 shows the Post-simulated IIP3 at 4 GHz and 10 GHz. Table 3.3 shows the post-simulation results summary of typical and corner case. The performance of the proposed

52

UWB LNA is summarized in Table 3.4.

RF Input

RF Output VDD

Vbias RF_PAD

RF_PAD M2

DC_PAD

DC_PAD

C4

C5

(1.4p)

(1.4p)

(0.4V)

(0.9V)

mimcapC1

lt=27um wt=25um C=711fF

M1

M3

Fig. 3. 22 Circuit schematic of the UWB LNA with three core circuit blocks in which the active and passive devices dimensions are provided

Fig. 3. 23 Chip layout of the UWB LNA

53

Fig. 3. 25 Pre-layout simulation for reverse isolation (S12) VDD=0.9V, VG=0.4V, frequency=2~11 GHz.

54

2 3 4 5 6 7 8 9 10 11

0 2 4 6 8 10

Pre-sim

NF ( d B)

Frequency (GHz)

Fig. 3. 26 Pre-layout simulation for noise figure (NF). VDD=0.9V, VG=0.4V, frequency=2~11 GHz.

2 3 4 5 6 7 8 9 10 11

0 1 2 3 4 5 6 7 8 9 10

μ ( S tabi lit y )

Pre-sim

Frequency (GHz)

Fig. 3. 27 Pre-layout simulation for stability. VDD=0.9V, VG=0.4V, frequency=2~11 GHz.

55

Fig. 3. 28 Pre-layout simulation for third-order intercept point (IIP3) (a) 4GHz : IIP3 =-10dBm (b) 10GHz IIP3=-11dBm. Two-tone test with tone spacing of 1MHz.

VDD=0.9V, VG=0.4V.

56

Fig. 3. 29 Pre-layout simulation for power gain (S21), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz.

Fig. 3. 30 Pre-layout simulation for input return loss (S11), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz

57

Fig. 3. 31 Pre-layout simulation for output return loss (S22), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz

Fig. 3. 32 Pre-layout simulation for reverse isolation (S12), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz

58

Fig. 3. 33 Pre-layout simulation for noise figure (NF), under typical (TT) and corner conditions (FF, SS). TT : VDD=0.9V, VG=0.4V, frequency=2~11 GHz.

Table 3. 2 Pre-layout simulation results, under typical and corner conditions

Pre-layout simulation

RF Corner Unit TT FF SS

Frequency GHz 3.1 ~ 10.6 3.1 ~ 10.6 3.1 ~ 10.6

Power (only core LNA) mW 4.7 7.9 2.5

Power (total) mW 8.3 11.1 6.6

Supply Volatge (V_DD) V 0.9 0.9 0.9

Bias current (only core LNA) mA 5.23 8.75 2.80

Bias current (total) mA 9.18 12.30 7.36

Gain(S₂₁)max / Gain(S₂₁)min dB 17.3 / 11.2 16.3 / 9.6 16.5 / 10.2

NF - min / max dB 2.7 / 4.1 2.4 / 4.0 3.3 / 5.1

Input Return Loss (S₁₁) dB < -8.6 < -8.5 < -7.6 Output Return Loss (S₂₂) dB < -10.1 < -9.4 < -10.8

IIP3 dBm -10@4GHz,-11@10GHz -11@4GHz,-11@10GHz -7@4GHz,-6@10GHz

Reverse isolation (S₁₂) dB < -43.6 < -41.1 < -45.8

59

0 2 4 6 8 10 12

-10 -5 0 5 10 15 20

S2 1 ( dB)

Frequency (GHz)

Pre-sim Post-sim

Fig. 3. 34 Comparison between pre-layout and post-layout simulation results for the power gain(S21). VDD=0.9V, VG=0.4V, frequency=2~11 GHz.

0 2 4 6 8 10 12

-25 -20 -15 -10 -5 0

Frequency (GHz)

Pre-sim Post-sim

S11 (d B)

Fig. 3. 35 Comparison between pre-layout and post-layout simulation results for the input return loss (S11). VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.

60

0 2 4 6 8 10 12

-30 -25 -20 -15 -10 -5 0

S22 ( d B )

Frequency (GHz)

Pre-sim Post-sim

Fig. 3. 36 Comparison between pre-layout and post-layout simulation results for the output return loss (S22). VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.

0 2 4 6 8 10 12

-100 -90 -80 -70 -60 -50 -40

Pre-sim Post-sim

S1 2 ( d B)

Frequency (GHz)

Fig. 3. 37 Comparison between pre-layout and post-layout simulation results for the reverse isolation (S12). VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.

61

Fig. 3. 38 Comparison between pre-layout and post-layout simulation results for noise figure (NF). VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.

Fig. 3. 39 Comparison between pre-layout and post-layout simulation results for stability.

VDD=0.9V, VG=0.4V, frequency=0.5~12 GHz.

62

Fig. 3. 40 Post-layout simulation for third-order intercept point (IIP3) (a) 4GHz : IIP3 = -11dBm (b) 10GHz IIP3= -10dBm. Two-tone test with tone spacing of 1MHz.

VDD=0.9V, VG=0.4V.

63

Table 3. 3 Post-layout simulation results, under typical and corner conditions

Post-layout simulation

RF Corner Unit TT FF SS

Frequency GHz 3.1 ~ 10.6 3.1 ~ 10.6 3.1 ~ 10.6

Power (only core LNA) mW 4.7 7.9 2.5

Power (total) mW 8.2 11.0 6.6

Supply Volatge (V_DD) V 0.9 0.9 0.9

Bias current (only core LNA) mA 5.23 8.74 2.80

Bias current (total) mA 9.10 12.20 7.31

Gain(S₂₁)max / Gain(S₂₁)min dB 17.2 / 8.4 16.1 / 8.0 16.2 / 5.7

NF - min / max dB 2.8 / 6.5 2.5 / 5.0 3.4 / 8.8

Input Return Loss (S₁₁) dB < -8.3 < -8.2 < -7.5 Output Return Loss (S₂₂) dB < -10.3 < -9.7 < -10.9

IIP3 dBm -11@4GHz,-10@10GHz -12@4GHz,-11@10GHz -7@4GHz,-4@10GHz

Reverse isolation (S₁₂) dB < -46.1 < -43.7 < -47.4

Table 3. 4 Comparison of pre-layout and post-layout simulation results (typical condition)

Specification Unit Pre-sim Post-sim

Frequency GHz

Power (only core LNA) mW 4.7 4.7

Power (total) mW 8.3 8.2

Supply Volatge (V_DD) V 0.9 0.9

Bias current (only core LNA) mA 5.23 5.23

Bias current (total) mA 9.18 9.10

Gain(S₂₁)max / Gain(S₂₁)min dB 17.3 / 11.2 17.2 / 8.4

NF - min / max dB 2.7 / 4.1 2.8 / 6.5

Input Return Loss (S₁₁) dB < -8.6 < -8.3 Output Return Loss (S₂₂) dB < -10.1 < -10.3

IIP3 dBm -10@4GHz,-11@10GHz -11@4GHz,-10@10GHz

Reverse isolation (S₁₂) dB < -43.6 < -46.1

Chip size mm²

3.1 ~ 10.6

0.637x0.892

64

3.5 Measurement

3.5.1 Measurement Considerations

For this UWB LNA design, the test chip characterization will be performed through on-wafer measurement. To meet this purpose, the probing pads layout must follow the rule issued by NDL RF Lab. to match the RF probe station configuration. This LNA chip needs one 3-pin DC PGP probe and two RF GSG probes for on-wafer measurement. The measurement setup is shown in Fig. 3.41, where one DC PGP probe is located at the top and two RF GSG probes are place at two sides, in parallel to each other. Note that the DC PGP probe is used to provide the DC supply voltages to the drain and biasing voltage to the gate.

Fig. 3. 41 On-wafer measurement setup for UWB LNA chip test and characterization

The measurement equipments to support this LNA chip test include a network analyzer (Agilent PNA-X N5242A), a spectrum analyzer (Agilent E4448A) with options for NF measurement, and dc power supply (Agilent 6623A & Keithley Model 236 Source-Measure Unit). The measurement setups are shown in Fig.3.42(a) for S-parameter, IIP3, and 1-dB compression point (P1dB), and Fig.3.42(b) for noise figure. In the following, we will present

65

the LNA chip characterization results for all of the key performance parameters and a comparison with what predicted by post-layout simulation.

Agilent PNA-X N5242A Agilent E4448A

Agilent 6623A Keithley Model 236 Source-Measure Unit

(a) (b)

Fig. 3. 42 Measurement setups for (a) S-parameter & IIP3 & P1dB (b) noise figure

66

3.5.2 Measurement Results and Discussion

Fig. 3.43 presents the performance measured from this UWB LNA fabricated in 0.13μm 1.2V RF CMOS process. The comparisons between the measurement and post-layout simulation are demonstrated for power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S12), noise figure (NF) and stability, shown in Fig. 3.43(a)~(f). Fig.

3.44 indicates the measured third-order intercept point (IIP3) in which the IIP3 can reach 12dBm and 5dBm at 4GHz and 10GHz, respectively. Table 3.5 summarizes all of the performance parameters from our designed UWB LNA, and the comparison with post-layout simulation. The one-to-one comparison between measured data and simulation reveals an obvious degradation in the power gain (S21) while a significant improvement on the linearity in terms of IIP3. The power gain achievable from this UWB LNA is S21=5.0~10.8 dB over the bandwidth of 3.1 ~ 8.1 GHz, which are around 6/3.4 dB lower than the maximum/minimum gain predicted by simulation. As for the linearity, the measured IIP3 are as high as 12/5 dBm at 4/10 GHz, which are much better than the simulated IIP3 of –11/-10 dBm. The degradation of power gain, particularly worse in higher frequencies suggests that shunt peaking method cannot exactly meet the design target from simulation. The process variation induced shift in inductance (Ld) and resistance (Rd) is considered as one major root cause responsible for S21

degradation, and the power loss through the parasitic capacitance to the lossy Si substrate is proposed as the underlying mechanism. This kind of power loss generally increases dramatically when increasing frequency. Referring to (3-8), Cout representing the sum of junction and gate capacitances given as C_out =C_db2+C_gd3+C_dg2+C_gs3(1−K) in (3-11) becomes a critical coupling path for power loss. Besides, Cgs of M2 (Fig.3.1) offers one more path for power loss at high frequency. The input matching circuits are justified by the acceptable match in S11 but somewhat more deviation is revealed in output matching in terms of S22. The measured NF is close to the simulated performance over the broadband of

67

frequencies. This is an important achievement for LNA design and suggests the success of noise shielding technique using guard rings and ground shielding under the pads and transmission lines. Finally, an extensive performance benchmark with the state-of-the-art techniques in latest publications [5, 24, 35, 42, 43] has been done and summarized in Table 3.6. This benchmark indicates that our designed UWB LNA demonstrates the advantages of lower power, lower NF, and higher linearity (IIP3) under comparable gain and bandwidth.

These advantages prove that the proposed UWB LNA can be realized by standard RF CMOS process and applied to UWB system applications.

0 1 2 3 4 5 6 7 8 9 10 11 12

68

69

Fig. 3. 43 UWB LNA chip measured results and comparison with post-layout simulation for (a) power gain (S21) (b) input return loss (S11) (c) output return loss (S22) (d) reverse isolation (S12) (e) noise figure (NF) (f) stability

70

Fig. 3. 44 UWB LNA chip measured third-order intercept point (IIP3) (a) IIP3 =12dBm at 4GHz (b) IIP3= 5dBm at 10GHz

71

Table 3. 5 UWB LNA chip measured performance and comparison with post-layout simulation

Specification Unit Post-sim measure

Frequency GHz 3.1 ~ 10.6 3.3 ~ 8.1

Power (only core LNA) mW 4.7

--Power (total) mW 8.2 8.4

Supply Volatge (V_DD) V 0.9 0.9

Bias current (only core LNA) mA 5.23

--Bias current (total) mA 9.10 9.30

Gain(S₂₁)max / Gain(S₂₁)min dB 17.2 / 8.4 10.8 / 5.0

NF- min / max dB 2.8 / 6.5 3.9 / 4.1

Input Return Loss (S₁₁) dB < -8.3 < -6.7 Output Return Loss (S₂₂) dB < -10.3 < -5.8

IIP3 dBm -11@4GHz,-10@10GHz 12@4GHz,5@10GHz

Reverse isolation (S₁₂) dB < -46.1 < -27.3

Chip size mm² 0.637x0.892

72

Table 3. 6 UWB LNA Performance Benchmark

Table 3. 6 UWB LNA Performance Benchmark

在文檔中 利用順向基極偏壓設計之低功耗低雜訊放大器 (頁 56-0)